MOTOROLA UC3842AN

Order this document by UC3842A/D
The UC3842A, UC3843A series of high performance fixed frequency
current mode controllers are specifically designed for off–line and dc–to–dc
converter applications offering the designer a cost effective solution with
minimal external components. These integrated circuits feature a trimmed
oscillator for precise duty cycle control, a temperature compensated
reference, high gain error amplifier, current sensing comparator, and a high
current totem pole output ideally suited for driving a power MOSFET.
Also included are protective features consisting of input and reference
undervoltage lockouts each with hysteresis, cycle–by–cycle current limiting,
programmable output deadtime, and a latch for single pulse metering.
These devices are available in an 8–pin dual–in–line plastic package as
well as the 14–pin plastic surface mount (SO–14). The SO–14 package has
separate power and ground pins for the totem pole output stage.
The UCX842A has UYLO thresholds of 16 V (on) and 10 V (off), ideally
suited for off–line converters. The UCX843A is tailored for lower voltage
applications having UVLO thresholds of 8.5 V (on) and 7.6 V (off).
• Trimmed Oscillator Discharge Current for Precise Duty Cycle Control
•
•
•
•
•
•
•
•
HIGH PERFORMANCE
CURRENT MODE
CONTROLLERS
N SUFFIX
PLASTIC PACKAGE
CASE 626
8
1
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
14
1
PIN CONNECTIONS
Current Mode Operation to 500 kHz
Automatic Feed Forward Compensation
Latching PWM for Cycle–By–Cycle Current Limiting
Internally Trimmed Reference with Undervoltage Lockout
High Current Totem Pole Output
Compensation 1
8
Vref
Voltage Feedback 2
7
VCC
Current Sense 3
6
Output
RT/CT 4
5
Gnd
Undervoltage Lockout with Hysteresis
Low Startup and Operating Current
(Top View)
Direct Interface with Motorola SENSEFET Products
Compensation
1
14 Vref
NC
2
13 NC
Voltage Feedback
3
12 VCC
NC
4
11 VC
Current Sense
5
10 Output
NC
6
9
Gnd
RT/CT
7
8
Power Ground
Simplified Block Diagram
VCC
7(12)
(Top View)
Vref
5.0V
Reference
8(14)
R
Vref
Undervoltage
Lockout
R
RTCT
2(3)
Output
Compensation
1(1)
ORDERING INFORMATION
VC
Output
Latching
PWM
+
–
Error
Amplifier
6(10)
Power
Ground
5(8)
Current
Sense
3(5) Input
Gnd
Device
Operating
Temperature Range
5(9)
Pin numbers in parenthesis are for the D suffix SO–14 package.
SO–14
UC3842AD
UC3843AD
UC3842AN
TA = 0° to +70°C
SO–14
Plastic
UC3843AN
Plastic
UC2842AD
SO–14
UC2843AD
UC2842AN
TA = – 25° to +85°C
UC2843AN
 Motorola, Inc. 1996
MOTOROLA ANALOG IC DEVICE DATA
Package
7(11)
Oscillator
4(7)
Voltage
Feedback
Input
VCC
Undervoltage
Lockout
SO–14
Plastic
Plastic
Rev 1
1
UC3842A, 43A UC2842A, 43A
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
(ICC + IZ)
30
mA
Output Current, Source or Sink (Note 1)
IO
1.0
A
Output Energy (Capacitive Load per Cycle)
W
5.0
µJ
Current Sense and Voltage Feedback Inputs
Vin
– 0.3 to + 5.5
V
Error Amp Output Sink Current
IO
10
mA
PD
RθJA
862
145
mW
°C/W
PD
RθJA
1.25
100
W
°C/W
Operating Junction Temperature
TJ
+ 150
°C
Operating Ambient Temperature
UC3842A, UC3843A
UC2842A, UC2843A
TA
Total Power Supply and Zener Current
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction–to–Air
N Suffix, Plastic Package
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction–to–Air
Storage Temperature Range
°C
0 to + 70
– 25 to + 85
Tstg
°C
– 65 to + 150
ELECTRICAL CHARACTERISTICS (VCC = 15 V, [Note 2], RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh [Note 3],
unless otherwise noted.)
UC284XA
Characteristics
UC384XA
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Vref
4.95
5.0
5.05
4.9
5.0
5.1
V
Line Regulation (VCC = 12 V to 25 V)
Regline
–
2.0
20
–
2.0
20
mV
Load Regulation (IO = 1.0 mA to 20 mA)
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = 25°C)
Regload
–
3.0
25
–
3.0
25
mV
Temperature Stability
TS
–
0.2
–
–
0.2
–
mV/°C
Total Output Variation over Line, Load, Temperature
Vref
4.9
–
5.1
4.82
–
5.18
V
Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C)
Vn
–
50
–
–
50
–
µV
Long Term Stability (TA = 125°C for 1000 Hours)
S
–
5.0
–
–
5.0
–
mV
ISC
– 30
– 85
– 180
– 30
– 85
– 180
mA
47
46
52
–
57
60
47
46
52
–
57
60
Output Short Circuit Current
OSCILLATOR SECTION
Frequency
TJ = 25°C
TA = Tlow to Thigh
fosc
kHz
Frequency Change with Voltage (VCC = 12 V to 25 V)
∆fosc/∆V
–
0.2
1.0
–
0.2
1.0
%
Frequency Change with Temperature
TA = Tlow to Thigh
∆fosc/∆T
–
5.0
–
–
5.0
–
%
Vosc
–
1.6
–
–
1.6
–
V
7.5
7.2
8.4
–
9.3
9.5
7.5
7.2
8.4
–
9.3
9.5
Oscillator Voltage Swing (Peak–to–Peak)
Discharge Current (Vosc = 2.0 V)
TJ = 25°C
TA = Tlow to Thigh
Idischg
mA
NOTES: 1. Maximum Package power dissipation limits must be observed.
2. Adjust VCC above the Startup threshold before setting to 15 V.
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible
Tlow = –20°C for UC3842A, UC3843A
Thigh = +70°C for UC3842A, UC3843A
Tlow = –25°C for UC2842A, UC2843A
Thigh = +85°C for UC2842A, UC2843A
2
MOTOROLA ANALOG IC DEVICE DATA
UC3842A, 43A UC2842A, 43A
ELECTRICAL CHARACTERISTICS (VCC = 15 V, [Note 2], RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh [Note 3],
unless otherwise noted.)
UC284XA
Characteristics
Symbol
Min
VFB
IIB
Unity Gain Bandwidth (TJ = 25°C)
AVOL
BW
Power Supply Rejection Ratio (VCC = 12 V to 25 V)
PSRR
UC384XA
Typ
Max
Min
Typ
Max
2.45
2.5
2.55
–
–0.1
–1.0
65
90
0.7
60
Unit
2.42
2.5
2.58
V
–
–0.1
–2.0
µA
–
65
90
–
dB
1.0
–
0.7
1.0
–
MHz
70
–
60
70
–
ERROR AMPLIFIER SECTION
Voltage Feedback Input (VO = 2.5 V)
Input Bias Current (VFB = 2.7 V)
Open Loop Voltage Gain (VO = 2.0 V to 4.0 V)
Output Current
Sink (VO = 1.1 V, VFB = 2.7 V)
Source (VO = 5.0 V, VFB = 2.3 V)
Output Voltage Swing
High State (RL = 15 k to ground, VFB = 2.3 V)
Low State (RL = 15 k to Vref, VFB = 2.7 V)
dB
mA
ISink
ISource
2.0
–0.5
12
–1.0
–
–
2.0
–0.5
12
–1.0
–
–
VOH
VOL
5.0
–
6.2
0.8
–
1.1
5.0
–
6.2
0.8
–
1.1
AV
Vth
PSRR
2.85
3.0
3.15
2.85
3.0
3.15
V/V
0.9
1.0
1.1
0.9
1.0
1.1
V
–
70
–
–
70
–
IIB
tPLH(in/out)
–
–2.0
–10
–
–2.0
–10
µA
–
150
300
–
150
300
ns
VOL
–
–
13
12
0.1
1.6
13.5
13.4
0.4
2.2
–
–
–
–
13
12
0.1
1.6
13.5
13.4
0.4
2.2
–
–
–
0.1
1.1
–
0.1
1.1
–
50
150
–
50
150
ns
–
50
150
–
50
150
ns
15
7.8
16
8.4
17
9.0
14.5
7.8
16
8.4
17.5
9.0
9.0
7.0
10
7.6
11
8.2
8.5
7.0
10
7.6
11.5
8.2
94
–
96
–
–
0
94
–
96
–
–
0
V
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Notes 4 & 5)
Maximum Current Sense Input Threshold (Note 4)
Power Supply Rejection Ratio
VCC = 12 to 25 V (Note 4)
Input Bias Current
Propagation Delay (Current Sense Input to Output)
dB
OUTPUT SECTION
Output Voltage
Low State (ISink = 20 mA)
Low State (ISink = 200 mA)
High State (ISink = 20 mA)
High State (ISink = 200 mA)
Output Voltage with UVLO Activated
VCC = 6.0 V, ISink = 1.0 mA
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C)
Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C)
V
VOH
VOL(UVLO)
tr
tf
V
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold
UCX842A
UCX843A
Minimum Operating Voltage After Turn–On
UCX842A
UCX843A
Vth
V
VCC(min)
V
PWM SECTION
Duty Cycle
Maximum
Minimum
%
DCmax
DCmin
TOTAL DEVICE
Power Supply Current (Note 2)
Startup:
(VCC = 6.5 V for UCX843A,
(VCC = 14 V for UCX842A) Operating
Power Supply Zener Voltage (ICC = 25 mA)
ICC
VZ
mA
–
–
0.5
12
1.0
17
–
–
0.5
12
1.0
17
30
36
–
30
36
–
V
NOTES: 2. Adjust VCC above the Startup threshold before setting to 15 V.
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible
Tlow = –20°C for UC3842A, UC3843A
Thigh = +70°C for UC3842A, UC3843A
Tlow = –25°C for UC2842A, UC2843A
Thigh = +85°C for UC2842A, UC2843A
4. This parameter is measured at the latch trip point with VFB = 0 V.
∆V Output Compensation
5. Comparator gain is defined as: AV
∆V Current Sense Input
MOTOROLA ANALOG IC DEVICE DATA
3
UC3842A, 43A UC2842A, 43A
Figure 1. Timing Resistor versus
Oscillator Frequency
Figure 2. Output Deadtime versus
Oscillator Frequency
80
% DT, PERCENT OUTPUT DEADTIME
100
20
8.0
5.0
2.0 VCC = 15 V
TA = 25°C
10 k
20 k
50 k
100 k
200 k
500 k
1.0 M
I dischg , DISCHARGE CURRENT (mA)
10
5.0
2.0
1.0
20 k
50 k
100 k
200 k
500 k
fOSC, OSCILLATOR FREQUENCY (Hz)
Figure 3. Oscillator Discharge Current
versus Temperature
Figure 4. Maximum Output Duty Cycle
versus Timing Resistor
100
VCC = 15 V
VOSC = 2.0 V
8.5
8.0
7.5
–25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
90
80
Idischg = 7.2 mA
60
50
40
800
Idischg = 9.5 mA
1.0 k
2.0 k
3.0 k
4.0 k
6.0 k
8.0 k
Figure 6. Error Amp Large Signal
Transient Response
VCC = 15 V
AV = –1.0
TA = 25°C
3.0 V
20 mV/DIV
2.5 V
VCC = 15 V
CT = 3.3 nF
TA = 25°C
RT, TIMING RESISTOR (Ω)
VCC = 15 V
AV = –1.0
TA = 25°C
2.55 V
1.0 M
70
Figure 5. Error Amp Small Signal
Transient Response
2.5 V
2.0 V
2.45 V
0.5 µs/DIV
4
10 k
fOSC, OSCILLATOR FREQUENCY (Hz)
9.0
7.0
–55
20
200 mV/DIV
0.8
VCC = 15 V
TA = 25°C
50
Dmax , MAXIMUM OUTPUT DUTY CYCLE (%)
RT, TIMING RESISTOR (k Ω )
50
0.1 µs/DIV
MOTOROLA ANALOG IC DEVICE DATA
UC3842A, 43A UC2842A, 43A
80
Gain
60
0
30
60
40
90
Phase
20
120
0
150
100
1.0 k
10 k
100 k
1.0 M
180
10 M
0.8
TA = 25°C
0.6
TA = 125°C
0.4
TA = –55°C
0.2
0
Figure 9. Reference Voltage Change
versus Source Current
Figure 10. Reference Short Circuit Current
versus Temperature
–4.0
–8.0
–12
TA = 125°C
–16
TA = 55°C
TA = 25°C
–20
–24
20
40
60
80
100
120
ISC, REFERENCE SHORT CIRCUIT CURRENT (mA)
2.0
4.0
6.0
VO, ERROR AMP OUTPUT VOLTAGE (V)
VCC = 15 V
0
8.0
110
VCC = 15 V
RL ≤ 0.1 Ω
90
70
50
–55
–25
0
25
50
75
100
Figure 11. Reference Load Regulation
Figure 12. Reference Line Regulation
VCC = 15 V
IO = 1.0 mA to 20 mA
TA = 25°C
, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
TA, AMBIENT TEMPERATURE (°C)
, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
Iref, REFERENCE SOURCE CURRENT (mA)
125
VCC = 12 V to 25 V
TA = 25°C
O
O
∆V
VCC = 15 V
1.0
f, FREQUENCY (Hz)
0
0
1.2
2.0 ms/DIV
MOTOROLA ANALOG IC DEVICE DATA
∆V
– 20
10
∆ V ref , REFERENCE VOLTAGE CHANGE (mV)
VCC = 15 V
VO = 2.0 V to 4.0 V
RL = 100 K
TA = 25°C
Vth, CURRENT SENSE INPUT THRESHOLD (V)
100
Figure 8. Current Sense Input Threshold
versus Error Amp Output Voltage
φ, EXCESS PHASE (DEGREES)
A VOL , OPEN LOOP VOLTAGE GAIN (dB)
Figure 7. Error Amp Open Loop Gain and
Phase versus Frequency
2.0 ms/DIV
5
UC3842A, 43A UC2842A, 43A
0
Source Saturation
(Load to Ground)
VCC
–1.0
TA = 25°C
Figure 14. Output Waveform
VCC = 15 V
80 µs Pulsed Load
120 Hz Rate
VCC = 15 V
CL = 1.0 nF
TA = 25°C
90%
–2.0
TA = –55°C
3.0
TA = –55°C
2.0
TA = 25°C
200
400
600
IO, OUTPUT LOAD CURRENT (mA)
50 ns/DIV
800
Figure 16. Supply Current versus
Supply Voltatage
Figure 15. Output Cross Conduction
VCC = 30 V
CL = 15 pF
TA = 25°C
25
20
15
10
UCX843A
I CC , SUPPLY CURRENT
V O , OUTPUT VOLTAGE
0
Gnd
I CC , SUPPLY CURRENT (mA)
0
10%
5
RT = 10 k
CT = 3.3 nF
VFB = 0 V
ISense = 0 V
TA = 25°C
UCX842A
Sink Saturation
(Load to VCC)
20 V/DIV
1.0
100 mA/DIV
V sat , OUTPUT SATURATION VOLTAGE (V)
Figure 13. Output Saturation Voltage
versus Load Current
0
100 ns/DIV
0
10
20
30
40
VCC , SUPPLY VOLTAGE
6
MOTOROLA ANALOG IC DEVICE DATA
UC3842A, 43A UC2842A, 43A
Figure 17. Representative Block Diagram
VCC
VCC
Vref
8(14)
R
Internal
Bias
2.5V
RT
R
3.6V
+
+ –
–
7(12)
36V
+
Reference
Regulator
VCC
UVLO
–
Vin
+
–
VC
7(11)
Vref
UVLO
Output
Q1
Oscillator
4(7)
+
CT
Voltage Feedback
Input
2(3)
Output
Compensation
1(1)
6(10)
T Q
1.0mA
Power Ground
S
+
–
–
+
2R
Error
Amplifier
R
Gnd
Q
R
5(8)
PWM
Latch
1.0V
Current Sense Input
Current Sense
Comparator
3(5)
5(9)
+
–
=
RS
Sink Only
Positive True Logic
Pin numbers in parenthesis are for the D suffix SO–14 package.
Figure 18. Timing Diagram
Capacitor CT
Latch
‘‘Set’’ Input
Output/
Compensation
Current Sense
Input
Latch
‘‘Reset’’ Input
Output
Large RT/Small CT
MOTOROLA ANALOG IC DEVICE DATA
Small RT/Large CT
7
UC3842A, 43A UC2842A, 43A
OPERATING DESCRIPTION
The UC3842A, UC3843A series are high performance,
fixed frequency, current mode controllers. They are
specifically designed for Off–Line and dc–to–dc converter
applications offering the designer a cost effective solution
with minimal external components. A representative block
diagram is shown in Figure 17.
amplifier’s source current (0.5 mA) and the required output
voltage (VOH) to reach the comparator’s 1.0 V clamp level:
Oscillator
The oscillator frequency is programmed by the values
selected for the timing components RT and CT. Capacitor CT
is charged from the 5.0 V reference through resistor RT to
approximately 2.8 V and discharged to 1.2 V by an internal
current sink. During the discharge of CT, the oscillator
generates and internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in
a low state, thus producing a controlled amount of output
deadtime. Figure 1 shows RT versus Oscillator Frequency
and Figure 2, Output Deadtime versus Frequency, both for
given values of CT. Note that many values of RT and CT will
give the same oscillator frequency but only one combination
will yield a specific output deadtime at a given frequency. The
oscillator thresholds are temperature compensated, and the
discharge current is trimmed and guaranteed to within ± 10%
at TJ = 25°C. These internal circuit refinements minimize
variations of oscillator frequency and maximum output duty
cycle. The results are shown in Figures 3 and 4.
In many noise sensitive applications it may be desirable to
frequency–lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 20. For reliable locking, the
free–running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi unit
synchronization is shown in Figure 21. By tailoring the clock
waveform, accurate Output duty cycle clamping can be
achieved.
Current Sense Comparator and PWM Latch
The UC3842A, UC3843A operate as a current mode
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error Amplifier
Output/Compensation (Pin1). Thus the error signal controls
the peak inductor current on a cycle–by–cycle basis. The
current Sense Comparator PWM Latch configuration used
ensures that only a single pulse appears at the Output during
any given oscillator cycle. The inductor current is converted
to a voltage by inserting the ground referenced sense resistor
RS in series with the source of output switch Q1. This voltage
is monitored by the Current Sense Input (Pin 3) and
compared a level derived from the Error Amp Output. The
peak inductor current under normal operating conditions is
controlled by the voltage at pin 1 where:
Error Amplifier
A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical dc
voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz
with 57 degrees of phase margin (Figure 7). The noninverting
input is internally biased at 2.5 V and is not pinned out. The
converter output voltage is typically divided down and
monitored by the inverting input. The maximum input bias
current is –2.0 µA which can cause an output voltage error
that is equal to the product of the input bias current and the
equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provide for external loop
compensation (Figure 30). The output voltage is offset by two
diode drops (≈ 1.4 V) and divided by three before it connects
to the inverting input of the Current Sense Comparator. This
guarantees that no drive pulses appear at the Output (Pin 6)
when Pin 1 is at its lowest state (VOL). This occurs when the
power supply is operating and the load is removed, or at the
beginning of a soft–start interval (Figures 23, 24). The Error
Amp minimum feedback resistance is limited by the
8
Rf(min) ≈
3.0 (1.0 V) + 1.4 V
= 8800 Ω
0.5 mA
V
– 1.4 V
Ipk = (Pin 1)
3 RS
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
Ipk(max) =
1.0 V
RS
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
order to keep the power dissipation of RS to a reasonable
level. A simple method to adjust this voltage is shown in
Figure 22. The two external diodes are used to compensate
the internal diodes yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the Ipk(max) clamp
voltage.
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with a
time constant that approximates the spike duration will
usually eliminate the instability; refer to Figure 26.
MOTOROLA ANALOG IC DEVICE DATA
UC3842A, 43A UC2842A, 43A
PIN FUNCTION DESCRIPTION
Pin
8–Pin
14–Pin
F
Function
i
D
Description
i i
1
1
Compensation
2
3
Voltage
Feedback
3
5
Current Sense
4
7
RT/CT
5
–
Gnd
6
10
Output
7
12
VCC
This pin is the positive supply of the control IC.
8
14
Vref
This is the reference output. It provides charging current for capacitor CT through
resistor RT.
–
8
Power Ground
This pin is a separate power ground return (14–pin package only) that is connected back to the
power source. It is used to reduce the effects of switching transient noise on the control circuitry.
–
11
VC
The Output high state (VOH) is set by the voltage applied to this pin (14–pin package only). With
a separate power source connection, it can reduce the effects of switching transient noise on the
control circuitry.
–
9
Gnd
This pin is the control circuitry ground return (14–pin package only) and is connected back to the
power source ground.
–
2,4,6,13
NC
No connection (14–pin package only). These pins are not internally connected.
This pin is Error Amplifier output and is made available for loop compensation.
This is the inverting input of the Error Amplifier. It is normally connected to the switching power
supply output through a resistor divider.
A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
The Oscillator frequency and maximum Output duty cycle are programmed by connecting
resistor RT to Vref and capacitor CT to ground. Operation to 500 kHz is possible.
This pin is the combined control circuitry and power ground (8–pin package only).
This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced
and sunk by this pin.
Undervoltage Lockout
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional before
the output stage is enabled. The positive power supply
terminal (VCC) and the reference output (Vref) are each
monitored by separate comparators. Each has built–in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator
upper and lower thresholds are 16 V/10 V for the UCX842A,
and 8.4 V/7.6 V for the UCX843A. The Vref comparator upper
and lower thresholds are 3.6V/3.4 V. The large hysteresis
and low startup current of the UCX842A makes it ideally
suited in off–line converter applications where efficient
bootstrap startup techniques are required (Figure 33). The
UCX843A is intended for lower voltage dc to dc converter
applications. A 36 V zener is connected as a shunt regulator
form VCC to ground. Its purpose is to protect the IC from
excessive voltage that can occur during system startup. The
minimum operating voltage for the UCX842A is 11 V and
8.2 V for the UCX843A.
Output
These devices contain a single totem pole output stage
that was specifically designed for direct drive of power
MOSFETs. It is capable of up to ±1.0 A peak drive current and
MOTOROLA ANALOG IC DEVICE DATA
has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull–down resistor.
The SO–14 surface mount package provides separate
pins for VC (output supply) and Power Ground. Proper
implementation will significantly reduce the level of switching
transient noise imposed on the control circuitry. This
becomes particularly useful when reducing the Ipk(max) clamp
level. The separate VC supply input allows the designer
added flexibility in tailoring the drive voltage independent of
VCC. A zener clamp is typically connected to this input when
driving power MOSFETs in systems where VCC is greater that
20 V. Figure 25 shows proper power and control ground
connections in a current sensing power MOSFET
application.
Reference
The 5.0 V bandgap reference is trimmed to ±1.0%
tolerance at TJ = 25°C on the UC284XA, and ± 2.0% on the
UC384XA. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has short
circuit protection and is capable of providing in excess of
20 mA for powering additional control system circuitry.
9
UC3842A, 43A UC2842A, 43A
DESIGN CONSIDERATIONS
Do not attempt to construct the converter on
wire–wrap or plug–in prototype boards. High Frequency
circuit layout techniques are imperative to prevent pulsewidth
jitter. This is usually caused by excessive noise pick–up
imposed on the Current Sense or Voltage Feedback inputs.
Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low–current signal and
high–current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 µF) connected directly to VCC, VC,
and Vref may be required depending upon circuit layout. This
provides a low impedance path for filtering the high frequency
noise. All high current loops should be kept as short as
possible using heavy copper runs to minimize radiated EMI.
The Error Amp compensation circuitry and the converter
output voltage divider should be located close to the IC and
as far as possible from the power switch and other noise
generating components.
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulators closed–loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 19A
shows the phenomenon graphically. At t0, switch conduction
begins, causing the inductor current to rise at a slope of m1.
This slope is a function of the input voltage divided by the
inductance. At t1, the Current Sense Input reaches the
threshold established by the control voltage. This causes the
switch to turn off and the current to decay at a slope of m2 until
the next oscillator cycle. The unstable condition can be
shown if a pertubation is added to the control voltage,
resulting in a small ∆I (dashed line). With a fixed oscillator
period, the current decay time is reduced, and the minimum
current at switch turn–on (t2) is increased by ∆I + ∆I m2/m1.
The minimum current at the next cycle (t3) decreases to (∆I +
∆I m2/m1) (m2/m1). This pertubation is multiplied by m2.m1 on
10
each succeeding cycle, alternately increasing and
decreasing the inductor current at switch turn–on. Several
oscillator cycles may be required before the inductor current
reaches zero causing the process to commence again. If
m2/m1 is greater than 1, the converter will be unstable. Figure
19B shows that by adding an artificial ramp that is
synchronized with the PWM clock to the control voltage, the
∆I pertubation will decrease to zero on succeeding cycles.
This compensation ramp (m3) must have a slope equal to or
slightly greater than m2/2 for stability. With m2/2 slope
compensation, the average inductor current follows the
control voltage yielding true current mode operation. The
compensating ramp can be derived from the oscillator and
added to either the Voltage Feedback or Current Sense
inputs (Figure 32).
Figure 19. Continuous Current Waveforms
(A)
∆I
Control Voltage
m2
m1
Inductor
Current
m2
m1
∆I + ∆I
m2
∆ I + ∆I m
1
Oscillator Period
t1
t0
t2
m2
m1
t3
(B)
Control Voltage
∆I
m3
m1
m2
Inductor
Current
Oscillator Period
t4
t5
t6
MOTOROLA ANALOG IC DEVICE DATA
UC3842A, 43A UC2842A, 43A
Figure 21. External Duty Cycle Clamp and
Multi Unit Synchronization
Figure 20. External Clock Synchronization
Vref
8(14)
R
Bias
RT
RB
6
CT
47
2(3)
+
5
2
+
–
2R
R
EA
5.0k
0.01
4(7)
Bias
5.0k
+
–
+
–
R
Osc
R
3
Q
S
+
–
7
1(1)
5(9)
1.44
f=
(RA + 2RB)C
The diode clamp is required if the Sync amplitude is large enough to
cause the bottom side of CT to go more than 300 mV below ground.
Figure 22. Adjustable Reduction of Clamp Level
Vin
7(12)
5.0Vref
+
–
5.0Vref
Bias
+
R2
2(3)
Q1
S
–
+
2R
R
Q
1.0V
R1
C
RS
5(9)
VClamp =
1.67
+ 0.33 x 10 – 3
R2
+1
R1
+
–
5.0Vref
8(14)
R
Bias
R
+
+
4(7)
+
–
5(9)
EA
R2
+
7(11)
Q1
–
+
2R
R
6(10)
S
Q
R
Comp/Latch
1.0V
5(9)
1.67
Ipk(max) = VClamp
RS
tSoftstart = – In
–
+
–
(11)
S
–
(10) G
Control CIrcuitry
Ground:
To Pin (9)
M
K
(8)
(5)
RS
R2
+1
R1
+
3(5)
1(1)
MPSA63
+
–
S
Q
–
R
+
Comp/Latch
5(8)
RS Ipk rDS(on)
VPin 5 =
rDM(on) + RS
If: SENSEFET = MTP10N10M
RS = 200
Then: Vpin 5 = 0.075 Ipk
D SENSEFET
Vin
(12)
5.0Vref
–
+
–
VClamp
1.0mA
VCC
Vin
+
–
Osc
VClamp =
3600C in µF
Figure 25. Current Sensing Power MOSFET
7(12)
R1
1.0V
Where: 0 ≤ VClamp ≤ 1.0 V
VCC
C
Q
Ipk(max) = VClamp
RS
Figure 24. Adjustable Buffered Reduction of
Clamp Level with Soft–Start
2(3)
R
1(1)
tSoft–Start
R1 R2
R1 + R2
–
+
2R
R
EA
2(3)
1.0M
S
1.0mA
+
–
3(5)
1(1)
+
4(7)
5(8)
R
Comp/Latch
+
–
–
Osc
6(10)
VClamp
EA
+
7(11)
1.0mA
+
–
Bias
R
–
Osc
R
–
+
–
+
8(14)
+
R
R
5(9)
To Additional
UCX84XA’s
RB
Dmax =
RA + 2RB
Figure 23. Soft–Start Circuit
VCC
4(7)
2R
R
EA
2(3)
1
1(1)
8(14)
+
4(7)
5.0k MC1455
C
R
4
8
Osc
External
Sync
Input
8(14)
RA
R
RS
1/4 W
Power Ground
To Input Source
Return
Where: 0 ≤ VClamp ≤ 1.0 V
1–
MOTOROLA ANALOG IC DEVICE DATA
VC
3VClamp
C
R1 R2
R1 + R2
Virtually lossless current sensing can be achieved with the implementation of a
SENSEFET power switch. For proper operation during over current conditions, a
reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 22 and 24.
11
UC3842A, 43A UC2842A, 43A
Figure 26. Current Waveform Spike Suppression
VCC
+
–
+
–
5.0Vref
+
7(11)
+
–
+
–
–
–
7(11)
Rg
–
Q1
Q1
6(10)
6(10)
S
S
–
+
Vin
7(12)
+
+
–
+
VCC
Vin
7(12)
5.0Vref
Figure 27. MOSFET Parasitic Oscillations
Q
R
Comp/Latch
–
+
5(8)
R
Q
R
Comp/Latch
5(8)
3(5)
3(5)
C
RS
RS
Series gate resistor Rg will damp any high frequency parasitic oscillations
caused by the MOSFET input capacitance and any series wiring inductance
in the gate–source circuit.
The addition of the RC filter will eliminate instability caused by the leading
edge spike on the current waveform.
Figure 28. Bipolar Transistor Drive
IB
Figure 29. Isolated MOSFET Drive
VCC
Vin
+
Vin
7(12)
0
Base Charge
Removal
–
5.0Vref
C1
+
+
–
Isolation
Boundary
+
–
+
–
+
0
–
–
Q1
6(1)
6(1)
S
Q
–
R
+
Comp/Latch
5(8)
R
3(5)
NS
RS
RS
50% DC
+
0
–
25% DC
V(pin 1) – 1.4
Ipk =
3 RS
5(8)
3(5) C
ÉÉÉÉ
ÉÉ
ÉÉÉÉ
VGS Waveforms
Q1
7(11)
NP
NS
Np
The totem–pole output can furnish negative base current for enhanced
transistor turn–off, with the addition of capacitor C1.
Figure 30. Latched Shutdown
Figure 31. Error Amplifier Compensation
From VO
8(14)
2.5V
Ri
R
Bias
Rd
R
2(3)
CI
+
–
1(1)
5(9)
1.0mA
EA
Error Amp compensation circuit for stabilizing any current–mode topology except
for boost and flyback converters operating with continuous inductor current.
2R
R
From VO
1(1)
2N
3905
2R
R
EA
Rf
Osc
MCR
101
1.0mA
+
4(7)
2(3)
+
+
–
5(9)
2N
3903
Rp
Cp
2.5V
2(3)
Ri
Rd
CI
Rf
+
1.0mA
+
–
EA
2R
R
1(1)
5(9)
The MCR101 SCR must be selected for a holding of less than 0.5 mA at
TA(min). The simple two transistor circuit can be used in place of the SCR as
shown. All resistors are 10 k.
12
Error Amp compensation circuit for stabilizing current–mode boost and flyback
topologies operating with continuous inductor current.
MOTOROLA ANALOG IC DEVICE DATA
UC3842A, 43A UC2842A, 43A
Figure 32. Slope Compensation
VCC
Vin
7(12)
8(14)
+
–
5.0Vref
R
RT
Bias
MPS3904
+
R
7(11)
Osc
From VO
CT
Ri
Rd
–
+
–
–
4(7)
RSlope
+
+
2(3)
Cf
6(10)
–m
1.0mA
+
–
S
–
+
2R
R
EA
Rf
Q
R
5(8)
Comp/Latch
1.0V
3(5)
m
1(1)
RS
–3.0 m
5(9)
The buffered oscillator ramp can be resistively summed with either the voltage feedback or current sense inputs to provide slope compensation.
Figure 33. 27 Watt Off–Line Flyback Regulator
4.7Ω
+
MDA
202
3300pF
4.7k
250
T1
+
2200
56k
115Vac
L1
MBR1635
1000
+
5.0V RTN
MUR110
1N4935
1N4935
7(12)
+
68
+
+
–
5.0Vref
0.01
+
10k
1000
7(11)
150k
100pF
4.7k
+
–
2.7k
6(10)
+
18k
2(3)
S
–
+
EA
Q
R
5(8)
Comp/Latch
3(5)
Conditions
Results
∆ = 50 mV or ± 0.5%
∆ = 24 mV or ± 0.1%
Load Regulation: 5.0 V
± 12 V
Vin = 115 Vac, Iout = 1.0 A to 4.0 A
Vin = 115 Vac, Iout = 100 mA to 300 mA
∆ = 300 mV or ± 3.0%
∆ = 60 mV or ± 0.25%
Output Ripple:
Vin = 115 Vac
40 mVpp
80 mVpp
Vin = 115 Vac
70%
Efficiency
5.0 V
± 12 V
L3
1N4937
1.0k
Vin = 95 Vac to 130 Vac
5.0 V
± 12 V
–12V/0.3A
L1 – 15 µH at 5.0 A, Coilcraft Z7156.
L2, L3 – 25 µH at 1.0 A, Coilcraft Z7157.
5(9)
Line Regulation:
+
MTP
4N50
470pF
1(1)
Test
12V/0.3A
22Ω
Osc
4700pF
10
+
MUR110
680pF
+
–
4(7)
+
±12V RTN
+
1N4937
Bias
L2
10
47
100
8(14)
+
1000
5.0V/4.0A
0.5Ω
T1 – Primary: 45 Turns # 26 AWG
T1 – Secondary ± 12 V: 9 Turns # 30 AWG
T1 – (2 strands) Bifiliar Wound
T1 – Secondary 5.0 V: 4 Turns (six strands)
T1 – #26 Hexfiliar Wound
T1 – Secondary Feedback: 10 Turns #30 AWG
T1 – (2 strands) Bifiliar Wound
T1 – Core: Ferroxcube EC35–3C8
T1 – Bobbin: Ferroxcube EC35PCB1
T1 – Gap ≈ 0.01” for a primary inductance of 1.0 mH
All outputs are at nominal load currents, unless otherwise noted.
MOTOROLA ANALOG IC DEVICE DATA
13
UC3842A, 43A UC2842A, 43A
OUTLINE DIMENSIONS
8
N SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
5
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–B–
1
4
DIM
A
B
C
D
F
G
H
J
K
L
M
N
F
–A–
NOTE 2
L
C
J
–T–
N
SEATING
PLANE
D
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
–––
10_
0.030
0.040
M
K
G
H
0.13 (0.005)
M
T A
M
B
M
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
(SO–14)
ISSUE F
–A–
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
8
–B–
1
P 7 PL
0.25 (0.010)
7
G
M
M
K
0.25 (0.010)
M
T B
S
M
F
–T–
D 14 PL
B
R X 45 _
C
SEATING
PLANE
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
–––
10_
0.76
1.01
A
S
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.228
0.244
0.010
0.019
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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Opportunity/Affirmative Action Employer.
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14
◊
*UC3842A/D*
MOTOROLA ANALOG IC DEVICE
DATA
UC3842A/D