T PJ3844B / PJ3845B High Performance Current Mode Controller he PJ3844B , PJ3845 series are high performance fixed cycle-by-cycle current limiting , programmable output frequency current mode controllers. This is specifically deadtime, and a latch for single pulse metering. Allowing output deadtimes to be programmed from 50% to 70%. designed for Off-Line and DC-to-DC converter applications offering the designer a cost effective solution with minimal This device is available in 8-pin dual-in-line plastic external components.This integrated circuits feature a packages as well as the 8-pin plastic surface mount (SOP-8). trimmed oscillator for precise duty cycle control, a The SOP-8 package has separate power and ground pins for temperature compensated reference, high gain error amplifier, the totem pole output stage. The PJ3844B is tailored for lower voltage applications current sensing comparator,and a high current totem pole having UVLO thresholds of 16V (on) 10V (off). ThePJ3845B output ideally suited for driving a power MOSFET. is tailored for lower voltage applications having UVLO Also included are protective features consisting of input thresholds of 8.5V(on) and 7.6V(off). and reference undervoltage lockouts each with hysteresis, FEATURES DIP-8 y Trimmed Oscillator Discharge Current for Precise Duty SOP-8 Cycle Control y Current Mode Operation to 500KHz y Automatic Feed Forward Compensation Pin：1. Compensation Pin：2. Voltage Feedback Pin：3. Current Sense Pin：4. RT/CT y Latching PWM for Cycle-By-Cycle Current Limiting y Internally Trimmed Reference with Undervoltage Lockout y High Current Totem Pole Output 5. Gnd 6. Output 7. Vcc 8. Vref ORDERING INFORMATION y Input Undervoltage Lockout with Hystersis y Low Start-Up and Operating Current Device PJ3844/3845BCD PJ3844/3845BCS Operating Temperature (Ambient) Package DIP-8 -20℃ TO +850C SOP-8 SIMPLIFIED BLOCK DIAGRAM Pin numbers adjacent to terminals are for the 8-pin dual-in-line package. Pin numbers in parenthesis are for the SOP-8 package The document contains information on a new product.Specifications and information herein are subject to change without notice. 1-14 2004/11. Rev B PJ3844B / PJ3845B High Performance Current Mode Controller MAXIMUM RATING Parameter Symbol Value Unit Supply Voltage (low impedance source) Vi 30 V Supply Voltage (Ii<30mA) Vi Self Limiting Output Current IO ±1 A Output Energy (capacitive load ) EO 5 V -0.3 to 6.3 mJ 10 mA -65 to +150 ℃ Analog Inputs (pins 2,3 ) Error Amplifier Output Sink Current Storage Temperature Range Tstg * All voltages are with respect to pin 5,all currents are positive into the specified terminal. ELECTRICAL CHARACTERISTICS (VCC = 15V (Note 2), RT =10K, CT=3.3nF, TA=Tlow to Thigh(Note 3) unless otherwise noted) (Unless otherwise stated , these specifications apply for 0<Tamb<70℃；Vi = 15V (Note 5), RT=10K, CT=3.3nF ) Parameter REFERENCE SECTION Output Voltage Symbol VREF Test Conditions Io=1mA,TJ = 25℃ PJ3844B / PJ3845B Min Typ Max Unit 4.90 5.00 5.10 V Line Regulation △VREF 12V<Vi<25V - 6 20 mV Load Regulation △VREF 1<Io<20mA - 6 25 mV - 0.2 0.4 mV/℃ 4.82 - 5.18 V - 50 - mV - 5 25 mV -30 -100 -180 mA 47 52 57 KHz Temperature Stability (Note2) △VREF /△T Total Output Variantion Output Noise Voltage Vn Long Term Stability Output Short Circuit OSCILLATOR SECTION Initial Accuracy Line,Load, Temperature(2) 10Hz<f<10kHz TJ=25℃ (2) Tamb=125℃, 1000Hrs(2) Isc fs TJ=25℃ Voltage Stability 12<Vi<25V - 0.5 3 % Temperature Stability TMIN <Tamb<TMAX (2) - 5 - % - 1.7 - V 2.42 65 0.7 60 2.50 -0.3 90 1.0 70 2.58 -2.0 - V mΑ dB MHz dB 2.0 -0.5 6 -0.8 - V 4.55 4.85 - V - 0.7 1.1 V Amplitude VPIN4 Peak to Peak ERROR AMPLIFIER SECTION Input Voltage (Vo=2.5V) Input Bias Current Unity Gain Bandwidth (2) Supply Voltage Rejection Output Current Sink Source Output Voltage Swing High State Output Voltage Swing Low State V4 V2 IB AVOL B SVR Isink ISource VOH VOL VPIN1=2.5V 2<Vo<4V VPIN2=2.7V, VPIN1=1.1V VPIN2=2.3V, VPIN1=5V VPIN2=2.3V, RL=15KΩ to Ground VPIN2=2.7V, RL=15KΩ to Pin8 2-14 2004/11. Rev B PJ3844B / PJ3845B High Performance Current Mode Controller Parameter Symbol CURRENT SENSE SECTION Current Sense Input Voltage Gain (Note 3 &4 ) Maximum Input Signal Gv V3 Supply VoltageRejection Test Conditions SVR VPIN1=5V(Note 3 ) 12<Vi<25V(Note 3 ) PJ3844B / PJ3845B Min Typ Max Unit 2.8 3.0 3.2 V/V 0.9 1.0 1.1 V - 70 - dB Input Bias Current IB - -2.0 -10 mΑ Delay to Output OUTPUT SECTION Output Voltage Td - 150 300 ns Isink=20mA - 0.1 0.4 Isink=200mA - 1.5 2.2 13 13.5 - 12 13.5 - TJ=25℃, CL=1.0nF (Note2 ) - 50 150 ns TJ=25℃, CL=1.0nF (Note2 ) - 50 150 ns 14.5 16 17.5 V 7.8 8.4 9.0 8.5 10 11.5 7.0 7.6 8.2 DCmax 44 48 50 % Ist - 0.1 0.5 mA - 11 20 mA 30 34 - V Low State VOL High State VOH Output Voltage Rise Time tr Output Voltage Fall Time tf UNDER-VOLTAGE LOCKOUT SECTION Start-Up Threshold PJ3844B PJ3845B Minimum Operating Voltage After Turn-On PJ3844B Isource=20mA Isource=200mA Vth VCC(min) PJ3845B PWM SECTION Max. Duty Cycle TOTAL STANDBY CURRENT Start-Up Current Operating Supply Current Zener Voltage Ii Viz VPIN2=VPIN3=0V Ii=25mA V V Note: 1. Toggle flip flop used only in PJ3844 and PJ3845. 2. These parameters, although guaranteed, are not 100% tested in production. 3. Parameter measured at trip point of latch with VPIN2=0 4. Gain defined as : A = ∆VPIN1 ；0≦VPIN3≦0.8V. ∆VPIN3 5. Adjust Vi above the start threshold before setting at 15V. 3-14 2004/11. Rev B PJ3844B / PJ3845B High Performance Current Mode Controller FIGURE 1-TIMING RESISTOR versus OSCILLATOR FREQUENCY FIGURE 2-OUTPUT DEAD TIME versus OSCILLATOR FREQUENCY FIGURE 3-ERROR AMP SMALL SINGAL TRANSIENT RESPONSE FIGURE 4-ERROR AMP LARGE RESPONSE TRANSIENT RESPONSE FIGURE 5-ERROR AMP OPEN-LOOP GAIN AND PHASE versus FREQUENCY FIGURE 6-CURRENT SENSE INPUT THRESHOLD versus ERROR AMP OUTPUT VOLTAGE 4-14 2004/11. Rev B PJ3844B / PJ3845B High Performance Current Mode Controller FIGURE 7-REFERENCE VOLTAGE CHANGE versus SOURCE CURRENT FIGURE 8-REFERENCE SHORT CIRCUIT CURRENT versus TEMPERATURE FIGURE 9-REFERENCE LOAD REGULATION FIGURE 10-REFERENCE LINE REGULATION FIGURE 11- OUTPUT SATURATION VOLTAGE versus LOAD CURRENT FIGURE 12-OUTPUT WAVEFORM 5-14 2004/11. Rev B PJ3844B / PJ3845B High Performance Current Mode Controller FIGURE 13-OUTPUT CROSS CONDUCTION VOLTAGE FIGURE 14-SUPPLY CURRENT versus SUPPLY PIN FUNCTION DESCRIPTION Pin No. Function Description 1 Compensation 2 Voltage Feedback 3 Current Sense 4 RT/CT 5 Gnd 6 Output 7 Vcc This pin is the positive supply of the control IC. 8 Vref This pin is the reference output . It provides charging current for capacitor CT through resistor RT. This pin is the Error Amplifier output and is made available for loop compensation This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. The Oscillator Frequency and maximum Output duty are programmed by connecting resistor RT to Vref and capacitor CT to ground .Oscillator operation to 1.0MHz is possible. This pin is the combined control circuity and power ground (8-pin package only). This output directly drives the gate of a power MOSFET.Peak current up to 1.0A are sourced and sunk by this pin.The output switchs at one-half the oscillator frequency. 6-14 2004/11. Rev B PJ3844B / PJ3845B High Performance Current Mode Controller FIGURE 17-REPRESENTATIVE BLOCK DIAGRAM Pin numbers adjacent to terminals are for the 8 pin dual-in-line package. Pin numbers in parenthesis are for the SOP-14 package. FIGURE 18-TIMING DIAGRAM UNDERVOLTAGE LOCKOUT Two undervoltage lockout comparators have been The Vref comparator upper and lower thresholds are incorporated to guarantee that the IC is fully functional before 3.6V/3.4V.The large hysteresis and low start-up current of the the output stage is enabled. The positive power supply UC3844B makes it ideally suited in off-line converter terminal (VCC) and the reference output (Vref) are each applications where efficient bootstrap start-up technique monitored built-in (Figure 33). 36 V zener is connected as a shunt regulator from hysteresis to prevent erratic output behavior as their respective VCC to ground.Its purpose is to protect the IC from excessive thresholds are crossed.The VCC comparator upper and lower voltage that can occur during system start-up. The minimum thresholds are 1 8.4 V/7.6 V for the UC3845A operating voltage for the UC3844B is 11V. by separate comparators.Each has 7-14 2004/11. Rev B PJ3844B / PJ3845B High Performance Current Mode Controller Output FIGURE 19-CONTINUOUS CURRENT WAVEFROMS These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFET’s. It is capable of up to ±1.0A peak drive current and has a typical rise and fall time of 50 ns with a 1.0nF load. Additional internal circuitry has been added to keep the Output in a sinking mode whenever an undervoltage lockout is active.This characteristic eliminates the need for an external pull-down resistor. The SOP-8 surface mount package provides separate pins for Vc(output supply) and Power Ground.Proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. Current mode converters can exhibit subharmonic oscillations when operating at a duty cycle greater than 50% with continuous inductor current,This instability is independent of the regulators closed loop characteristics and is caused by the simultaneous operating conditions of fixed frequency and peak current detecting. Figure 19A shows the phenomenon graphically, At t0 , switch conduction begins , causing the inductor current to rise at a slope of m1. This slope is a function of the input voltage divided by the inductance. At t1, the Current Sense Input reaches the threshold established by the control voltage. This causes the switch to turn off and the current to decay at a slope of m2, until the next oscillator cycle. This unstable condition can be shown if a perturbation is added to the control voltage , resulting in a small Δl (dashed line). With a fixed oscillator period, the current decay time is reduced, and the minimum current at switch turn-on(t2) is increased by Δl+Δl m2/m1. The minimum current at the next cycle (t3) decreases to (Δ l+Δl m2/m1)(m2/m1). This perturbation is multiplied by m2/m1 on each succeeding cycle , alternately increasing and decreasing the inductor current at switch turn-on, Several oscillator cycles may be required before the inductor current reaches zero causing the process to commence again. If m2/m1 is greater than 1, the converter will be unstable . Figure 19B shows that by adding an artificial ramp that is synchronized with the PWM clock to the control voltage . the Δ l perturbation will decrease to zero on succeeding cycles. This compensating ramp (m3) must have a slope equal to or slightly greater than m2/2 for stability . With m2/2 slope compensation , the average inductor current follows the control voltage yielding true current mode operation. The compensating ramp can be derived from the oscillator and added to either the Voltage Feedback or Current Sense inputs (Figure 32). This becomes particularly useful when reducing the Ipk(max) clamp level.The separate Vc supply input allows the designer added fiexlbility in tailoring the drive voltage independent of Vcc.A zener clamp is typically connected to this input when driving power MOSFETs in systems where Vcc is greater than 20V. Figure 25 shows proper power and control ground connections in a current sensing power MOSFET application. Reference The 5.0V bandgap reference is trimmed to±2.0% on the UC3844B.Its promary purpose to supply charging current to the oscillator timing capacitor.The reference has short circuit protection and is capable of providing in excess of 20mA for powering additional control system circuitry. Design Considerations Do not attempt to construct the converter on wirewrap or plug-in prototype boards. High frequency circuit layout techniques are imperative to prevent pulsewidth jitter.This is usually caused by excessive noise pick-up imposed on the Current Sense or Voltage Feedback inputs.Noise immunity can be improved by lowering circuit impedances at these points.The printed circuit layout should contain a ground plane with lowcurrent signal and high-current switch and output grounds returning separate paths back to the input filter capacitor.Ceramic bypass capacitors(0.1 μ F) connected directly to Vcc,Vc, and Vref may be required depending upon circuit layout . This provides a low impedance path for filtering the high frequency noised. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise generating components. 8-14 2004/11. Rev B PJ3844B / PJ3845B High Performance Current Mode Controller FIGURE 20-EXTERNAL CLOCK SYNCHRONIZATION FIGURE 21-EXTERNAL DUTY CYCLE CLAMP AND MULTI UNIT SYNCHRONIZATION The diode clamp is required if the Sync amplitude is large enough to the cause the bottom side of CT to go more than 300mV below ground. FIGURE 22-ADJUSTABLE REDUCTION OF CLAMP LEVEL I pk (max) = Vclamp = Vclmap Rs 1.67 R2 + 1 R1 f = (R A + R B ) D MAX = RB R A + 2R B FIGURE 23-SOFT-START CIRCUIT Isoft-Start=3600c in µF Where：≤ Vclmap ≤ 1.0V + 0.33 × 10 1.44 −3 R1 R2 R1 + R2 FIGURE 24-ADJUSTABLE BUFFERED REDUCTION OF CLAMP LEVEL WITH SOFT-STAR FIGURE 25-CURRENT SENSING POWER MOSFET Virtually lossless current sensing can be achieved with the implementation of a SENSEFET power switch.For proper operation during over current conditions.a reduction of the Ipk(max) clamp level must be implemented.Refer to Figure 22 and 24. 9-14 2004/11. Rev B PJ3844B / PJ3845B High Performance Current Mode Controller FIGURE 26-CURRENT WAVEFORM SPIKE SUPPRESSION FIGURE 27-MOSFET PARASITIC OSCILLATIONS The addition of RC filter will eliminate instability caused by the leading edge splik on the current waveform. FIGURE 28-BIPOLAR TRANSISTOR DRIVE FIGURE 29-ISOLATED MOSFET DRIVE The totem-pole output can furnish negative base current for enhanced transistor turn-off,with the additions of capacitor C1. FIGURE 30-LATCHED SHUTDOWN FIGURE 31-ERROR AMPLIFIER COMPENSATION Error Amp compensation circuit for stabilizing any currentmode topology except for boost and flyback converters operating with continuous inductor current. The MCR101 SCR must be selected for a holding of less than 0.5mA at TA (min).The simple two transistor circuit can be used in place of the SCR as shown.All resistors are 10K. Error Amp compensation circuit for stabilizing any currentmode topology except for boost and flyback converters operating with continuous inductor current. 10-14 2004/11. Rev B PJ3844B / PJ3845B High Performance Current Mode Controller FIGURE 32-SLOPE COMPENSATION The buffered oscillator ramp can resistively summed with either the voltage feedback or current sense inputs to provide slope compensation. FIGURE 33-27 WATT OFF-LINE REGULATION T1-Primary:45 Turns #26 AWG Secondary ±12V :9 Turns #30 AWG (2 strands ) Bifiliar Wound L1-15μH at 5.0A, Coilcraft 27156. Secondary 5.0V: 4 Turns (six strands) #26 Hexfiliar Wound L2.L3-25μH at 1.0A, Coilcraft 27157. Secondary Feedback : 10 Turns #30 AWG (2 strands) Bifiliar Wound Core: Ferroxcube EC35-3C8 Bobbin : Ferroxcube EC35PCB1 Gap： ≅ 0.10 ” for a primary inductance of 1.0mH Line Regulation：5.0V =50mV or ±0.5% Vin=95 to 130 Vac Line Regulation：±12V =24mV or ±0.1% Load Regulation：5.0V =300mV or ±3.0% Vin=115Vac, Iout =1.0A to 4.0A Load Regulation：±12V =60mV or ±0.25% Vin=115Vac,Iout=100mA to 300mA Output Ripple：5.0V Vin=115Vac 40mVp-p Output Ripple：±12V 80 Vp-p Efficiency Vin=115Vac 70% All outputs are at nominal load currents unless otherwise noted. 11-14 2004/11. Rev B PJ3844B / PJ3845B High Performance Current Mode Controller FIGURE 21-33 WATT OFF-LINE FLYBACK CONVERTER WITH SOFT-START AND PRIMARY POWER LIMITING T1 Coilcraft 11-464-16, 0.025” gap in each leg TEST CONDITIONS RESULTS Line Regulation 5.0V Vin=95 to 135 Vac, Io=3.0A 20mV 0.40% Line Regulation± 12V Vin=95 to 135 Vac, Io=±0.75A 52mV 0.26% Line Regulation 5.0V Vin=115 Vac, Io=1.0 to 4.0A 476mV 9.5% Line Regulation± 12V Vin=115 Vac, Io=±0.4 to ±0.9A 300mV 2.5% Line Regulation 5.0V Vin=115 Vac, Io=3.0A 45 mVp-p P.A.R.D. Line Regulation± 12V Vin=115 Vac, Io=±0.75A Vin=115 Vac, Io 5.0V=3.0A Vin=115 Vac, Io ±12=±0.75A 75 mV p-p P.A.R.D. Efficiency 74% Baobbin： Coilcraft 37-573 Windings： Primary, 2 each: 75 turns #26 Awg Bifilar wound Feedback： 15 turns #26 Awg Secondary , 5.0V： 6 turns #22 Awg Bifiar wound Secondary , 5.0V： 14 turns #24 Awg Bifiar wound L1 Coilcraft Z7156. 15μF @ 5.0A L2,L3 Coilcraft Z7157. 25μF @ 1.0A 12-14 2004/11. Rev B PJ3844B / PJ3845B High Performance Current Mode Controller OPERATING DESCRIPTION The UC3844B series are high performance, fixed frequency, current mode controllers, They are specifically designed for Off-Line and DC-to-DC converter applications offering the designer a cost effective solution with minimal external components . A representative block diagram is shown in Figure 17. OSCILLATOR The oscillator frequency is programmed by the values selected for the timing components RT and CT . Capacitor CT is charged from the 5.0V reference through resistor RT to approximately 2.8V and discharge to 1.2V by an internal current sink.During the discharge of CT , the oscillator generates an internal blanking pulse that holds the center input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. Figure 1 shows RT versus Oscillator Frequency and Figure 2, Output Deadtime versus Frequency, both for given values of CT . Note that many values of RT and C T will give the same oscillator frequency but only onne combination will yield a specific output deadtime at a given frequency. The oscillator thresholds are temperature compensated, and the discharge current is trimmed and guaranteed to within ±10% at TJ =25 ℃. These internal circuit refinements minimum variations of oscillator frequency and maximum output duty cycle. The results are shown in Figure 3 and 4. In many noise sensitive applications it may be desirable to frequency-lock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 20. For reliable locking. The free-running oscillator frequency should be set about 10% less than the clock frequency . A method for multi unit synchronization is shown in Figure 21. By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved. ERROR AMPLIFIER A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical DC voltage gain of 90dB, and a unity gain bandwidth of 1.0MHz with 57 degrees of phase margin (Figure 7). The non-inverting input is internally biased at 2.5V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is -2.0μA which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. The Error Amp Output (Pin 1) is provided for external loop compensation (Figure 31). The output voltage is offset by two diode drops (≈1.4V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Output(Pin 6) when Pin 1 is at its lowest state (VOL). This occurs when the power supply is operating and the load is removed, or at the beginning of a soft-start interval (Figure 23,24). The Error Amp minimum feedback resistance is limited by the amplifier's source current (0.5mA) and the required output voltage (VOH) to reach the comparator’s 1.0V clamp level: Rf(MIN) = [3.0 (1.0V)+1.4V] / 0.5mA = 8800Ω CURRENT SENSE COMPARATOR AND PWM LATCH The UC3844B operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin 1). Thus the error signal controls the peak inductor current on a cycle-by-cycle basis. The Current Sense Comparator PWM Latch configuration used ensures that only a single appears at the Output during any given oscillator cycle. The inductor current is converted to a voltageby inserting the ground referenced sense resistor RS in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where: IPK = [V(Pin 1) - 1.4V] / 3RS Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost, Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0V. Therefore the maximum peak switch current is: IPK (MAX) = 1.0V / RS When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 22. The two external diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the IPK (max) clamp voltage. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability: refer to Figure 26. 13-14 2004/11. Rev B PJ3844B / PJ3845B High Performance Current Mode Controller DIP-8 Mechanical drawing 1.Top View 2.Side View A DIP-8 DIMENSION 8 B 1 4 MIN MAX MIN MAX A 8.85 9.05 0.348 0.356 B 6.30 6.40 0.248 0.252 C 3.65 3.95 0.143 0.156 D 0.45 0.55 0.017 0.022 C F 7.75 8.00 0.305 0.315 G 0.20 0.30 0.007 0.012 - H G 0.10BSC 2.54BSC E F INCHES MILLIMETERS DIM 5 10° - 10° H E D SOP-8 Mechanical drawing 1.Top View 2.Side View SOP-8 DIMENSION A G 8 5 B 1 C 4 H DIM MILLIMETERS INCHES MIN MAX MIN MAX A 4.80 5.00 0.189 0.197 B 3.80 4.00 0.150 0.157 C 5.80 6.20 0.228 0.244 D 1.40 1.50 0.055 0.059 E 0.33 0.51 0.013 0.020 F 0.05BSC 1.27BSC G 0.19 0.25 0.007 0.010 H 0.40 1.27 0.016 0.050 0° 8° 0° 8° D E 14-14 2004/11. Rev B