TA1296FN Preliminary TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic TA1296FN Down-Converter IC with PLL for Satellite Tuner The TA1296FN is a wideband down-converter which can operate at input frequency ranging from 850 MHz to 2200 MHz. Intended primarily for use in satellite tuners, this IC includes an oscillator, a mixer, an IF amplifier and a PLL. The I2C bus data format is used as the data control format. The supply voltage of 5.0 V helps minimize the tuner’s power dissipation, while the compact 30-pin SSOP package allows the tuner to be kept small. Features · Supply voltage: 5.0 V (typ.) · Wide input frequency range · Low phase noise oscillator · Standard I2C bus format control · 4-MHz (X’tal) buffer output pin · Reference oscillator input change-over switch [X’tal or external input] · 33-V high-voltage tuning amplifier built-in · 3-bit input port (for read mode) · 2-bit band switch drive transistor (for write mode) · 5-level AD converter · Frequency step: 62.5 kHz or 125 kHz (for 4-MHz X’tal) · 4-address setting via address selector · Power-on reset circuit · ×1/2 prescaler · Flat compact package: SSOP30-P-300-0.65 (0.65-mm pitch) Weight: 0.17 g (typ.) Power-On Reset Operation Conditions · · · · · Frequency step: 125 kHz Charge pump output current: ±50 mA Counter data: all [0] Band driver: OFF Tuning amplifier: OFF Note 1: This device can easily be damaged by high voltages or electrical fields. For this reason, please handle it with care. 1 2002-02-12 TA1296FN VCC4 GND7 RF in2 RF in1 GND6 ADR set XO SW GND5 VCC3 IF out VCC3 Band2 out Band1 out SDA in/out SCL in Block Diagram 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADR XO-SW Band Driver Programmable Counter 1/32 1/33 1/2 Data Interface Phase Comparator Divider ADC Comparator 8 VCC1 OSC-E OSC-B GND2 Vt-out NF X’tal 2 9 10 11 12 13 14 15 I-P3 in 7 I-P2 in 6 I-P1 in 5 ADC in 4 GND3 3 XO buff out 2 VCC2 1 GND1 Charge Pump 2002-02-12 TA1296FN Pin Functions Pin No. Pin Name Function Interface 1 GND1 Ground pin for oscillator circuit block 2 VCC1 Power supply pin for local oscillator circuit block ¾ 2 4 3 Oscillator 3 Local oscillator circuit 4 GND1 5 GND2 ¾ Ground pin for oscillator circuit block VCC2 6 Vt Output 6 50 W Tuning voltage output pin with built-in tuning amplifier GND3 7 NF 7 VCC2 8 (4-MHz input) 8 5 kW Crystal oscillator input Reference Input 5 kW 1 kW VCC2 1 kW Can be switched between X’tal oscillator and external input using pin 24 (XO switch). GND3 9 VCC2 ¾ Power supply pin for PLL circuit block 10 Reference signal buffer output Buffer output pin for reference signal 5 kW 5 kW VCC2 10 GND3 11 GND3 Ground pin for PLL circuit block 3 ¾ 2002-02-12 TA1296FN Pin No. Pin Name Function Interface VCC2 2 kW AD converter pin 12 ADC Converts input voltage into digital data. 12 GND3 13 I-P1 VCC2 13, 15 15 I-P3 GND3 Comparator status can be checked in Read Mode. VCC2 14 14 I-P2 GND3 VCC2 SCL Input 2 Input pin for I C bus serial clock data 16 1 kW 100 W 16 GND3 VCC2 17 GND3 4 20 W 1 kW 100 W Input/Output 2 Input/output pin for I C bus serial clock data 70 kW SDA 17 2002-02-12 TA1296FN Pin No. Pin Name Function Interface VCC2 18 Band 1 Output 18, 19 Output can be controlled by setting band switch data. 19 Band 2 Output GND3 20 GND4 Ground pin for IF amplifier circuit block ¾ VCC3 21 IF Output 21 IF output pin GND4 22 VCC3 Power supply pin for IF amplifier circuit block ¾ 23 GND5 Ground pin for IF amplifier circuit block ¾ Determines reference signal input. XO Switch If connected to ground: X’tal oscillator. 24 1 kW 25 kW 24 25 kW VCC2 If open or connected to VCC2: external input GND3 25 ADR Set 150 kW The address for hardware bit setting can be selected by applying voltage to this pin. 100 W VCC2 25 1 kW 50 kW 4 programmable address can be programmed. 100 W GND3 26 GND6 Ground pin for mixer circuit block 5 ¾ 2002-02-12 TA1296FN 27 Pin Name Function Interface RF Input1 27 RF signal input pin Input can be either balanced or unbalanced. 28 28 3 kW Pin No. 3 kW RF Input2 GND7 29 GND7 Ground pin for mixer circuit block ¾ 30 VCC4 Power supply pin for mixer circuit block ¾ 6 2002-02-12 TA1296FN Absolute Maximum Ratings (Ta = 25°C) Parameter Pin No. Symbol Rating 2 VCC1 6 9 VCC2 6 22 VCC3 6 Supply voltage Unit V 30 VCC4 6 Tuning amplifier voltage 6 VBT 38 Power dissipation ¾ PD Operating temperature ¾ Topr -20 to 85 °C Storage temperature ¾ Tstg -55 to 150 °C V 1130 mW (Note 2) Note 2: 50 mm ´ 50 mm ´ 1.6 mm, 40% Cu board If Ta > 25°C, derate this value by 9.1 mW/°C. Recommended Operating Conditions Pin No. Symbol Min Typ. Max Unit 2 Local oscillator block VCC1 4.5 5.0 5.5 V 9 PLL block VCC2 4.5 5.0 5.5 V 22 IF amplifier block VCC3 4.5 5.0 5.5 V 30 Mixer block VCC4 4.5 5.0 5.5 V Electrical Characteristics DC Characteristics (unless otherwise specified, VCC1 = VCC2 = VCC3 = VCC4 = 5 V, Ta = 25°C) When power on, counter data = all [0], VBT = OFF, CP1 = CP0 = 0 and band = all [0] Parameter Symbol Test Circuit ICC1 Power supply current Total Test Condition Min Typ. Max ¾ 5.0 7.5 10.0 ¾ 16.0 20.0 25.5 ICC3 ¾ 16.5 20.0 24.5 ICC4 ¾ 9.5 12.5 16.0 ¾ 47.0 60.0 76.0 ICC2 ICC-total 1 ¾ 7 Unit mA mA 2002-02-12 TA1296FN Down-Converter Block AC Characteristics (unless otherwise specified, VCC1 = VCC2 = VCC3 = VCC4 = 5 V, Ta = 25°C) Symbol Test Circuit Test Condition RF input frequency Mfin ¾ RF input level MPin IF output frequency Parameter IF output impedance (Note 3) Local oscillator frequency Min Typ. Max Unit ¾ 850 ¾ 2200 MHz ¾ ¾ ¾ ¾ -35 dBmW Afin ¾ ¾ 350 ¾ 550 MHz AZout ¾ ¾ 75 ¾ W LO ¾ 1300 ¾ 2700 MHz fRF = 898 MHz 27.5 31 34 fRF = 1598 MHz 27.5 31 34.5 fRF = 2198 MHz 25 29 32.5 fRF = 898 MHz ¾ 9 10.5 fRF = 1598 MHz ¾ 9 11 fRF = 2198 MHz ¾ 11 13 Conversion gain CG 2 (Note 3) Noise figure NF 3 (Note 3) IF output power level Apsat 2 (Note 3) 3rd inter modulation (IF output intercept point) IP3 4 (Note 3) Conversion gain shift CGs 2 (Note 3) Frequency shift (PLL OFF) DfB 2 Phase noise PN 2 (with 10-kHz offset) RF pin LORF 2 LO leak level IF pin LOIF LO leak level 2 (Note 4) Single-end ¾ fRF = 898 MHz 6.5 8.5 ¾ fRF = 1598 MHz 6.5 8.5 ¾ fRF = 2198 MHz 6.5 8.5 ¾ fd = 898 MHz, fud = 903 MHz 15 18.5 ¾ fd = 1598 MHz, fud = 1603 MHz 15 17 ¾ fd = 2198 MHz, fud = 2203 MHz 15 17 ¾ fRF = 898 MHz ¾ ¾ ±2 fRF = 1598 MHz ¾ ¾ ±2 fRF = 2198 MHz ¾ ¾ ±2 fosc = 1300 MHz ¾ ¾ ±4.5 fosc = 2000 MHz ¾ ¾ ±3.5 fosc = 2600 MHz ¾ ¾ ±3.5 fosc = 1300 MHz ¾ -74 -70 fosc = 2000 MHz ¾ -75 -71 fosc = 2600 MHz ¾ -74 -70 fosc = 1300 MHz -40 -37 fosc = 2000 MHz -32 -29 fosc = 2600 MHz -32 -29 fosc = 1300 MHz -28 -20 fosc = 2000 MHz -32 -24 fosc = 2600 MHz -32.5 -27 dB dB dBmW dBmW dB MHz dBc/ Hz dBmW dBmW Note 3: IF output frequency = 402 MHz Note 4: IF output load = 75 W 8 2002-02-12 TA1296FN PLL Block (unless otherwise specified, VCC1 = VCC2 = VCC3 = VCC4 = 5 V, Ta = 25°C) Parameter Symbol Test Circuit Tuning amplifier output voltage (close) Vt out 1 Tuning amplifier maximum current Ivt X’tal negative resistance Test Condition Min Typ. Max Unit VBT = 33 V, RL = 33 kW 0.3 ¾ 33 V 1 VBT = 33 V ¾ ¾ 3 mA XtR 1 XO-SW:GND (X’tal oscillator mode) 1 2.5 ¾ kW X’tal operating range OSCin 1 [NDK (AT-51), 4 MHz used] 3.2 ¾ 4.5 MHz X’tal external input level Xo extl 1 100 ¾ 1000 mVp-p X-ext 1 2 ¾ 6 MHz N ¾ 1024 ¾ 65,535 Logic input low voltage VIL 1 -0.3 ¾ 1.5 Logic input high voltage VIH 1 2.4 ¾ Logic input current (low) I BsL 1 -20 ¾ 10 mA -10 ¾ 20 mA ¾ ¾ 0.4 V CP1 = [0], CP0 = [0] ±35 ±50 ±75 CP1 = [0], CP0 = [1] ±75 ±100 ±145 CP1 = [1], CP0 = [0] ±180 ±240 ±345 CP1 = [1], CP0 = [1] ±375 ±490 ±700 X’tal external input frequency Ratio setting range (Note 4) XO-SW: VCC2 or open 16-bit counter SDA and SCL pins SDA and SCL pins Logic input current (high) I BsH 1 ACK output voltage VACK 1 Charge pump output current Ichg 1 ISINK = 3 mA VCC2 + 0.3 V V mA Band driver drive current IBD 1 B1, B2 ¾ ¾ 10 mA Band driver voltage drop VBDsat 1 B1, B2: IBD = 10-mA drive ¾ ¾ 0.2 V Comparator pin input voltage VCMP 1 IP-1, IP-2, IP-3 0 ¾ 6 V Comparator pin low voltage VLCMP 1 IP-1, IP-2, IP-3 0 ¾ 1.5 V Comparator pin high voltage VHCMP 1 IP-1, IP-2, IP-3 2.7 ¾ 6 V 350 500 ¾ mVp-p 1-kW, 10-pF load Xo buffer output level Xo out 1 X’tal: NDK (AT-51), 4 MHz used. 4-MHz level monitored on oscilloscope using FET probe (1 MW, 1.9 pF). 9 2002-02-12 TA1296FN Bus Line Characteristics Parameter Symbol Test Circuit Test Condition Min Typ. Max Unit SCL clock frequency fSCL 0 ¾ 100 kHz Bus free time between a STOP and START conditions tBUF 4.7 ¾ ¾ ms tHD; STA 4 ¾ ¾ ms SCL clock low period tLOW 4.7 ¾ ¾ ms SCL clock high period tHIGH 4 ¾ ¾ ms 4.7 ¾ ¾ ms Hold time for repeated START condition ¾ Please refer to data timing chart. Set-up time for repeated START condition fSU; STA Data hold time tHD; DAT 0 ¾ ¾ ms Data set-up time tSU; DAT 250 ¾ ¾ ns Rise time for SDA and SCL signals tR ¾ ¾ 1000 ns Fall time for SDA and SCL signals tF ¾ ¾ 300 ns tsU; STO 4 ¾ ¾ ms Set-up time for STOP condition SDA tBUF tLOW tR tF tHD; STA SCL tHD; STA P tHD; DAT tHIGH S Figure 1 tSU; STO tSU; DAT tSU; STA Sr P 2 I C Bus Data Timing Chart (rising-edge timing) 10 2002-02-12 TA1296FN Test Conditions (1) Conversion gain RF input level = -40dBmW (2) Noise figure NF meter direct-reading value (DSB measurement) (3) IF output power level Measure maximum IF output level. (4) 3rd inter modulation · fd (fd input level = -40dBmW) · fud = fd + 5 MHz (fud input level = -40dBmW) Calculate IF output intercept point as follows: IP3 = S/(N - 1) + P [dBmW] S: suppression level N: 3 P: IF output level (5) Conversion gain shift Conversion gain shift is defined as change in conversion gain when supply voltage exceeds ranges VCC = 5 V to 4.5 V or VCC = 5 V to 5.5 V. (6) Frequency shift (PLL OFF) Frequency shift is defined as change in oscillator frequency when supply voltage exceeds ranges VCC1 = 5 V to 4.5 V or VCC1 = 5 V to 5.5 V. (7) Phase noise (offset = 10 kHz) Measure phase noise at 10-kHz offset. (8) RF pin local-leak level Measure worst-case local-leak level for RF pin (with IF output pin open). (9) IF pin local-leak level Measure worst-case local-leak level for IF pin (with RF input pins shorted using 50-W resistor). 11 2002-02-12 TA1296FN PLL Block 2 --I C Bus Communications Control-The TA1296FN conforms to Standard Mode I2C bus format. I2C Bus Mode allows two-way bus communication using Write Mode (for receiving data) and Read Mode (for processing status data). Write Mode or Read Mode can be selected by setting the least significant bit (R/W bit) of the address byte. If the least significant address bit is set to 0, Write Mode is selected; if it is set to 1, Read Mode is selected. Address can be set using the hardware bits. 4 programmable address can be programmed. Using this setting, multiple frequency synthesizers can be used on the same I2C bus line. The address for the hardware bit setting can be selected by applying voltage to the address setting pin (ADR-pin 25). The address is selected according to the setting of these bits. During acknowledgment of receipt of a valid address byte, the serial data (SDA) line is Low. If Write Mode is currently selected, when the data byte is programmed, the serial data (SDA) line will be Low during the next acknowledgment. A) Write mode (setting command) When Write Mode is selected, byte 1 holds address data; byte 2 and byte 3 hold frequency data; byte 4 holds frequency data, the divider ratio setting and function setting data; and byte 5 holds output port data. Data is latched and transferred at the end of byte 3, byte 4 and byte 5. Byte 2 and byte 3 are latched and transferred as a byte pair. Once a valid address has been received and acknowledged, the data type can be determined by reading the first bit of the next byte. That is, if the first bit is 0, the data is frequency data; if it is 1, the data is function-setting or band output data. Additional data can be input without the need to transmit the address data again until the I2C bus STOP condition is detected (e.g. a frequency sweep using additional frequency data is possible). If a data transmission is aborted, data programmed before the abort remains valid. [[BYTE 1]] The address data for byte 1 can be set using the hardware bit. The hardware bit can be set by applying a voltage to the address-setting pin (ADR: pin 25). [[BYTE 2, BYTE 3, (N15) in BYTE 4]] Byte 2 , byte 3 and N15 of byte 4 control the 16-bit programmable counter ratio and are stored in the 16-bit shift register together with frequency setting counter data. The program frequency can be calculated using the following formula: fosc = 2 ´ fr ´ N fosc: Program frequency fr: Phase comparator reference frequency N: Counter total divider ratio fr is calculated from the crystal oscillator frequency and the reference frequency divider ratio set in byte 4 (the control byte). (fr = X’tal oscillator frequency/reference divider ratio) The reference frequency divider ratio can be set to 1/64 or 1/128. When a 4-MHz crystal oscillator is used, fr = 62.5 kHz or 31.25 kHz. The respective step frequencies are 125 kHz and 62.5 kHz. [[BYTE 4]] Byte 4 is a control byte used for selecting functions. Bit 4 (CP1) and bit 5 (CP0) determine the output current of the charge pump circuit. If bit 4 and bit 5 are set to [CP1]:[CP0] = 00, the output current is set to ±50 mA. If bit 4 and bit 5 are set to [CP1]:[CP0] = 01, the output current is set to ±100 mA. If bit 4 and bit 5 are set to [CP1]:[CP0] = 10, the output current is set to ±240 mA. If bit 4 and bit 5 are set to [CP1]:[CP0] = 11, the output current is set to ±490 mA. Bit 7 (Rs) can be used to set the X’tal reference frequency divider ratio. If bit 7 is set to 0, the X’tal divider ratio is 1/128 (with a frequency step of 62.5 kHz). If it is set to 1, the X’tal divider ratio is 1/64 (with a frequency step of 125 kHz). Bit 8 (OS) can be used to set the charge pump driver amplifier output setting. If bit 8 is set to 0, the output is ON (the normal setting). If it is set to 1, the output is OFF. 12 2002-02-12 TA1296FN [[BYTE 5]] Byte 5 can be used to select Test Mode and to control the output ports (band 1 and band 2). Bit 1, bit 2 and bit 3 (T2, T1 and T0) can be used to set up Test Mode. These bits determine the phase comparator reference signal output and the counter divider output. Bit 5 (for B2) and bit 8 (for B1) can be used to control the output ports. When either of these bits is set to 0, the corresponding port is turned OFF. When either of these bits is set to 1, the corresponding port is turned ON. Each output port can be driven at less than 10 mA. B) Read mode (status request) When Read Mode is selected, the power-on reset operation status, phase comparator lock detector output status, comparator input port status and 5-level AD converter pin input voltage status are output to the master device. Bit 1 (POR) indicates the power-on reset operation status. When the power supply voltage VCC2 is cut off, this bit is set to 1. Bit 1 is reset to 0 when a voltage of 3 V or higher is applied to VCC2 and transmission is requested in Read Mode. At this point the new status is output. (bit 1 is also set to 1 when VCC2 is turned ON.) Bit 2 (FL) indicates the phase comparator lock status. When the phase comparator is locked, 1 is output. When the phase comparator is unlocked, 0 is output. Bit 3, bit 4 and bit 5 (I-P3, I-P2, I-P1) indicate the input comparator status. I-P3, I-P2 and I-P1 indicate the status of input ports I-P3, I-P2 and I-P1 (pins 13, 14 and 15) respectively. The input voltage status for each comparator input port pin is output to the master device. High is indicated by 1. Low is indicated by 0. High represents a voltage of above 2.7 V applied to the corresponding pin. Low represents an applied voltage of below 1.5 V. Bit 6, bit 7 and bit 8 (A2, A1 and A0) indicate the status of the five-level AD converter. The voltage applied to the AD converter input pin (pin 3) is output after being resolved to one of five levels. To see the bit values output for the five resolution levels and to see how these levels correspond to the voltage applied to the AD converter input pin (ADCin-pin 12), please refer to the table entitled A2, A1 and A0: Five-level AD converter status (e.g. the AFT output voltage data can be given to the master device). Data Format A) Write mode MSB LSB 1 Address Byte 1 1 0 0 0 MA1 MA0 R/W = 0 ACK 2 Divider Byte 1 0 N14 N13 N12 N11 N10 N9 N8 ACK 3 Divider Byte 2 N7 N6 N5 N4 N3 N2 N1 N0 ACK (L) 4 Control Byte 1 ´ N15 CP1 CP0 ´ Rs OS ACK (L) 5 Band SW Byte T2 T1 T0 ´ B2 ´ ´ B1 ACK (L) ´: Don’t care ACK: Acknowledged (L): Latch and transfer timing B) Read mode MSB 1 Address Byte 2 Status Byte LSB 1 1 0 0 0 MA1 MA0 R/W = 1 ACK POR FL I-P3 I-P2 I-P1 A2 A1 A0 ¾ ACK: Acknowledged 13 2002-02-12 TA1296FN Data Specifications · MA1 and MA0: programmable hardware address bits MA1 MA0 Voltage Applied to Address Pin 0 0 0 to 0.1VCC2 0 1 OPEN or 0.2VCC2 to 0.3VCC2 1 0 0.4VCC2 to 0.6VCC2 1 1 0.9VCC2 to VCC2 · N15-N0: programmable counter data · CP1 and CP0: charge pump output current setting · · CP1 CP0 Output Current (mA) 0 0 ±50 (typ.) 0 1 ±100 (typ.) 1 0 ±240 (typ.) 1 1 ±490 (typ.) Rs: reference frequency divider ratio selection bit. Rsa Divider Ratio Step Frequency Phase Comparator Reference Frequency 0 1/128 62.5 kHz 31.25 kHz 1 1/64 125 kHz 62.5 kHz OS: tuning amplifier control bit 0: Tuning amplifier ON (normal operation) 1: Tuning amplifier OFF · T2, T1 and T0: test mode setting bits Parameter T2 T1 T0 Notes 0 0 ´ ¾ OFF 0 1 ´ Charge pump is OFF. SINK 1 1 0 Only charge pump sink current is ON. SOURCE 1 1 1 Only charge pump source current is ON. Reference signal output 1 0 0 Reference signal output (check output: ADC) 1/2 counter divider output 1 0 1 1/2 counter output (check output: ADC) Phase comparator test 0 0 1 Normal operation Charge pump Comparative signal input: SDA Reference signal input: SCL ´: DON’T CARE Note 5: When Test Mode is used, the tuning amplifier control bit OS is 0, signifying normal operation. To test the counter divider output, programmable counter data input is required. 14 2002-02-12 TA1296FN · B1 and B2: band output 0: OFF 1: ON · POR: power-on reset flag 0: Normal operation 1: Reset · FL: lock detect flag 0: Unlocked 1: Locked · I-P1, I-P2 and I-P3: comparator input status 0: Input voltage is below 1.5 V. 1: Input voltage is above 2.7 V. · A2, A1 and A0: five-level AD converter status Voltage Applied to ADC Pin A2 A1 A0 0.60VCC2 to VCC2 1 0 0 0.45VCC2 to 0.60VCC2 0 1 1 0.30VCC2 to 0.45VCC2 0 1 0 0.15VCC2 to 0.30VCC2 0 0 1 0 V to 0.15VCC2 0 0 0 Accuracy is ±(0.03 ´ VCC2) · XO-SW: reference signal changeover switch Pin 24 Status Input Method GND X’tal input VCC2 or open External input 15 2002-02-12 TA1296FN Test Circuit 1 DC Characteristics VCC4 (5 V) ADR set VCC2/Open 30 29 28 27 26 25 24 SDA IBD1 A A ICC3 0.01 mF XO-SW 1 nF 1 nF 0.01 mF A ICC4 R VCC3 (5 V) VCC2/Open: Extenal input GND: X’tal 23 22 SCL V Vsat NC 21 20 19 18 17 16 ADR XO-SW Band Driver Programmable Counter 1/32 1/33 1/2 Data Interface Phase Comparator Divider ADC Comparator 3 4 NC NC 5 6 7 1 nF A ICC1 VCC1 (5 V) 8 9 NC NF 10 11 12 13 14 15 ADC in I-P1 I-P2 I-P3 1 nF 2 0.01 mF *X’tal 22 pF 1 0.01 mF Charge Pump 1 kW A ICC2 10 pF 4 MHz out EXT.in VCC2 (5 V) X’tal: NDK (AT-51), 4 MHz 16 2002-02-12 TA1296FN Test Circuit 2 AC Characteristics 5V VCC2/Open IF out 29 28 0.1 mF 1 nF 1 nF 1 nF 0.1 mF 30 XO-SW 27 26 25 24 23 22 B2 B1 SDA 19 18 17 1 nF VCC2/Open: Extenal input GND: X’tal 21 20 SCL 390 W ADR set 390 W RF in 16 ADR XO-SW Band Driver Programmable Counter 1/32 1/33 1/2 Data Interface Phase Comparator Divider ADC Comparator 47 kW 10 11 12 13 14 15 ADC in I-P1 I-P2 I-P3 1 nF 9 0.01 mF 4.7 nF 8 *X’tal 22 pF 7 13 kW 6 5 pF 10 kW 4.7 kW 1T379 1T379 L 5 4 MHz out 1 nF 33 V 4 4.7 nF 3 0.1 mF 10 kW 2 47 pF 1 0.1 mF Charge Pump X’tal: NDK (AT-51), 4 MHz 17 2002-02-12 TA1296FN Test Circuit 3 Measuring Noise Figure Noise Figure Meter out in DUT 28 21 75 W-50 W impedance transformer Test Circuit 4 Measuring 3rd Inter Modulation fd Signal Generator 1 28 DUT 21 in Spectrum Analyzer 75 W-50 W impedance transformer Signal Generator 2 fud 18 2002-02-12 TA1296FN 2 I C-Bus Control Summary The bus control format of TA1296FN conforms to the Philips I2C-bus control format. Data Transmission Format S Slave address 0 A SUB address 7 bits A Data 8 bits MSB MSB A P 8 bits MSB S: Start condition P: Stop condition A: Acknowledge (1) Start/stop condition Serial Data Serial Clock (2) S P Start condition Stop condition Bit transfer Serial Data Serial Clock Serial data unchanged. (3) Serial data can be changed. Acknowledge Serial Data From Master Device High-Impedance Serial Clock From Slave High-Impedance Serial Clock From Master Device 1 8 9 S 19 2002-02-12 TA1296FN (4) Slave address A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 0 0 * * 0 Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Tights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Handling Precautions 1. The device should not be inserted into or removed from the test jig while a voltage is being applied to it: otherwise the device may be degraded or break down. Also, do not abruptly increase or decrease the power supply to the device (see figure 1). Overshoot or chattering in the power supply may cause the IC to be degraded. To avoid this, filters should be placed on the power supply line. Supply voltage 6 V (VCC1, VCC2, VCC3, VCC4) 38 V (VBT) 90% 10% 1 ms Time Figure 1 2. The peripheral circuits described in this datasheet are given only as system examples for evaluating the device’s performance. TOSHIBA intend neither to recommend the configuration or related values of the peripheral circuits nor to manufacture such application systems in large quantities. Please note that the high-frequency characteristics of the device may vary depending on the external components, the mounting method and other factors relating to the application design. Therefore, the evaluation of the characteristics of application circuits is the responsibility of the designer. TOSHIBA only guarantee the quality and characteristics of the device as described in this datasheet and do not assume any responsibility for the customer’s application design. 3. In order to better understand the quality and reliability of TOSHIBA semiconductor products and to incorporate them into designs in an appropriate manner, please refer to the latest Semiconductor Reliability Handbook (integrated circuits) published by TOSHIBA Semiconductor Company. This handbook can also be viewed on-line at the following URL: <http://www.semicon.toshiba.co.jp/noseek/us/sinrai/sinraifm.htm>. 20 2002-02-12 TA1296FN Package Dimensions Weight: 0.17 g (typ.) 21 2002-02-12 TA1296FN RESTRICTIONS ON PRODUCT USE 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 22 2002-02-12