TA1322FN Preliminary TOSHIBA Bipolar Linear Integrated Circuit Silicon Monolithic TA1322FN Down-Converter IC with PLL for Satellite Tuner The TA1322FN is a wideband down-converter which can operate at input frequency ranging from 850 MHz to 2200 MHz. Intended primarily for use in satellite tuners, this IC includes an oscillator, a mixer, an IF amplifier and a PLL. The I2C bus data format is used as the data control format. The supply voltage of 5.0 V helps minimize the tuner’s power dissipation, while the compact 30-pin SSOP package allows the tuner to be kept small. Features · Supply voltage: 5.0 V (typ.) · Wide input frequency range · Low phase noise oscillator · Standard I2C bus format control · 4-MHz (X’tal) buffer output pin · Reference oscillator input change-over switch [X’tal or external input] · 33-V high-voltage tuning amplifier built-in · Built-in comparator (P4, P5, P7) · Bandswitch drive transistor (P0) [IBD = 40 mA (max)] · Selected IF output port · Frequency step: 62.5 kHz or 125 kHz (for 4-MHz X’tal) · 4-address setting via address selector · Power-on reset circuit · ×1/2 prescaler · Flat compact package: SSOP30-P-300-0.65 (0.65-mm pitch) Weight: 0.17 g (typ.) Power-On Reset Operation Conditions · Frequency step: 125 kHz · Charge pump output current: ±50 µA · Counter data: all [0] · Band driver: OFF · Tuning amplifier: OFF · IF output operation: pin 19 is ON Note 1: This device can easily be damaged by high voltages or electrical fields. For this reason, please handle it with care. 1 2002-02-12 TA1322FN VCC4 GND7 RF in2 RF in1 GND6 TEST XO SW GND5 VCC3 IF out2 GND4 IF out1 ADR set PO out SDA in/out Block Diagram 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 XO-SW Address IF-SW Band Driver 2 Programmable Counter Divider Phase Comparator VCC1 OSC-E OSC-B GND2 Vt-out NF 8 9 10 11 12 13 14 15 SCL in 7 P7 6 P5 5 P4 4 GND3 3 XO buff out 2 VCC2 1 GND1 Comparator X’tal 1/32 1/33 1/2 I C BUS Data Interface 2 2002-02-12 TA1322FN Pin Functions Pin No. Pin Name Function Interface 1 GND1 Ground pin for oscillator circuit block 2 VCC1 Power supply pin for local oscillator circuit block ¾ 2 4 3 Oscillator 3 Local oscillator circuit 4 GND1 5 GND2 ¾ Ground pin for oscillator circuit block VCC2 6 Vt Output 6 50 W Tuning voltage output pin with built-in tuning amplifier GND3 7 NF 7 VCC2 8 (4-MHz input) 8 5 kW Crystal oscillator input Reference Input 5 kW 1 kW VCC2 1 kW Can be switched between X’tal oscillator and external input using pin 24 (XO switch). GND3 9 VCC2 ¾ Power supply pin for PLL circuit block 10 Reference signal buffer output Buffer output pin for reference signal 5 kW 5 kW VCC2 10 GND3 11 GND3 Ground pin for PLL circuit block 3 ¾ 2002-02-12 TA1322FN Pin No. 12 13 Pin Name P4 P5 Function Interface CMOP Output can be controlled by setting the band switch data. 12, 13, 14 The circuit configuration is open collector output. Each pin has a built-in comparator. 14 P7 The status of the comparator can be checked READ mode. GND3 VCC2 SCL Input 2 Input pin for I C bus serial clock data 15 1 kW 100 W 15 GND3 VCC2 20 W 1 kW GND3 17 PO output Output can be controlled by setting band switch data. 12 kW VCC2 100 W 16 12 kW Input/Output 2 Input/output pin for I C bus serial clock data 70 kW SDA 16 DATA I/F 17 GND3 ADR Set 18 4 programmable address can be programmed. 100 W 100 W 1 kW 50 kW 18 The address for hardware bit setting can be selected by applying voltage to this pin. 150 kW VCC2 GND3 4 2002-02-12 TA1322FN Pin No. Pin Name Function Interface IF output pin. 19 IF Output 1 VCC3 Output can be controlled by setting the band switch data (P6). IF output impedance is 75 W each other. 21 IF Output 2 19, 21 When P6 data set 0, output pin is Pin 19 (IF output 1). When P6 data set 1, output pin is Pin 21 (IF output 2). GND4, 5 20 GND4 Ground pin for IF amplifier circuit block ¾ 22 VCC3 Power supply pin for IF amplifier circuit block ¾ 23 GND5 Ground pin for IF amplifier circuit block ¾ Determines reference signal input. XO Switch If connected to ground: X’tal oscillator. 24 1 kW 25 kW 24 25 kW VCC2 If open or connected to VCC2: external input GND3 TEST 25 100 kW 25 When test mode set, this pin can confirm X’tal divider signal and 1/2 counter signal. This pin can be used at open. 25 kW VCC2 GND3 GND6 27 RF Input1 ¾ Ground pin for mixer circuit block 27 RF signal input pin Input can be either balanced or unbalanced. 28 28 3 kW 26 3 kW RF Input2 GND7 29 GND7 Ground pin for mixer circuit block ¾ 30 VCC4 Power supply pin for mixer circuit block ¾ 5 2002-02-12 TA1322FN Absolute Maximum Ratings (Ta = 25°C) Parameter Pin No. Symbol Rating 2 VCC1 6 9 VCC2 6 22 VCC3 6 Supply voltage Unit V 30 VCC4 6 Tuning amplifier voltage 6 VBT 38 Power dissipation ¾ PD Operating temperature ¾ Topr -20 to 85 °C Storage temperature ¾ Tstg -55 to 150 °C V 1130 mW (Note 2) Note 2: 50 mm ´ 50 mm ´ 1.6 mm, 40% Cu board If Ta > 25°C, derate this value by 9.1 mW/°C. Recommended Operating Conditions Pin No. Symbol Min Typ. Max Unit 2 Local oscillator block VCC1 4.5 5.0 5.5 V 9 PLL block VCC2 4.5 5.0 5.5 V 22 IF amplifier block VCC3 4.5 5.0 5.5 V 30 Mixer block VCC4 4.5 5.0 5.5 V Electrical Characteristics DC Characteristics (unless otherwise specified, VCC1 = VCC2 = VCC3 = VCC4 = 5 V, Ta = 25°C) When power on, counter data = all [0], VBT = OFF, CP0 = 0, band = all [0], and IF output operate Pin 19. Parameter Symbol Test Circuit ICC1 Power supply current Total Test Condition Min Typ. Max ¾ 5.0 7.5 9.5 ¾ 21.5 26.5 32.0 ICC3 ¾ 19.5 24.0 29.0 ICC4 ¾ 10.0 12.5 15.5 ¾ 56.0 70.0 86.0 ICC2 ICC-total 1 ¾ 6 Unit mA mA 2002-02-12 TA1322FN Down-Converter Block AC Characteristics (unless otherwise specified, VCC1 = VCC2 = VCC3 = VCC4 = 5 V, Ta = 25°C) Symbol Test Circuit RF input frequency Mfin ¾ RF input level MPin IF output frequency Parameter IF output impedance (Note 3) Local oscillator frequency Min Typ. Max Unit ¾ 850 ¾ 2200 MHz ¾ ¾ ¾ ¾ -35 dBmW Afin ¾ ¾ 350 ¾ 550 MHz AZout ¾ ¾ 75 ¾ W LO ¾ 1300 ¾ 2700 MHz fRF = 898 MHz 27.5 30.5 33.5 fRF = 1598 MHz 27 31 34 fRF = 2198 MHz 24.5 29 32 fRF = 898 MHz ¾ 9 10.5 fRF = 1598 MHz ¾ 9 11.5 fRF = 2198 MHz ¾ 11 13 Conversion gain CG 3 (Note 3) Noise figure NF 4 (Note 3) IF output power level Apsat 3 (Note 3) 3rd inter modulation (IF output intercept point) IP3 5 (Note 3) Conversion gain shift CGs 3 (Note 3) Frequency shift (PLL OFF) DfB 3 Phase noise PN 3 (with 10-kHz offset) RF pin LORF 3 LO leak level IF pin LOIF 3 LO leak level IF switch isolation Test Condition (Note 4, Note 5) IFiso 3 Single-end ¾ fRF = 898 MHz 6 8 ¾ fRF = 1598 MHz 6 8 ¾ fRF = 2198 MHz 6 8 ¾ fd = 898 MHz, fud = 903 MHz 13 15 ¾ fd = 1598 MHz, fud = 1603 MHz 14 16 ¾ fd = 2198 MHz, fud = 2203 MHz 14 16 ¾ fRF = 898 MHz ¾ ¾ ±2 fRF = 1598 MHz ¾ ¾ ±2 fRF = 2198 MHz ¾ ¾ ±2 fosc = 1300 MHz ¾ ¾ ±5.5 fosc = 2000 MHz ¾ ¾ ±3.5 fosc = 2600 MHz ¾ ¾ ±3.5 fosc = 1300 MHz ¾ -74 -70 fosc = 2000 MHz ¾ -75 -71 fosc = 2600 MHz ¾ -74 -70 fosc = 1300 MHz ¾ -36 -33 fosc = 2000 MHz ¾ -31.5 -28 fosc = 2600 MHz ¾ -33 -30 fosc = 1300 MHz ¾ -21.5 -15.5 fosc = 2000 MHz ¾ -31 -25 fosc = 2600 MHz ¾ -36 -30.5 fRF = 898 MHz 30 36 ¾ fRF = 1598 MHz 30 36 ¾ fRF = 2198 MHz 30 36 ¾ dB dB dBmW dBmW dB MHz dBc/ Hz dBmW dBmW dB Note 3: IF output frequency = 402 MHz Note 4: IF output load = 75 W Note 5: IF output operate Pin 21 7 2002-02-12 TA1322FN PLL Block (unless otherwise specified, VCC1 = VCC2 = VCC3 = VCC4 = 5 V, Ta = 25°C) Parameter Symbol Test Circuit Tuning amplifier output voltage (close) Vt out 1 Tuning amplifier maximum current Ivt X’tal negative resistance Test Condition Min Typ. Max Unit VBT = 33 V, RL = 33 kW 0.3 ¾ 33 V 1 VBT = 33 V ¾ ¾ 3 mA XtR 1 XO-SW:GND (X’tal oscillator mode) 1 2.5 ¾ kW X’tal operating frequency OSCin 1 [NDK (AT-51), 4 MHz used] 3.2 ¾ 4.5 MHz X’tal external input level Xo extl 1 100 ¾ 1000 mVp-p X-ext 1 2 ¾ 6 MHz N ¾ 1024 ¾ 32767 Logic input low voltage VIL 1 -0.3 ¾ 1.5 Logic input high voltage VIH 1 3 ¾ Logic input current (low) I BsL 1 -20 ¾ 10 mA -10 ¾ 20 mA ¾ ¾ 0.4 V CP = [0] ±35 ±50 ±75 CP = [1] ±180 ±240 ±345 X’tal external input frequency Ratio setting range XO-SW: VCC2 or open 15-bit counter SDA and SCL pins SDA and SCL pins VCC2 + 0.3 V V Logic input current (high) I BsH 1 ACK output voltage VACK 1 Charge pump output current Ichg 1 Band driver drive current IBD 1 P0 ¾ ¾ 40 mA Band driver voltage drop VBDsat 1 P0: IBD = 40-mA drive ¾ 0.2 0.4 V Comparator pin input voltage VCMP 1 IP4, IP5, IP7 0 ¾ 6 V Comparator pin low voltage VLCMP 1 IP4, IP5, IP7 0 ¾ 1.5 V Comparator pin high voltage VHCMP 1 IP4, IP5, IP7 2.7 ¾ 6 V Output port flow current Output port saturation voltage Output port leakage current Output port maximum voltage ISINK = 3 mA mA IPin 2 P4, P5, P7 ¾ ¾ 7 mA Vpinsat 2 P4, P5, P7 (Ipin = 7 mA) ¾ 0.1 0.15 V Iplk 1 P4, P5, P7 (Vport = 6 V) ¾ ¾ 10 mA Vport 1 P4, P5, P7 ¾ ¾ 6 V 350 500 ¾ mVp-p 1-kW, 10-pF load Xo buffer output level Xo out 1 X’tal: NDK (AT-51), 4 MHz used. 4-MHz level monitored on oscilloscope using FET probe (1 MW, 1.9 pF). 8 2002-02-12 TA1322FN Bus Line Characteristics Parameter Symbol Test Circuit Test Condition Min Typ. Max Unit SCL clock frequency fSCL 0 ¾ 100 kHz Bus free time between a STOP and START conditions tBUF 4.7 ¾ ¾ ms tHD; STA 4 ¾ ¾ ms SCL clock low period tLOW 4.7 ¾ ¾ ms SCL clock high period tHIGH 4 ¾ ¾ ms 4.7 ¾ ¾ ms Hold time for repeated START condition ¾ Please refer to data timing chart. Set-up time for repeated START condition fSU; STA Data hold time tHD; DAT 0 ¾ ¾ ms Data set-up time tSU; DAT 250 ¾ ¾ ns Rise time for SDA and SCL signals tR ¾ ¾ 1000 ns Fall time for SDA and SCL signals tF ¾ ¾ 300 ns tsU; STO 4 ¾ ¾ ms Set-up time for STOP condition SDA tBUF tLOW tR tF tHD; STA SCL tHD; STA P tHD; DAT tHIGH S Figure 1 tSU; STO tSU; DAT tSU; STA Sr P 2 I C Bus Data Timing Chart (rising-edge timing) 9 2002-02-12 TA1322FN Test Conditions (1) Conversion gain RF input level = -40dBmW (2) Noise figure NF meter direct-reading value (DSB measurement) (3) IF output power level Measure maximum IF output level. (4) 3rd inter modulation · fd (fd input level = -40dBmW) · fud = fd + 5 MHz (fud input level = -40dBmW) Calculate IF output intercept point as follows: IP3 = S/(N - 1) + P [dBmW] S: suppression level N: 3 P: IF output level (5) Conversion gain shift Conversion gain shift is defined as change in conversion gain when supply voltage exceeds ranges VCC = 5 V to 4.5 V or VCC = 5 V to 5.5 V. (6) Frequency shift (PLL OFF) Frequency shift is defined as change in oscillator frequency when supply voltage exceeds ranges VCC1 = 5 V to 4.5 V or VCC1 = 5 V to 5.5 V. (7) Phase noise (offset = 10 kHz) Measure phase noise at 10-kHz offset. (8) RF pin local-leak level Measure worst-case local-leak level for RF pin (with IF output pin open). (9) IF pin local-leak level Measure worst-case local-leak level for IF pin (with RF input pins shorted using 50-W resistor, and not measure IF output pin open). (10) IF switch isolation RF input level = -40dBmW Measure selected IF output pin’s level, and not selected IF output pin’s level. Ifiso = |(selected IF output pin’s level ) - (not selected IF output pin’s level)| Not selected IF output pin shorts using 50 W resistor. 10 2002-02-12 TA1322FN PLL Block 2 --I C Bus Communications Control-The TA1322FN conforms to Standard Mode I2C bus format. I2C Bus Mode allows two-way bus communication using Write Mode (for receiving data) and Read Mode (for processing status data). Write Mode or Read Mode can be selected by setting the least significant bit (R/W bit) of the address byte. If the least significant address bit is set to 0, Write Mode is selected; if it is set to 1, Read Mode is selected. Address can be set using the hardware bits. 4 programmable address can be programmed. Using this setting, multiple frequency synthesizers can be used on the same I2C bus line. The address for the hardware bit setting can be selected by applying voltage to the address setting pin (ADR-pin 18). The address is selected according to the setting of these bits. During acknowledgment of receipt of a valid address byte, the serial data (SDA) line is Low. If Write Mode is currently selected, when the data byte is programmed, the serial data (SDA) line will be Low during the next acknowledgment. A) Write mode (setting command) When Write Mode is selected, byte 1 holds address data; byte 2 and byte 3 hold frequency data; byte 4 holds the divider ratio setting and function setting data; and byte 5 holds output port data. Data is latched and transferred at the end of byte 3, byte 4 and byte 5. Byte 2 and byte 3 are latched and transferred as a byte pair. Once a valid address has been received and acknowledged, the data type can be determined by reading the first bit of the next byte. That is, if the first bit is 0, the data is frequency data; if it is 1, the data is function-setting or band output data. Additional data can be input without the need to transmit the address data again until the I2C bus STOP condition is detected (e.g. a frequency sweep using additional frequency data is possible). If a data transmission is aborted, data programmed before the abort remains valid. [[BYTE 1]] The address data for byte 1 can be set using the hardware bit. The hardware bit can be set by applying a voltage to the address-setting pin (ADR: pin 18). [[BYTE 2, BYTE 3]] Byte 2, byte 3 control the 15-bit programmable counter ratio and are stored in the 15-bit shift register together with frequency setting counter data. The program frequency can be calculated using the following formula: fosc = 2 ´ fr ´ N fosc: Program frequency fr: Phase comparator reference frequency N: Counter total divider ratio fr is calculated from the crystal oscillator frequency and the reference frequency divider ratio set in byte 4 (the control byte). (fr = X’tal oscillator frequency/reference divider ratio) The reference frequency divider ratio can be set to 1/64 or 1/128. When a 4-MHz crystal oscillator is used, fr = 62.5 kHz or 31.25 kHz. The respective step frequencies are 125 kHz and 62.5 kHz. [[BYTE 4]] Byte 4 is a control byte used to set function. Bit 2 (CP) controls the output current of the charge-pump circuit. When bit 2 is set to [0], the output current is set to ±50 mA; when set to [1], ±240 mA. Bit 3 (T1) is used to set the test mode. When bit 3 is set to [0], normal mode; when set to [1], test mode. Bit 4 (T0) is used to set the charge pump. When bit 4 is set to [0], charge pump is ON (normal used); When set to [1], charge pump is OFF. Bit 5 (TS2) and bit 6 (TS1) used to set the test mode. They are used to set the charge pump test, phase comparator reference signal output, and 1/2 counter divider ratios. Bit 7 (TS0) is used to set the X’tal reference frequency divider ratio. When bit 7 is set to [0], 1/128 (frequency step is 62.5 kHz); when set to [1], 1/64 (frequency step is 125 kHz). Bit 8 (OS) is used to set the charge pump drive amplifier output setting. When bit 8 is set to [0], 11 2002-02-12 TA1322FN the output is ON (normal mode); when set to [1], the output is OFF. [[BYTE 5]] Byte 5 can be used to set control the output port. Bit 1 (P7), bit 3 (P5) and bit 4 (P4) are used to control output port P7, P5 and P4. Bit 2 (P6) is used to control change IF output port. When bit 2 is set to [0], IF output 1 (pin 19) is ON; when set to [1], IF output 1 (pin 21) is ON. Bit 8 (P0) is used to control band output port (P0). When bit 8 is set to [0], P0 is OFF; when set to [1], P0 is ON. (P0) output port can be driven at less than 40 mA. B) READ mode (status request) When READ mode is set, power-on reset operation status, phase comparator lock detector output status, comparator input voltage status are output to the master device. Bit 1 (POR) indicates the power-on reset operation status. When the power supply of VCC2 stops, bit is set to [1]. The condition for reset to [0], voltage supplied to VCC2 is 3 V or higher, transmission is requested in READ mode, and the status is output. (when VCC2 is turned on, bit 1 is also set to [1].) Bit 2 (FL) indicates the phase comparator lock status. When locked, [1] is output; when unlocked, [0] is output. Bit 3 (IP7), bit 4 (IP5) and bit 5 (IP4) indicate the input comparator status. High level status is output [1], low level status is output is [0]. When voltage applied from 0 V to 1.5 V, output is [0]. When from 2.7 V to 6 V, output is [1]. Data Format A) Write mode MSB LSB 1 Address Byte 1 1 0 0 0 MA1 MA0 R/W = 0 ACK 2 Divider Byte 1 0 N14 N13 N12 N11 N10 N9 N8 ACK 3 Divider Byte 2 N7 N6 N5 N4 N3 N2 N1 N0 ACK (L) 1 CP T1 T0 TS2 TS1 TS0 OS ACK (L) P7 P6 P5 P4 ´ ´ ´ P0 ACK (L) 4 Control Byte 5 Band SW Byte ´: Don’t care ACK: Acknowledged (L): Latch and transfer timing B) Read mode MSB 1 Address Byte 2 Status Byte LSB 1 1 0 0 0 MA1 MA0 R/W = 1 ACK POR FL IP7 IP5 IP4 1 1 1 ¾ ACK: Acknowledged 12 2002-02-12 TA1322FN Data Specifications · MA1 and MA0: programmable hardware address bits MA1 MA0 Voltage Applied to Address Pin 0 0 0 to 0.1VCC2 0 1 OPEN or 0 to VCC2 1 0 0.4VCC2 to 0.6VCC2 1 1 0.9VCC2 to VCC2 · N14-N0: programmable counter data · CP: charge pump output current setting [0]: ±50 mA (typ.) [1]: ±240 mA (typ.) · T1: test mode setting [0]: normal mode [1]: test mode · T0: charge pump setting [0]: charge pump is ON (normal mode) [1]: charge pump is OFF · · TS0: X’tal reference frequency divider ratio select bits. TS0 Divider ratio Step frequency fr 0 1/128 62.5 kHz 31.25 kHz 1 1/64 125 kHz 62.5 kHz T1, TS2, TS1, TS0: test mode Characteristics T1 TS2 TS1 TS0 Divider ratio Notes Normal operation 0 ´ ´ 0 1/128 ¾ Normal operation 0 ´ ´ 1 1/64 ¾ Sink 1 1 0 0 1/128 ¾ Source 1 1 0 1 1/64 ¾ Output port OFF 1 1 1 0 1/128 Phase comparator test 1 1 1 1/64 Charge pump P7, P5, P4 OFF SDA: Comparative signal input 1 SCL: Reference signal input 1 0 0 0 1/128 1 0 0 1 1/64 1 0 1 0 1/128 1 0 1 1 1/64 Output to pin 25 (TEST) X’tal divider counter output Output to pin 25 (TEST) 1/2 counter divider output ´: DON’T CARE Note 5: When test mode, OS = 0 (tuning ON) is necessary. When testing the counter divider output, programmable counter data input is necessary. 13 2002-02-12 TA1322FN · OS: tuning amplifier control setting [0]: Tuning amplifier ON (normal operation) [1]: Tuning amplifier OFF · P4, P5, P7: output port [0]: OFF [1]: ON · · P6: IF output port switchover P6 Output Port 0 IF output 1 (pin 19) is ON 1 IF output 2 (pin 21) is ON P0: band output [0]: OFF [1]: ON This can be driven at less than 40 mA. · POR: power-on reset flag [0]: normal operation [1]: reset operation · FL: lock detect flag [0]: Unlocked [1]: Locked · IP4, IP5, IP7: comparator output [0]: supply voltage is from 0 V to 1.5 V [1]: supply voltage is from 2.7 V to 6 V · XO-SW: reference signal input changeover Pin 24 Input Method GND X’tal VCC2 or open External input 14 2002-02-12 TA1322FN Test Circuit 1 DC Characteristics VCC2/Open: Extenal input GND: X’tal SDA IBD VCC2/Open XO-SW ADR set 28 1 nF 1 nF 29 0.01 mF A ICC3 0.01 mF A ICC4 30 VBDsat VCC3 (5 V) TEST V 390 W VCC4 (5 V) A 27 26 25 24 23 22 NC 21 20 NC 19 XO-SW 18 17 16 Address IF-SW Band Driver 2 Programmable Counter 3 4 NC NC 5 6 7 8 9 NC NF 1 nF VCC1 (5 V) 11 12 13 14 15 P4 P5 P7 SCL 1 kW A ICC2 *X’tal 22 pF A ICC1 10 390 W 2 0.01 mF Comparator 1 nF 1 Divider Phase Comparator 0.01 mF 1/32 1/33 1/2 I C BUS Data Interface 10 pF 4 MHz out EXT.in VCC2 (5 V) X’tal: NDK (AT-51), 4 MHz 15 2002-02-12 TA1322FN Test Circuit 2 DC Characteristics Measurement for “Output port flow current” and “Output port saturation voltage”. 12, 13, 14 IPin A V VPinsat Test Circuit 3 AC Characteristics 5V VCC2/Open: Extenal input GND: X’tal VCC2/Open RF in IF out 1 IF out 2 ADR set PO out SDA 18 17 16 30 29 28 27 TEST 25 26 24 23 22 21 390 W 1 nF 1 nF 0.1 mF 1 nF 1 nF 0.1 mF 1 nF XO-SW 20 19 XO-SW Address IF-SW Band Driver 2 Programmable Counter 10 kW 10 11 12 13 14 15 P4 P5 P7 SCL 390 W 9 1 nF 8 X’tal 22 pF 7 0.1 mF 6 4.7 nF L 5 10 kW Comparator 4 MHz out 1 nF 47 kW 33 V 1T379 0.1 mF 4 5 pF 3 47 pF 2 0.1 mF 4.7 kW 1T379 4.7 nF 1 Divider Phase Comparator 13 kW 1/32 1/33 1/2 I C BUS Data Interface 16 2002-02-12 TA1322FN Test Circuit 4 Measuring Noise Figure Noise Figure Meter out in IF output pin DUT 28 Noise source 75 W-50 W impedance transformer Test Circuit 5 Measuring 3rd Inter Modulation fd Signal Generator 1 IF output pin 28 DUT in Spectrum Analyzer 75 W-50 W impedance transformer Signal Generator 2 fud 17 2002-02-12 TA1322FN 2 I C-Bus Control Summary The bus control format of TA1322FN conforms to the Philips I2C-bus control format. Data Transmission Format S Slave address 0 A SUB address 7 bits A Data 8 bits MSB MSB A P 8 bits MSB S: Start condition P: Stop condition A: Acknowledge (1) Start/stop condition Serial Data Serial Clock (2) S P Start condition Stop condition Bit transfer Serial Data Serial Clock Serial data unchanged. (3) Serial data can be changed. Acknowledge Serial Data From Master Device High-Impedance Serial Clock From Slave High-Impedance Serial Clock From Master Device 1 8 9 S 18 2002-02-12 TA1322FN (4) Slave address A6 A5 A4 A3 A2 A1 A0 R/W 1 1 0 0 0 * * 0 Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Tights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Handling Precautions 1. The device should not be inserted into or removed from the test jig while a voltage is being applied to it: otherwise the device may be degraded or break down. Also, do not abruptly increase or decrease the power supply to the device (see figure 1). Overshoot or chattering in the power supply may cause the IC to be degraded. To avoid this, filters should be placed on the power supply line. Supply voltage 6 V (VCC1, VCC2, VCC3, VCC4) 38 V (VBT) 90% 10% 1 ms Time Figure 1 2. The peripheral circuits described in this datasheet are given only as system examples for evaluating the device’s performance. TOSHIBA intend neither to recommend the configuration or related values of the peripheral circuits nor to manufacture such application systems in large quantities. Please note that the high-frequency characteristics of the device may vary depending on the external components, the mounting method and other factors relating to the application design. Therefore, the evaluation of the characteristics of application circuits is the responsibility of the designer. TOSHIBA only guarantee the quality and characteristics of the device as described in this datasheet and do not assume any responsibility for the customer’s application design. 3. In order to better understand the quality and reliability of TOSHIBA semiconductor products and to incorporate them into designs in an appropriate manner, please refer to the latest Semiconductor Reliability Handbook (integrated circuits) published by TOSHIBA Semiconductor Company. This handbook can also be viewed on-line at the following URL: <http://www.semicon.toshiba.co.jp/noseek/us/sinrai/sinraifm.htm>. 19 2002-02-12 TA1322FN Package Dimensions Weight: 0.17 g (typ.) 20 2002-02-12 TA1322FN RESTRICTIONS ON PRODUCT USE 000707EBA · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 21 2002-02-12