INTEGRATED CIRCUITS DATA SHEET SAA4979H Sample rate converter with embedded high quality dynamic noise reduction and expansion port Product specification 2002 May 28 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979H CONTENTS 8 CONTROL REGISTER DESCRIPTION 1 FEATURES 8.1 8.2 Host interface detail Special Function Registers (SFRs) 2 GENERAL DESCRIPTION 9 LIMITING VALUES 3 QUICK REFERENCE DATA 10 THERMAL CHARACTERISTICS 4 ORDERING INFORMATION 11 CHARACTERISTICS 5 BLOCK DIAGRAM 12 TRANSFER FUNCTIONS 6 PINNING 13 APPLICATION INFORMATION 7 FUNCTIONAL DESCRIPTION 14 PACKAGE OUTLINE 7.1 7.1.1 7.1.2 Digital processing at 1fH level ITU 656 decoder Double window and picture-in-picture processing Black bar detector Dynamic noise reduction Noise estimator Embedded DRAM 3.5-Mbit field memory Digital processing at 2fH level Sample rate conversion Expansion port Panoramic zoom Digital colour transient improvement Y horizontal smart peaking Non-linear phase filter Post processing Triple 10-bit digital-to-analog conversion Microcontroller Host interface I2C-bus interface SNERT-bus I/O ports Watchdog timer Reset System controller Read enable output Read enable input Input enable Horizontal deflection Vertical deflection Auxiliary display signal Read enable 2 Output input enable 2 Reset read 2 Reset write 2 Line-locked clock generation Boundary scan test 15 SOLDERING 15.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 7.1.3 7.1.4 7.1.5 7.2 7.2.1 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.4 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.6.7 7.6.8 7.6.9 7.6.10 7.7 7.8 2002 May 28 15.2 15.3 15.4 15.5 2 16 DATA SHEET STATUS 17 DEFINITIONS 18 DISCLAIMERS 19 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port 1 SAA4979H FEATURES • Digital YUV input according to ITU 656 standard • 4 : 2 : 2 field rate upconversion (50 to 100 Hz or 60 to 120 Hz) • 3.5-Mbit embedded DRAM • I2C-bus controlled • Sample rate conversion for linear zoom and compression • Synchronous No parity Eight bit Reception and Transmission (SNERT) interface • Panorama mode • Boundary Scan Test (BST). • Dynamic noise reduction • Noise estimator • Black bar detection 2 • Luminance horizontal smart peaking The SAA4979H provides an economic stand-alone solution for 4 : 2 : 2 field rate upconversion (50 to 100 Hz or 60 to 120 Hz) including the required field memory combined with picture improvement features and dynamic field based noise reduction. The IC contains two digital input channels to allow field or frame based picture-in-picture processing. It also offers a feature expansion port for vector based motion estimation and compensation ICs such as SAA4991WP or SAA4992H. • Digital Colour Transient Improvement (DCTI) • Triple 10-bit Digital-to-Analog Converter (DAC) • Line-locked PLL • Expansion port for SAA4992H and SAA4991WP • Double window and Picture-In-Picture (PIP) processing • Embedded 80C51 microcontroller GENERAL DESCRIPTION • 32-Kbyte internal ROM (mask programmable) • 512-byte internal RAM 3 QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDDD digital supply voltage 3.0 3.3 3.6 V VDDA analog supply voltage 3.15 3.30 3.45 V VDDO; VDDI I/O supply voltage 3.0 3.3 3.6 V VDDP protection supply voltage 3.0 5.0 5.5 V IDDD digital supply current − 120 160 mA IDDA analog supply current − 40 50 mA Ptot total power dissipation − − 0.9 W Tamb ambient temperature −20 − +70 °C 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA4979H QFP128 2002 May 28 DESCRIPTION plastic quad flat package; 128 leads (lead length 1.6 mm); body 28 × 28 × 3.4 mm; high stand-off height 3 VERSION SOT320-2 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port 5 SAA4979H BLOCK DIAGRAM handbook, full pagewidth NOISE ESTIMATOR LLC1 CLK27 BLACK BAR DETECTOR SAA4979H LLC2 SOURCE SELECT DI17 to DI10 DI27 to DI20 8 2 H, V ITU 656 DECODER 1 16 8 16 Y [7:0] MAIN CHANNEL 8 DYNAMIC NOISE REDUCTION 16 SUB CHANNEL FAST SWITCH 16 ITU 656 DECODER 2 FIELD MEMORY 3.5 MBIT H HREF EXT_CLK OSCI 16 SAMPLE RATE CONVERSION 27 to 32 MHz PLL CLK32 OSCO CLK32 BYPASS YO7 to YO0 UVO7 to UVO0 HD, VD, ADS REO, IE, OIE2 SYSTEM CONTROLLER 2 DOWNSAMPLING H, V RE2, RSTR2 REI, RSTW2 BYPASS ROM RST P1.2 to P1.5 SNRST SNDA,SNCL SDA, SCL RAM SOURCE SELECT MICROCONTROLLER I/O PORT SNERTBUS YI7 to YI0 UVI7 to UVI0 UPSAMPLING I2C-BUS PANORAMIC ZOOM LUMINANCE CIRCUIT 10 YOUT TRIPLE 10-BIT DAC UOUT VOUT POST PROCESSING NON-LINEAR PHASE FILTER HORIZONTAL SMART Y PEAKING Y BCE TDI BLANKING FRAMING SIDE PANEL CHROMINANCE CIRCUIT 10 10 UPSAMPLING 4: 2: 2 to 4: 4: 4 DCTI UV BOUNDARY SCAN TEST TCK TMS TRST TDO MHC186 Fig.1 Block diagram. 2002 May 28 4 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port 6 SAA4979H PINNING SYMBOL PIN TYPE DESCRIPTION VDDO1 1 supply I/O supply voltage 1 (3.3 V) RSTR2 2 digital output (test input) reset read, source 2 RE2 3 digital output (test input) read enable, source 2 OIE2 4 digital output (test input) output/input enable, source 2 VSSO1 5 ground I/O ground 1 RSTW2 6 digital input reset write, source 2 DI10 7 digital input ITU 656 input bit 0 (LSB), source 1 DI11 8 digital input ITU 656 input bit 1, source 1 DI12 9 digital input ITU 656 input bit 2, source 1 DI13 10 digital input ITU 656 input bit 3, source 1 DI14 11 digital input ITU 656 input bit 4, source 1 DI15 12 digital input ITU 656 input bit 5, source 1 DI16 13 digital input ITU 656 input bit 6, source 1 DI17 14 digital input ITU 656 input bit 7 (MSB), source 1 VSSD1 15 ground digital ground 1 LLC1 16 digital input 27 MHz clock signal, source 1 VDDD1 17 supply digital supply voltage 1 (3.3 V) VDDP 18 supply protection supply voltage (5 V) DI20 19 digital input ITU 656 input bit 0 (LSB), source 2 DI21 20 digital input ITU 656 input bit 1, source 2 DI22 21 digital input ITU 656 input bit 2, source 2 DI23 22 digital input ITU 656 input bit 3, source 2 DI24 23 digital input ITU 656 input bit 4, source 2 DI25 24 digital input ITU 656 input bit 5, source 2 DI26 25 digital input ITU 656 input bit 6, source 2 DI27 26 digital input ITU 656 input bit 7 (MSB), source 2 VSSD2 27 ground digital ground 2 LLC2 28 digital input 27 MHz clock signal, source 2 VDDD2 29 supply digital supply voltage 2 (3.3 V) TCK 30 digital input test clock TDI 31 digital input test data input TMS 32 digital input test mode select 33 digital input test reset (active LOW) − not connected TRST n.c. 34 to 41 TDO 42 digital output test data output VDDA1 43 supply analog supply voltage 1 (3.3 V) YOUT 44 analog output Y analog output VSSA1 45 ground analog ground 1 UOUT 46 analog output −(B − Y) analog output VDDA2 47 supply analog supply voltage 2 (3.3 V) 2002 May 28 5 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SYMBOL PIN TYPE SAA4979H DESCRIPTION VOUT 48 analog output −(R − Y) analog output VSSA2 49 ground analog ground 2 AGND 50 ground analog ground (without substrate contacts) BGEXT 51 analog I/O band gap external I/O VDDA3 52 supply analog supply voltage 3 (3.3 V) VSSO2 53 ground I/O ground 2 HD 54 digital output horizontal synchronisation output, display part VD 55 digital output vertical synchronisation output, display part VSSA3 56 ground analog ground 3 VDDI 57 supply I/O internal supply voltage (3.3 V) OSCI 58 analog input oscillator input OSCO 59 analog output oscillator output CLKEXT 60 digital input external clock input VDDD3 61 supply digital supply voltage 3 (3.3 V) CLK32 62 digital output 32 MHz clock output VSSD3 63 ground digital ground 3 VDDO2 64 supply I/O supply voltage 2 (3.3 V) UVI0 65 digital input UV digital input bit 0 (LSB) UVI1 66 digital input UV digital input bit 1 UVI2 67 digital input UV digital input bit 2 UVI3 68 digital input UV digital input bit 3 UVI4 69 digital input UV digital input bit 4 UVI5 70 digital input UV digital input bit 5 UVI6 71 digital input UV digital input bit 6 UVI7 72 digital input UV digital input bit 7 (MSB) YI0 73 digital input Y digital input bit 0 (LSB) YI1 74 digital input Y digital input bit 1 YI2 75 digital input Y digital input bit 2 YI3 76 digital input Y digital input bit 3 YI4 77 digital input Y digital input bit 4 YI5 78 digital input Y digital input bit 5 YI6 79 digital input Y digital input bit 6 YI7 80 digital input Y digital input bit 7 (MSB) REI 81 digital input read enable input VSSO3 82 ground I/O ground 3 IE 83 digital output input enable REO 84 digital output read enable output YO7 85 digital output Y digital output bit 7 (MSB) YO6 86 digital output Y digital output bit 6 YO5 87 digital output Y digital output bit 5 YO4 88 digital output Y digital output bit 4 2002 May 28 6 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SYMBOL PIN TYPE SAA4979H DESCRIPTION VDDO3 89 supply I/O supply voltage 3 (3.3 V) YO3 90 digital output Y digital output bit 3 YO2 91 digital output Y digital output bit 2 YO1 92 digital output Y digital output bit 1 YO0 93 digital output Y digital output bit 0 (LSB) VSSO4 94 ground I/O ground 4 UVO7 95 digital output UV digital output bit 7 (MSB) UVO6 96 digital output UV digital output bit 6 UVO5 97 digital output UV digital output bit 5 UVO4 98 digital output UV digital output bit 4 VDDO4 99 supply I/O supply voltage 4 (3.3 V) UVO3 100 digital output UV digital output bit 3 UVO2 101 digital output UV digital output bit 2 UVO1 102 digital output UV digital output bit 1 UVO0 103 digital output UV digital output bit 0 (LSB) VSSD4 104 ground digital ground 4 VDDD4 105 supply digital supply voltage 4 (3.3 V) ADS 106 digital output auxiliary display signal SNCL 107 digital output SNERT clock SNDA 108 digital I/O SNERT serial data VSSO5 109 ground microcontroller I/O ground SNRST 110 digital I/O SNERT restart (port 1.0) SDA 111 digital I/O I2C-bus serial data (port 1.7) SCL 112 digital I/O I2C-bus clock (port 1.6) P1.5 113 digital I/O port 1 data input/output signal 5 P1.4 114 digital I/O port 1 data input/output signal 4 P1.3 115 digital I/O port 1 data input/output signal 3 P1.2 116 digital I/O port 1 data input/output signal 2 VDDO5 117 supply microcontroller I/O supply voltage (3.3 V) RST 118 digital input microcontroller reset input n.c. 119 to 127 BCE 128 2002 May 28 − not connected digital input boundary scan compliant enable 7 Philips Semiconductors Product specification UVO4 UVO5 98 97 100 UVO3 99 VDDO4 101 UVO2 102 UVO1 SAA4979H 104 VSSD4 103 UVO0 106 ADS 105 VDDD4 107 SNCL 110 SNRST 109 VSSO5 108 SNDA 111 SDA 112 SCL 113 P1.5 114 P1.4 115 P1.3 116 P1.2 119 n.c. 120 n.c. 121 n.c. 122 n.c. 123 n.c. 124 n.c. 125 n.c. 126 n.c. 127 n.c. 128 BCE handbook, full pagewidth 118 RST 117 VDDO5 Sample rate converter with embedded high quality dynamic noise reduction and expansion port VDDO1 1 96 UVO6 RSTR2 2 95 RE2 3 94 UVO7 VSSO4 OIE2 VSSO1 4 93 YO0 5 92 YO1 RSTW2 6 91 YO2 DI10 7 90 DI11 8 89 YO3 VDDO3 DI12 9 88 YO4 DI13 10 87 YO5 DI14 11 86 YO6 DI15 12 85 YO7 DI16 13 84 REO DI17 14 83 VSSD1 LLC1 VDDD1 15 82 IE VSSO3 VDDP DI20 81 REI 80 YI7 18 79 YI6 19 78 YI5 DI21 20 77 YI4 DI22 21 76 YI3 DI23 22 75 YI2 DI24 23 74 YI1 DI25 24 73 YI0 DI26 25 72 UVI7 DI27 26 71 UVI6 VSSD2 LLC2 VDDD2 27 70 UVI5 28 69 UVI4 29 68 UVI3 TCK 30 67 UVI2 TDI 31 66 UVI1 TMS 32 65 UVI0 16 2002 May 28 8 60 64 59 OSCO CLKEXT VDDD3 63 58 VDDO2 57 OSCI 62 56 VSSA3 VDDI CLK32 VSSD3 55 Fig.2 Pin configuration. 61 54 VD 53 VSSO2 HD 44 YOUT VSSA1 52 43 VDDA1 51 42 TDO BGEXT VDDA3 41 n.c. 50 40 n.c. AGND 39 n.c. 49 38 n.c. 48 37 n.c. VOUT VSSA2 36 n.c. 47 35 n.c. 45 34 n.c. UOUT VDDA2 33 TRST 46 SAA4979H 17 MHC200 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port 7 FUNCTIONAL DESCRIPTION The incoming active video data must be limited to 1 to 254, since the data words 00H and FFH are used for identification of the timing reference headers. Digital processing at 1fH level 7.1 7.1.1 SAA4979H ITU 656 DECODER The digital signal input levels should comply to the CCIR-601 standard (see Fig.3). The data stream is decoded into the internal 4 : 2 : 2 YUV format at a 13.5 MHz clock rate. If required the sign of the UV signals can be inverted for both channels (control inputs: uv_sign1 and uv_sign2). The SAA4979H provides 2 digital video input channels, which comply to the ITU 656 standard. 720 active video pixels per line are processed at a line-locked clock of 27 MHz, which has to be provided by the signal source. Luminance and chrominance information have to be multiplexed in the following order: CB1, Y1, CR1, Y2, ... Timing reference codes must be inserted at the beginning and end of each video line (see Table 1): The signal source of the main channel can be selected from both inputs by the internal microcontroller (control input: Select_data_input1). • A ‘Start of Active Video’ (SAV) code before the first active video sample (see Table 2) • A ‘End of Active Video’ (EAV) code after the last active video sample (see Table 2). Table 1 ITU data format BLANKING PERIOD ... 80 Table 2 10 720 PIXELS YUV 4 : 2 : 2 DATA TIMING REFERENCE CODE (HEX) BLANKING PERIOD FF 00 00 SAV CB0 Y0 CR0 Y1 CB2 Y2 ... CR718 Y719 FF 00 00 EAV 80 10 ... SAV/EAV format BIT 6 (F) BIT 7 1 TIMING REFERENCE CODE (HEX) field bit 1st field: F = 0; 2nd field: F = 1 2002 May 28 BIT 5 (V) BIT 4 (H) vertical blanking bit VBI: V = 1; active video: V = 0 H = 0 in SAV format; H = 1 in EAV format 9 BIT 3 (P3) BIT 2 (P2) BIT 1 (P1) BIT 0 (P0) reserved; evaluation not recommended (protection bits according to ITU 656) Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port + 255 handbook, full pagewidth + 235 + 128 white LUMINANCE 100% SAA4979H + 255 + 240 blue 100% + 255 + 240 red 100% + 212 blue 75% + 212 red 75% + 128 colourless + 128 colourless U-COMPONENT + 16 black 0 V-COMPONENT + 44 yellow 75% + 44 cyan 75% + 16 yellow 100% + 16 cyan 100% 0 0 MHC201 a. Y output range. b. U output range (CB). c. V output range (CR). It should be noted that the input levels are limited to 1 to 254 in accordance with ITU 601/656 standard. Fig.3 Digital video input levels. 7.1.2 DOUBLE WINDOW AND PICTURE-IN-PICTURE 7.1.3 PROCESSING Black bar detection searches for the last black line in the upper part of the screen and for the first black line in the lower part of the screen. The detection is done within a programmable window (control inputs: bbd_hstart, bbd_hstop, bbd_vstart and bbd_vstop). To avoid disturbances of LOGOs in the video, the window can be shifted to the horizontal centre of the lines. A video line is considered to be black if the luminance values of that line within the detection window are not greater than a certain slice level (control input: bbd_slice_level) for more than a specific number of pixels (control input: bbd_event_value). Data from the sub channel can be inserted into the data stream of the main channel by means of a fast switch. The two channels can be used together with one or two external field memories to implement, for example, double window or PIP processing. Both field based and frame based PIP processing is supported. The synchronization of the sub channel to the main channel is achieved by providing synchronized read signals (RE2 and RSTR2) for the external field memories, whereas the write signals need to be provided together with the incoming data by the external signal source. The numbers of the first and the last active video line can be read out by the microcontroller (control outputs: bbd_1st_videoline and bbd_last_videoline). A multi-PIP mode is also supported by freezing the data in the internal field memory within certain areas via the programmable internal control signal IEint. 2002 May 28 BLACK BAR DETECTOR 10 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port 7.1.4 It should be noted that recursion is done over fields, and that pixel positions between the new and old fields always have a vertical offset of one line. So averaging is not only done in the dimension of time but also in the vertical direction. Therefore averaging vertically on, for example, a vertical black to white edge would produce a grey result. DYNAMIC NOISE REDUCTION The main function of the noise reduction is shown in Fig.4. It is divided into two signal paths for chrominance and luminance. In principal two operating modes can be used, the fixed and the adaptive mode. In both modes the applied frequency range, in which the noise reduction takes place, can be reduced or not reduced (control input: unfiltered). The averaging in chrominance can optionally be slaved to the luminance averaging (control input: Klumatochroma), in that case chrominance differences are not taken into account for the K factor setting of the chrominance signal path. The noise reduction operates field recursive with an averaging ratio (K factor) between fresh (new) and over previous fields averaged (old) luminance and chrominance values. Noise reduction can be activated by forcing the NREN control bit to HIGH. If NREN is LOW the noise reduction block is bridged via a data multiplexer. The noise reduction scheme also decreases the cross-colour patterns effectively if the adaptive noise reduction for the averaging in chrominance is slaved to the luminance averaging (control input: Klumatochroma). The cross-colour pattern does not produce an increase of the measured luminance difference, therefore this pattern will be averaged over many fields. In the fixed mode, the noise reduction produces a constant weighted input averaging. Because of smearing effects this mode should not be used for normal operation except for K = 1. The fixed mode can be activated separately for chrominance (control input: chromafix) and luminance (control input: lumafix). In the adaptive mode, the averaging ratio is based on the absolute differences of the inputs of luminance and chrominance respectively. If the absolute difference is low, only a small part of the fresh data will be added. In cases of high difference, much of the fresh data will be taken. This occurs either in situations of movement or where a significant vertical contrast is seen. The relationship between the amount of movement and the K factor values is defined in a look-up table where the steps can be programmed (control input: Kstep). 2002 May 28 SAA4979H 11 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port data input UV7 to UV0 Dfielddelay UV7 to UV0 data input Y7 to Y0 8 8 8 8 new U/V old U/V new Y old Y delta U/V delta Y LOW-PASS FILTER 1 LOW-PASS FILTER 1 control input: unfiltered control input: unfiltered LF delta Y HF delta U/V LF delta U/V ABS/LIMITER UV AVERAGE ABS/LIMITER LOW-PASS FILTER 2 LOW-PASS FILTER 2 control input: chromafix and Klumatochroma control input: Cadapt_gain LUT Dfielddelay Y7 to Y0 HF delta Y handbook, full pagewidth SAA4979H control input: Yadapt_gain control input: lumafix Klumafix Kchroma Kchromafix Kluma Kluma LUT processed UV control input: noiseshape processed Y control input: noiseshape NOISE SHAPE 8 8 Dtomemory UV7 to UV0 MHC202 Fig.4 Schematic diagram of noise reduction. 2002 May 28 NOISE SHAPE 12 Dtomemory Y7 to Y0 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port 7.1.4.1 Band-splitting 7.1.4.4 The frequencies of the difference signals of luminance (delta Y) and chrominance (delta U/V) can be split optionally into an upper band (HF) and a lower band (LF) with a low-pass filter in both signal paths. The lower frequency band signals (LF delta Y and LF delta U/V) are used as input for the noise reduction function. 7.1.5 Motion detection The same signals (the noise reduction is applied to) are also used to detect the amount of motion in the difference signals. Therefore, the absolute values of the difference signals are generated and limited to a maximum value. The absolute values of the difference signal of U and V are then averaged. The signals are low-pass filtered for smoothing these signals. The filtered signals are amplified, depending on the setting of the control inputs: Yadapt_gain and Cadapt_gain respectively. The lower boundary is increased or decreased by 1 in each field until an interval is found which contains at least a predefined number of estimates, and is at the same time lowest in the range. The value of the lower boundary of this interval determines the current noise figure output. The predefined number of estimates can be set via the microcontroller (control input: wanted_value), and good results were obtained with a value which is approximately 0.27% of the total number of blocks. The amplified signals, which correlate to the amount of movement in the chrominance or luminance signal path, are transferred into 1 out of 9 possible K factor values via look-up tables. The look-up tables consist of 9 intervals, each related to one K factor. The boundaries between the 9 intervals are defined by 8 programmable steps (control inputs: Kstep0 to Kstep7). The step values are valid for the look-up tables for both the chrominance and the luminance path. For example, signal values between Kstep2 and Kstep3 result in a K factor of K = 3/8. For video fields with a lot of noise the number of small differences is very low, that means the number of noise estimates in the lower intervals is close to 0. Contrary to this, for clean sequences this number is very high. This means that for clean sequences the noise estimate figure will be close to 0, and for sequences with a lot of noise the noise estimate figure (control output: nest) will reach 15. K factor The amount of noise reduction (field averaging) is described my means of the K factor. When K = 1 no averaging is applied and the new field information is used. When K = 0 no averaging is applied and thus only the old field information is used like in a still picture mode. All values inbetween mean that a weighted averaging is applied. It is possible to use fixed K factor values if the control inputs lumafix or chromafix are set to logic 1. The possible fixed K factor values of the control inputs Klumafix and Kchromafix are given in Table 6. 2002 May 28 NOISE ESTIMATOR The noise level of the luminance signal can be measured within a programmable window (control inputs: ne_hstart, ne_hstop, ne_vstart and ne_vstop). The correlation in flat areas is used to estimate the noise in the video signal. A large number of estimates of the noise is calculated for every video field. Such an estimate is obtained by summing absolute differences between current pixel values and delayed pixel values within blocks of 4 pixels. Within the lower part of the total range of possible estimates 15 intervals are defined. Each interval is defined by a lower boundary and an upper boundary. The lower boundary is equal to the number of the interval, whereas the upper boundary has a fixed relationship to the lower boundary (control input: gain_upbnd). Optionally it is possible to bridge the band-splitting (control input: unfiltered = 1). 7.1.4.3 Noise shape Possible shadow picture information in the chrominance and luminance path, resulting from a low K factor value, will be eliminated if the noise shaping is activated. The noise shaping function can be switched off via the microcontroller (control input: noiseshape). The lower frequency band of the difference signals can also be used for the motion detection. If, for example, only the lower frequency band contains information, the specific picture content does not move or is moving slowly. 7.1.4.2 SAA4979H To improve the performance of the noise estimator, several functions are implemented which can be controlled by the microcontroller. To increase the sensitivity of the noise measurement a prefilter with different gain settings is available (control input: Ypscale). Since the video content, e.g. sequences with a lot of high frequencies, can influence the noise estimate figure, a detail-counter is built-in. 13 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979H The detail-counter calculates the number of absolute differences between current and previous pixels within a programmable interval defined by the control inputs lb_detail and upb_detail. The result of the 16-bit detail-counter (control outputs: detail_cnt_h and detail_cnt_l) can be used to increase or decrease the result of the noise estimation figure (control input: compensate). In addition, the internal write address pointer is incremented if WEint is HIGH at the positive transition of the SWCKint write clock. The data is latched if WEint was HIGH at the previous positive transition of SWCKint. Input enable (IEint) LOW can also suppress the storage of the data into the memory array but does not influence the write pointer increment. It is used to freeze parts of the field data e.g for PIP processing. In order to reduce the effect of clipping, only the blocks where the sum of the luminance value is within a predefined range are taken into account. The control signal clip_offs can be used to increase or decrease this range. A grey-counter gives information whether enough pixels with values in the grey range are present in a video field (control output: grey_cnt). When this number is lower than a predefined threshold, e.g. for complete fields towards black or white, all blocks are taken into account. The read operation starts with a reset (RSTRint) of the read address pointer during the read enable (REint) LOW phase. The RSTRint LOW-to-HIGH transition, referred to the rising edge of the read clock SRCKint, must be at least 18 clock cycles ahead of the first read data (REint HIGH) and 18 clock cycles after the last read data. The reset read resets the read counter to the lowest address and requests a read operation of the data of the lowest address to the serial read register. Read enable (REint) is used to enable or disable the read operation. The REint controls the data outputs Q0 to Q15. REint HIGH increments the read counter. 7.2 7.2.1 Embedded DRAM 3.5-MBIT FIELD MEMORY In parallel to the write operation a read2 operation is done using the same control signals as the write operation: SWCKint, WEint and RSTWint. It reads the old data of the previous field. The data Qold is needed as data input (Dfielddelay) for the noise reduction. The basic functionality of the field memory, which is shown in Fig.5, is similar to the SAA4956TJ. The memory size is extended to 3538944 bits. The data path is 16-bit wide (8-bit chrominance and 8-bit luminance). The field memory is capable of storing, for example, up to 307 video lines of 720 pixels in a 4 : 2 : 2 format. After writing or reading 18 words of 16-bit width, a data transfer is performed from the serial to parallel data registers (writing) or from the parallel to the serial registers (reading). The field memory has one write interface (controller and registers) to store 1fH data and two read interfaces, one to read field delayed 1fH data for the noise reduction function and the other to read 2fH data for the following data processing. Since two asynchronous clock domains are involved (SWCKint as 1fH clock and SRCKint as 2fH clock) the read and write access to the memory array is controlled asynchronously by the memory arbitration logic triggered via request and acknowledge pulses. When the WEint signal is HIGH it indicates that active video (valid 1fH data) is to be stored. The start of WEint HIGH is triggered by the H and V status bits of the ITU data stream. The start of WEint HIGH can be delayed by the control signals weint_hstart (number of clock delays) and weint_vstart (number of video lines delay). The stop of WEint HIGH is controlled by weint_hstop and weint_vstop. When the IEint signal is HIGH it indicates that active video (valid 1fH data) is also to be stored. The video data is not stored and earlier written data is maintained (frozen) if WEint is HIGH and IEint is LOW. The start of IEint HIGH is triggered by the H and V status bits of the ITU data stream. The start of IEint HIGH can be delayed by the control signals ieint_hstart (number of clock delays) and ieint_vstart (number of video lines delay). The stop of IEint HIGH is controlled by ieint_hstop and ieint_vstop. The write operation starts with a reset write (RSTWint) address pointer operation during the write enable (WEint) LOW phase. The RSTWint LOW-to-HIGH transition, referred to the rising edge of the write clock SWCKint, must be at least 18 clock cycles ahead of the first written data (WEint HIGH) and 18 clock cycles after the last written data. The reset write transfers data temporarily stored in the serial write registers to the memory array and resets the write counter to the lowest address. Write enable (WEint) is used to enable or disable a data write operation. The WEint signal controls the data inputs D0 to D15. 2002 May 28 RSTWint is triggered by the V status bit of the ITU data stream. RSTRint is identical to the VD output signal. REint is provided by the following sample rate conversion to gather 2fH data if it is needed. 14 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979H D15 to D0 and IEint handbook, full pagewidth WEint RSTWint SWCKint 17 SERIAL WRITE CONTROLLER write control (requests reset/next) SERIAL WRITE REGISTER 18-WORD (× 17) 18 × (16 + 1) PARALLEL WRITE REGISTER 18-WORD (× 17) 18 × (16 + 1) WRITE ADDRESS COUNTER READ2 ADDRESS COUNTER address and control MEMORY ARRAY MEMORY ARBITRATION LOGIC 221184-WORD (× 16) READ ADDRESS COUNTER 18 × 16 PARALLEL READ2 REGISTER 18-WORD (×16) 18 × 16 PARALLEL READ REGISTER 18-WORD (× 16) 18 × 16 18 × 16 SERIAL READ2 REGISTER 18-WORD (× 16) SERIAL READ REGISTER 18-WORD (× 16) read control (requests reset/next) read2 control (requests reset/next) read2 acknowledge SERIAL READ2 CONTROLLER SERIAL READ CONTROLLER 16 WEint RSTWint SWCKint 16 Qold15 to Qold0 Q15 to Q0 REint RSTRint SRCKint Fig.5 Schematic diagram of 3.5-Mbit field memory. 2002 May 28 read acknowledge 15 MHC190 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port 7.3 Digital processing at 2fH level 7.3.1 An internal bandwidth detector is implemented to detect whether the colour difference signals provide either the full 4 : 2 : 2 bandwidth or a reduced 4 : 1 : 1 bandwidth. Therefore absolute differences between original data and downsampled data are calculated and can be read out by the microcontroller (control output: UV_bw_detect). Low absolute differences indicate that the original data does not contain the full 4 : 2 : 2 bandwidth. This information can be used to switch the upsample and downsample filter on or off (control inputs: bypass_upsampling and bypass_downsampling). Bandwidth detection is done within a programmable window (control inputs: bw_hstart, bw_hstop and bw_vstart, bw_vstop). SAMPLE RATE CONVERSION The sample rate conversion block is used to obtain 848 active pixels per line out of the original 720 pixels according to the relation of the two sampling frequencies (32 MHz and 27 MHz). The interpolation for phase positions between the original samples is achieved with a variable phase delay filter with 10 taps for luminance signals and 6 taps for chrominance signals. The conversion to a higher sample frequency of 32 MHz is done to improve the motion estimation performance in combination with external feature ICs, which can process up to 848 pixels per line at a 32 MHz clock. Bypassing this function keeps the original 720 pixels per line (control input: bypass_FSRC). 7.3.2 In the event of a 4 : 1 : 1 format at the input an upconverter to 4 : 2 : 2 is applied with a linear interpolation filter for creation of the extra samples. These are combined with the original samples from the 4 : 1 : 1 stream. EXPANSION PORT The first phase of the YUV data stream is available on the output bus two clock cycles after the rising edge of the REI input signal. The start position, when the first phase of the YUV data stream arrives on the input bus, can be set via the control register exp_hstart. For a further extension of the system an expansion port is available, which is applicable for either a 4 : 2 : 2 format or a reduced 4 : 1 : 1 format for data input and output at a 32 MHz line-locked clock; see Table 3. However, the internal data is processed in a 8-bit wide 4 : 2 : 2 format. The luminance output signal is in 8-bit straight binary format, whereas the chrominance output signals are in twos complement format. The input data at the expansion slot is expected in the same format. U and V input signals are inverted if the corresponding control bit mid_uv_inv is set. To generate the 4 : 1 : 1 format at the output the U and V samples from the 4 : 2 : 2 data stream are filtered by a low-pass filter, before being subsampled with a factor of 2 and formatted to 4 : 1 : 1 format. Bypassing this function keeps the data in the 4 : 2 : 2 format. Table 3 SAA4979H YUV formats OUTPUT PIN YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 UVO7 UVO6 UVO5 UVO4 UVO3 UVO2 UVO1 UVO0 2002 May 28 4 : 1 : 1 FORMAT Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 V07 V06 − − − − Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04 − − − − 4 : 2 : 2 FORMAT Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U03 U02 V03 V02 − − − − Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U01 U00 V01 V00 − − − − 16 Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 U05 U04 U03 U02 U01 U00 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 V07 V06 V05 V04 V03 V02 V01 V00 INPUT PIN YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 UVI7 UVI6 UVI5 UVI4 UVI3 UVI2 UVI1 UVI0 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port 7.3.3 SAA4979H mode, which avoids discolourations in transients within a colour component. PANORAMIC ZOOM The panoramic zoom block contains a second sample rate converter, which performs the following tasks: 7.3.5 • Linear horizontal sample rate conversion in both zoom and compress direction, with a sample rate conversion factor between 0 and 2, meaning infinite zoom up to a compression with a factor of 2 HORIZONTAL SMART Y PEAKING A linear peaking is applied, which amplifies the luminance signal in the middle and the upper ranges of the bandwidth. • Dynamic sample rate conversion e.g. for panorama mode display of 4 : 3 material on a 16 : 9 screen. The filtering is an addition of: For linear horizontal zoom or compression the sample rate conversion factor is static during a video line (control input: c0). Positive values of c0 are suitable for compression, negative values result in expansion. • The original signal high-passed with maximum gain at a frequency of 1⁄2fs (sample frequency fs = 32 MHz) In panorama mode the video lines are geometrically expanded towards the sides. The sample rate conversion factor is modulated along the video line. A parabolic shape of the sample rate conversion factor can be obtained with the parameter c2, which controls the second order variation of the sample rate. Negative values of c2 are suitable for panorama mode, positive values result in the inverse mode (amaronap mode). • The original signal band-passed with a centre frequency of 4.76 MHz. • The original signal • The original signal band-passed with a centre frequency of 1⁄4fs The band-passed and high-passed signals are weighted with the factors 0, 1⁄16, 2⁄16, 3⁄16, 4⁄16, 5⁄16, 6⁄16 and 8⁄16, resulting in a maximum gain difference of 2 dB per step at the centre frequencies. Coring is added to avoid amplification of low amplitudes in the high-pass and band-pass filtered signals, which are considered to be noise. The coring threshold can be programmed as 0 (off), ±4, ±8, ±12 to ±60 LSB with respect to the (signed) 10-bit signal. The panoramic zoom block also provides a dynamically controlled delay with an accuracy up to 1⁄64 of a pixel and a range of −0.5 to +0.5 lines (control input: hshift). Sufficient accuracy in interpolation for phase positions between the original samples is achieved with a variable phase delay filter with 10 taps for luminance signals and 6 taps for chrominance signals. 7.3.4 In addition the peaking gain can be reduced depending on the signal amplitude, programming range 0 (no attenuation), 1⁄4, 2⁄4 and 4⁄4. It is also possible to make larger undershoots than overshoots, programming range 0 (no attenuation of undershoots), 1⁄4, 2⁄4 and 4⁄4. DIGITAL COLOUR TRANSIENT IMPROVEMENT A steepness detector is built-in, which provides information for dynamic control of the peaking. For that the maximum absolute value of the band-pass filtered signal within a video field is calculated and can be read out by the microcontroller (control output: steepness_max). The Digital Colour Transient Improvement (DCTI) is intended for U and V signals originating from a 4 : 1 : 1 source. Horizontal transients are detected and enhanced without overshoots by differentiating, make absolute and again differentiating the U and V signals separately. This results in a 4 : 4 : 4 U and V bandwidth. To prevent third-harmonic distortion, which is typical for this processing, a so called over the hill protection prevents peak signals becoming distorted. 7.3.6 The non-linear phase filter adjusts possible group delay differences in the Y, U and V output channels. The filter coefficients are: [−λ × (1 − µ); 1 + λ; −λ × µ] where λ determines the strength of the filter and µ determines the asymmetry. The effect of the asymmetry is a decrease in the delay for higher frequencies with µ ≤ 0.5. Control settings are provided for λ = 0, 1⁄8, 2⁄8, 3⁄8 and µ = 0, 1⁄4, 1⁄2. It is possible to control the following settings via the microcontroller: gain width (see Fig.10), threshold (i.e. immunity against noise), selection of simple or improved first differentiating filter (see Fig.9), limit for pixel shift range (see Fig.11), common or separate processing of U and V signals, hill protection mode (i.e. no discolourations in narrow colour gaps), low-pass filtering for U and V signals (see Fig.12) and a so called super hill 2002 May 28 NON-LINEAR PHASE FILTER 17 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port 7.3.7 The range of the Y output signal can be chosen between 9 and 10 bits (control input: output_range). In the event of 9 bits for the nominal signal there is room left for under and overshoot, adding up to a total of 10 bits. In the event of selecting all 10 bits of the luminance digital-to-analog converter for the nominal signal any under or overshoot will be clipped (see Fig.6). POST PROCESSING Blanking is done just before the digital-to-analog conversion by switching Y to a fixed black value and UV to a colourless value. The blanking window is defined by the control inputs: bln_hstart, bln_hstop, bln_vstart and bln_vstop. Side panels are generated by switching the Y, U and V to defined values within a horizontal window (control inputs: sidepanel_hstart and sidepanel_hstop); the 8 MSBs of Y and the 4 MSBs of U and V are programmable (control inputs: sidepanel_y, sidepanel_u and sidepanel_v). The Y samples can be shifted onto 16 positions with respect to the UV samples (control input: y_delay). The zero delay setting is suitable for the nominal case of aligned input data. The other settings provide eight samples with less delay to seven samples with more delay in Y. Framing e.g. for picture-in-picture mode, can be achieved by another programmable window (control inputs: PIP_frame_hstart, PIP_frame_hstop, PIP_frame_vstart and PIP_frame_vstop). The vertical and horizontal frame width can be programmed from 1 up to 15 pixels (control inputs: PIP_frame_heigth and PIP_frame_width). Framing uses the same colour and luminance values as the side panels. (255) 1023 handbook, full pagewidth (235) 940 7.4 Triple 10-bit digital-to-analog conversion Three identical 10-bit converters are used to map the 4 : 4 : 4 YUV data to analog levels with a 32 MHz data rate. The polarity of the colour difference signals U and V is switchable by the control bit uv_inv_out. The output ranges are illustrated in Figs 6 and 7 respectively. VOY + 1.095 V VOY + 1.0 V white SAA4979H VOY + 1.674 V 1023 (255) 766 (235) 727 white 1.0 V (p-p) 1.0 V (p-p) (16) 288 (0) 256 (16) 64 (0) 0 black VOY + 1.0 V VOY VOY − 0.073 V 0 black VOY VOY − 0.656 V MHC191 a. Output range = 1. b. Output range = 0. Fig.6 Luminance output levels. 2002 May 28 18 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port (255) 1023 handbook, full pagewidth (212) 848 (128) 512 blue 75% colourless VOU + 1.012 V (255) 1023 VOU + 0.665 V (212) 848 VOU (128) 512 VOV + 0.8 V red 75% yellow 75% (0) 0 VOV + 0.575 V colourless 1.33 V (p-p) (44) 176 SAA4979H VOV 1.05 V (p-p) VOU − 0.665 V (44) 176 VOU − 1.012 V (0) 0 cyan 75% VOV − 0.575 V VOV − 0.8 V MHC192 a. U output level. b. V output level. Fig.7 Chrominance output levels. 7.5 The I2C-bus slave address of the SAA4979H is 0110100 R/W. During slave transmit mode the SCL LOW period may be extended by pulling SCL to LOW (in accordance with the I2C-bus specification). Microcontroller The SAA4979H contains an embedded 80C51 microcontroller core including 512-byte RAM and 32-Kbyte ROM. The microcontroller runs on a 16 MHz clock, generated by dividing the 32 MHz display clock by a factor of 2. 7.5.1 Detailed information about the software dependent I2C-bus subaddresses of the control registers and a detailed description of the transmission protocol can be found in Application Note “I2C-bus register specification of the SAA4979H”. HOST INTERFACE For controlling internal registers a host interface, consisting of a parallel address and data bus, is built-in. The interface can be addressed as internal AUXRAM via a MOVX type of instruction. The complete range of internal control registers and the corresponding host addresses are described in Section 8.1. User access to these control registers via the I2C-bus can be implemented in the embedded software. 7.5.2 7.5.3 A SNERT interface is built-in, which operates in a master receive and transmit mode for communication with peripheral circuits such as SAA4991WP or SAA4992H. The SNERT interface replaces the standard UART interface. Contrary to the 80C51 UART interface there are additional special function registers (see Table 10) and there is no byte separation time between address and data. I2C-BUS INTERFACE The I2C-bus interface in the SAA4979H is used in a slave receive and transmit mode for communication with a central system microcontroller. The standardized bus frequencies of both 100 kHz and 400 kHz can be accommodated. 2002 May 28 SNERT-BUS INTERFACE 19 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port The system controller is connected to the microcontroller via the host interface. The SNERT interface transforms the parallel data from the microcontroller into 1 or 2 Mbaud SNERT data, switchable via microcontroller. The SNERT-bus consists of three signals: SNCL used as serial clock signal, generated by the SNERT interface; SNDA used as bidirectional data line and SNRST used as reset signal, generated by the microcontroller at port pin P1.0 to indicate the start of a transmission. 7.6.1 7.6.2 I/O PORTS 7.6.3 WATCHDOG TIMER 7.6.4 7.6.5 VERTICAL DEFLECTION The Vertical Deflection (VD) signal is for driving a deflection circuit. This signal has a cycle time of 10 ms and the start and stop values of the vertical position are programmable in steps of 16 µs (control inputs: vd_start and vd_stop). RESET 7.6.6 System controller AUXILIARY DISPLAY SIGNAL The Auxiliary Display Signal (ADS) is for general purposes; the horizontal and vertical positions are programmable (control inputs: ads_hstart, ads_hstop, ads_vstart and ads_vstop). The system controller provides all necessary internal read and write signals for controlling the embedded field memory. The required control signals (REO and IE) for applications with motion compensation circuits and the drive signals (HD and VD) for the horizontal and vertical deflection power stages are also generated. 7.6.7 READ ENABLE 2 The Read Enable 2 (RE2) signal is intended for control of an external field memory at input channel 2 in picture-in-picture applications. It is a composite signal consisting of a horizontal and a vertical part. The horizontal and vertical positions are programmable (control inputs: re2_hstart, re2_hstop, re2_vstart and re2_vstop). The system controller also supports double window or picture-in-picture processing in combination with an external field memory by providing the required memory control signals (RE2, RSTW2 and OIE2). 2002 May 28 HORIZONTAL DEFLECTION The Horizontal Deflection (HD) signal is for driving a deflection circuit; start and stop values of the horizontal position are programmable in a resolution of 4 clock cycles (control inputs: hd_start and hd_stop). A reset is accomplished by holding the RST pin HIGH for at least 0.75 µs while the display clock is running and the supply voltage is stabilized. 7.6 INPUT ENABLE The Input Enable (IE) signal is intended for control of field memories in applications together with an external feature IC connected to the expansion port. It can be directly set or reset via the microcontroller. The microcontroller contains an internal Watchdog timer, which can be activated by setting the corresponding special function register PCON.4. Only a synchronous reset will clear this bit. To prevent a system reset the Watchdog timer must be reloaded within a specified time. The Watchdog timer contains an 11-bit prescaler and is therefore incremented every 0.768 ms (16 MHz clock). The time interval between the timers reloading and the occurrence of a reset depends on the reloaded 8-bit value. 7.5.6 READ ENABLE INPUT The Read Enable Input (REI) signal is used in applications with external feature ICs connected to the expansion port. It has to be provided by the external circuit (see Section 7.3.2). A parallel 8-bit I/O port (P1) is available, where P1.0 is used as SNERT reset signal (SNRST), P1.2 to P1.5 can be used for application specific control signals, and P1.6 and P1.7 are used as I2C-bus signals (SCL and SDA). 7.5.5 READ ENABLE OUTPUT The Read Enable Output (REO) signal is intended for control of an external feature IC. It is a composite signal consisting of a horizontal and a vertical part. The horizontal and vertical positions are programmable (control inputs: reo_hstart, reo_hstop, reo_vstart and reo_vstop). The read or write operation must be set by the microcontroller. When writing to the bus, 2 bytes are loaded by the microcontroller: one for the address, the other for the data. When reading from the bus, one byte is loaded by the microcontroller for the address, the received byte is the data from the addressed SNERT location. 7.5.4 SAA4979H 20 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port 7.6.8 OUTPUT/INPUT ENABLE 2 7.7 RESET READ 2 7.8 The Reset Read 2 (RSTR2) signal is intended for control of the read access of an external field memory at input channel 2 in picture-in-picture applications. It is derived from the internal vertical reference signal of the main channel. 7.6.10 Boundary scan test The SAA4979H has built-in logic and 6 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA4979H follows the “IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan Architecture” set by the Joint Test Action Group (JTAG) chaired by Philips. RESET WRITE 2 The 6 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST), Test Data Input (TDI), Boundary-scan Compliant Enable (BCE) and Test Data Output (TDO). To achieve compliance to the “IEEE Std. 1149.1” a logic HIGH has to be applied to the BCE pin. Internal pull-up resistors at the input pins TMS, TRST and TDI are not implemented. The Reset Write 2 (RSTW2) input is used in picture-in-picture applications with an external field memory at input channel 2, and has to be provided by an external circuit which controls the field memory write access. 8 Line-locked clock generation An internal PLL generates the 32 MHz line-locked display clock CLK32. The PLL consists of a ring oscillator, DTO and digital control loop. The PLL characteristic is controlled by means of the microcontroller. The Output/Input Enable 2 (OIE2) signal is intended for control of one or two external field memories at input channel 2 in picture-in-picture applications. It can be directly set or reset via the microcontroller. 7.6.9 SAA4979H CONTROL REGISTER DESCRIPTION 8.1 Host interface detail Table 4 Write register at 1fH HOST ADDRESS (HEX) BIT NAME DESCRIPTION Host address 0102H to 011CH (system control) 0102 0 to 7 weint_vstart write enable internal memory vertical start (lower 8 of 9 bits) 0103 0 to 7 weint_vstop write enable internal memory vertical stop (lower 8 of 9 bits) 0104 0 weint_vstart (MSB) write enable internal memory vertical start (MSB) 1 weint_vstop (MSB) write enable internal memory vertical stop (MSB) 2 fm1_still still picture mode; 0 = normal mode, 1 = still picture mode 3 pip_2fm_dc direct controlled PIP mode; 0 = normal mode, 1 = direct mode 4 sfr field recognition mode; 0 = normal mode, 1 = inverse mode 5 sfm single field mode; 0 = normal mode, 1 = single field mode 6 re2_vstart (MSB) read enable PIP window vertical start (MSB) 7 re2_vstop (MSB) read enable PIP window vertical stop (MSB) 0105 0 to 7 re2_vstart read enable PIP window vertical start (lower 8 of 9 bits) 0106 0 to 7 re2_vstop read enable PIP window vertical stop (lower 8 of 9 bits) 0107 0 to 7 re2_hstart read enable PIP window horizontal start (lower 8 of 10 bits) 0108 0 to 7 re2_hstop read enable PIP window horizontal stop (lower 8 of 10 bits) 2002 May 28 21 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port HOST ADDRESS (HEX) 0109 BIT NAME SAA4979H DESCRIPTION 0 to 3 min_dist_maintosub minimum distance between main and sub channel 4 pip_raster_corr PIP raster correction; 0 = off, 1 = on 5 pip_on PIP mode; 0 = off, 1 = on 6 pip_2field PIP 2-field mode; 0 = single field mode, 1 = 2-field mode 7 mpip_on multi-PIP mode; 0 = off, 1 = on 010A 0 to 7 dispvpos vertical position of the display related to acquisition 0112 0 to 7 weint_hstart write enable internal memory horizontal start (lower 8 of 10 bits) 0113 0 to 7 weint_hstop write enable internal memory horizontal stop (lower 8 of 10 bits) 0114 0 to 1 weint_hstart (MSBs) write enable internal memory horizontal start (higher 2 of 10 bits) 2 to 3 weint_hstop (MSBs) write enable internal memory horizontal stop (higher 2 of 10 bits) 4 to 5 re2_hstart (MSBs) read enable PIP window horizontal start (higher 2 of 10 bits) 6 to 7 re2_hstop (MSBs) read enable PIP window horizontal stop (higher 2 of 10 bits) 0116 0 to 7 h656int_hstart internal H reference horizontal start; 4 pixel resolution 0117 0 to 7 h656int_hstop internal H reference horizontal stop; 4 pixel resolution 0118 0 to 7 ieint_hstart input enable internal memory horizontal start (lower 8 of 10 bits) 0119 0 to 7 ieint_hstop input enable internal memory horizontal stop (lower 8 of 10 bits) 011A 0 to 7 ieint_vstart input enable internal memory vertical start (lower 8 of 10 bits) 011B 0 to 7 ieint_vstop input enable internal memory vertical stop (lower 8 of 10 bits) 011C 0 to 1 ieint_hstart (MSBs) input enable internal memory horizontal start (higher 2 of 10 bits) 2 to 3 ieint_hstop (MSBs) input enable internal memory horizontal stop (higher 2 of 10 bits) 4 ieint_vstart (MSB) input enable internal memory vertical start (MSB) 5 ieint_vstop (MSB) input enable internal memory vertical stop (MSB) 6 to 7 − reserved Host address 0185H to 018EH (noise estimator) 0185 0186 0 to 1 ypscale scale of prefilter coefficients: (1⁄1, 1⁄2, 1⁄4, bypass prefilter) 2 to 5 compensate compensation value (4-bit signed) 6 to 7 − reserved 0 to 2 gain_upbnd gain of upper boundary: 0, 1, 2, 3, 4, 5, 6 and 7 3 sob_negl neglect sum over block value if HIGH 4 sel_sob_negl enable of control bit sob_negl: 0 = disable, 1 = enable 5 to 6 clip_offs 7 − clip offset: 1, 2, 4 and 8 reserved 0187 0 to 7 wanted_value wanted value in steps of 1⁄256%, i.e. predefined number of estimates; range: 0 to 255⁄256% 0188 0 to 7 lb_detail lower boundary of detail counter 0189 0 to 7 upb_detail upper boundary of detail counter 018A 0 to 7 ne_hstart noise measurement window horizontal start; 4 pixel resolution 018B 0 to 7 ne_hstop noise measurement window horizontal stop; 4 pixel resolution 018C 0 to 7 ne_vstart noise measurement window vertical start (lower 8 of 9 bits) 2002 May 28 22 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port HOST ADDRESS (HEX) BIT NAME SAA4979H DESCRIPTION 018D 0 to 7 ne_vstop noise measurement window vertical stop (lower 8 of 9 bits) 018E 0 ne_vstart (MSB) noise measurement window vertical start (MSB) 1 ne_vstop (MSB) noise measurement window vertical stop (MSB) 2 to 7 − reserved Host address 018FH (front-end control) 018F 0 Select_data_input1 select data input for main channel: 0 = input 2, 1 = input 1 1 uv_sign1 UV sign of main channel 1: 0 = unsigned, 1 = signed 2 uv_sign2 UV sign of sub channel 2: 0 = unsigned, 1 = signed 3 to 7 − reserved Host address 0190H to 0196H (noise reduction) 0190 0191 0192 0193 0194 0195 0196 0 to 3 Kstep0 step in adaptive curve from K = 1⁄16 to K = 1⁄8; weight of 1 4 to 7 Kstep1 step in adaptive curve from K = 1⁄8 to K = 2⁄8; weight of 1 0 to 3 Kstep2 step in adaptive curve from K = 2⁄8 to K = 3⁄8; weight of 2 4 to 7 Kstep3 step in adaptive curve from K = 3⁄8 to K = 4⁄8; weight of 2 0 to 3 Kstep4 step in adaptive curve from K = 4⁄8 to K = 5⁄8; weight of 4 4 to 7 Kstep5 step in adaptive curve from K = 5⁄8 to K = 6⁄8; weight of 4 0 to 3 Kstep6 step in adaptive curve from K = 6⁄8 to K = 7⁄8; weight of 8 4 to 7 Kstep7 step in adaptive curve from K = 7⁄8 to K = 8⁄8; weight of 8 0 to 3 Klumafix value of the fixed K factor of the luminance; see Table 6 4 to 6 Yadapt_gain value of the gain of the adaptive curve of the luminance; see Table 5 7 adaptive (lumafix = 0) or fixed K mode (lumafix = 1) of the luminance lumafix 0 to 3 Kchromafix value of the fixed K factor of the chrominance; see Table 6 4 to 6 Cadapt_gain value of the gain of the adaptive curve of the chrominance; see Table 5 7 chromafix adaptive (chromafix = 0) or fixed K mode (chromafix = 1) of chrominance 0 Klumatochr if HIGH: uses luminance K factor for chrominance path 1 unfiltered if HIGH: band splitting is deactivated, complete difference signals are used 2 noiseshape if HIGH: noise shaping is activated 3 splitscreen if HIGH: split screen demo mode is activated 4 NREN noise reduction enable; 0 = off; 1 = on 5 to 7 − reserved Host address 019AH to 019FH (black bar detection) 019A 019B 019C 2002 May 28 0 to 5 bbd_event_value black bar detection event value 6 to 7 − reserved 0 to 5 bbd_slice_level black bar detection slice level 6 bbd_vstop (MSB) black bar detection window vertical stop (MSB) 7 bbd_vstart (MSB) black bar detection window vertical start (MSB) 0 to 7 bbd_hstart black bar detection window horizontal start; 4 pixel resolution 23 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port HOST ADDRESS (HEX) BIT NAME SAA4979H DESCRIPTION 019D 0 to 7 bbd_hstop black bar detection window horizontal stop; 4 pixel resolution 019E 0 to 7 bbd_vstart black bar detection window vertical start (lower 8 of 9 bits) 019F 0 to 7 bbd_vstop black bar detection window vertical stop (lower 8 of 9 bits) Table 5 Gain settings of adaptive values for chrominance and luminance Yadapt_gain/Cadapt_gain [2:0] GAIN Table 6 HEX DECIMAL 00 0 01 1 02 2 03 3 04 4 05 5 06 6 07 7 1⁄ 8 2⁄ 8 4⁄ 8 8⁄ 8 16⁄ 8 32⁄ 8 64⁄ 8 128⁄ 8 Settings of fixed K factor values Klumafix/Kchromafix [3:0] K factor 2002 May 28 HEX DECIMAL 00 0 0 01 1 1⁄ 02 2 2⁄ 16 03 3 3⁄ 16 04 4 4⁄ 16 05 5 5⁄ 16 06 6 6⁄ 16 07 7 7⁄ 16 08 8 8⁄ 16 9⁄ 09 9 0A 10 0B 11 0C 12 0D 13 0E 14 0F 15 24 16 16 10⁄ 16 11⁄ 16 12⁄ 16 13⁄ 16 14⁄ 16 16⁄ 16 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port Table 7 SAA4979H Write register at 2fH HOST ADDRESS (HEX) BIT NAME DESCRIPTION Host address 0222H to 023FH (system control) 0222 0 to 7 vd_vstart vertical deflection pulse start (lower 8 of 11 bits) 0223 0 to 7 vd_vstop vertical deflection pulse stop (lower 8 of 11 bits) 0224 0 to 7 reo_vstart read enable output window vertical start (lower 8 of 10 bits) 0225 0 to 7 reo_vstop read enable output window vertical stop (lower 8 of 10 bits) 0226 0 to 3 dspflds number of display fields minus 1 4 to 7 − reserved 0 to 1 reo_vstart (MSBs) read enable output window vertical start (higher 2 of 10 bits) 0227 0228 2 to 3 reo_vstop (MSBs) read enable output window vertical stop (higher 2 of 10 bits) 4 to 7 − reserved 0 to 2 vd_vstart (MSBs) vertical deflection pulse start (higher 3 of 11 bits) 3 to 4 vd_vstop (MSBs) vertical deflection pulse start (higher 3 of 11 bits) 6 to 7 − reserved 0229 0 to 7 ads_hstart auxiliary display signal horizontal start (lower 8 of 10 bits) 022A 0 to 7 ads_hstop auxiliary display signal horizontal stop (lower 8 of 10 bits) 022B 0 vres_dis internal vertical reset; 0 = enable; 1 = disable 1 crn_direct direct vertical frame synchronization; 0 = disable; 1 = enable 2 dr_aabb display raster mode; 0 = standard VD synchronization; 1 = AABB synchronization; VD delayed for the first 50 Hz field 3 − reserved 4 gen_mode generator mode; 0 = off; 1 = on 5 ie_fm2 input enable signal (output IE) 6 smooth_lock smooth lock synchronization mode; 0 = off; 1 = on 7 − reserved 022C 0 to 7 ads_vstart auxiliary display signal vertical start (lower 8 of 10 bits) 022D 0 to 7 ads_vstop auxiliary display signal vertical stop (lower 8 of 10 bits) 022E 0 to 1 ads_hstart (MSBs) auxiliary display signal horizontal start (higher 2 of 10 bits) 2 to 3 ads_hstop (MSBs) auxiliary display signal horizontal stop (higher 2 of 10 bits) 4 to 5 ads_vstart (MSBs) auxiliary display signal vertical start (higher 2 of 10 bits) 6 to 7 ads_vstop (MSBs) auxiliary display signal vertical stop (higher 2 of 10 bits) 0230 0 to 7 hd_hstart horizontal deflection pulse start; 4 pixels resolution 0231 0 to 7 hd_hstop horizontal deflection pulse stop; 4 pixels resolution 0234 0 to 7 reo_hstart read enable output window horizontal start (lower 8 of 10 bits) 0235 0 to 7 reo_hstop read enable output window horizontal stop (lower 8 of 10 bits) 0238 0 to 1 reo_hstart (MSBs) read enable output window horizontal start (higher 2 of 10 bits) 023A 2002 May 28 2 to 3 reo_hstop (MSBs) read enable output window horizontal stop (higher 2 of 10 bits) 4 to 7 − reserved 0 to 7 fl display field length (lower 8 of 11 bits) 25 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port HOST ADDRESS (HEX) 023B BIT NAME SAA4979H DESCRIPTION 0 to 2 fl (MSBs) display field length (higher 3 of 11 bits) 3 to 7 − reserved 023C 0 to 7 hp1 frame synchronization pulse position; 4 pixels resolution 023D 0 to 7 dsplock_vstart display locking window vertical start (lower 8 of 10 bits) 023E 0 to 7 dsplock_vstop display locking window vertical stop (lower 8 of 10 bits) 023F 0 to 1 dsplock_vstart (MSBs) display locking window vertical start (higher 2 of 10 bits) 2 to 3 dsplock_vstop (MSBs) display locking window vertical stop (higher 2 of 10 bits) 4 to 7 − reserved Host address 0287H to 028DH (panoramic zoom) 0287 0 to 7 c2 compression or expansion non-linearity value 0288 0 to 7 c0 linear compression or expansion value (lower 8 of 9 bits) 0289 0 to 7 hshift (LSBs) horizontal pixel shift (lower 8 of 16 bits) 028A 0 to 7 hshift (MSBs) horizontal pixel shift (higher 8 of 16 bits) 028B 0 to 7 nrln number of lines per field (lower 8 of 10 bits) 028C 0 to 7 nrpx_div4 number of pixels per line divided-by-4 028D 0 transparent_mode bypass panoramic zoom: 0 = panoramic zoom active, 1 = bypass 1 c0 (MSB) linear compression or expansion value (MSB) 2 to 3 nrln (MSBs) number of lines per field (higher 2 of 10 bits) 4 to 7 − reserved Host address 0280H to 0284H and 0290H (mid-end control) 0280 0 to 7 mid_hstart bandwidth detection window horizontal start (lower 8 of 10 bits) 0281 0 to 7 bw_hstop bandwidth detection window horizontal stop (lower 8 of 10 bits) 0282 0 to 7 bw_hstart bandwidth detection window vertical start (lower 8 of 10 bits) 0283 0 to 7 bw_hstop bandwidth detection window vertical stop (lower 8 of 10 bits) 0284 0 to 1 bw_hstart (MSBs) bandwidth detection window horizontal start (higher 2 of 10 bits) 2 to 3 bw_hstop (MSBs) bandwidth detection window horizontal stop (higher 2 of 10 bits) 4 to 5 bw_hstart (MSBs) bandwidth detection window vertical start (higher 2 of 10 bits) 6 to 7 bw_hstop (MSBs) bandwidth detection window vertical stop (higher 2 of 10 bits) 0 bypass_downsampling bypass downsampling: 0 = downsampling active, 1 = bypass 1 mid_uv_inv inverts UVO output signals: 0 = no inversion, 1 = inversion 2 bypass_FSRC bypass Fixed Sample Rate Converter (FSRC): 0 = FSRC active, 1 = bypass 3 to 7 − reserved 0290 Host address 0298H to 029FH (back-end control) 0298 0 to 7 be_hstart back-end window horizontal start (lower 8 of 10 bits) 0299 0 to 7 be_hstop back-end window horizontal stop (lower 8 of 10 bits) 029A 0 to 7 be_hstart back-end window vertical start (lower 8 of 10 bits) 029B 0 to 7 be_hstop back-end window vertical stop (lower 8 of 10 bits) 2002 May 28 26 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port HOST ADDRESS (HEX) 029C BIT NAME SAA4979H DESCRIPTION 0 to 1 be_hstart (MSBs) 2 to 3 be_hstop (MSBs) back-end window horizontal stop (higher 2 of 10 bits) 4 to 5 be_hstart (MSBs) back-end window vertical start (higher 2 of 10 bits) 6 to 7 be_hstop (MSBs) back-end window vertical stop (higher 2 of 10 bits) 029D 0 to 7 exp_hstart expansion port input window: horizontal start (lower 8 of 10 bits) 029E 0 to 1 exp_hstart (MSBs) expansion port input window: horizontal start (higher 2 of 10 bits) 2 to 7 − reserved 0 bypass_upsampling bypass upsampling: 0 = upsampling active, 1 = bypass 1 extern_device external device multiplexer: 0 = internal, 1 = data from external device 2 to 7 − reserved 029F back-end window horizontal start (higher 2 of 10 bits) Host address 02A0H to 02A6H (dynamic horizontal smart peaking) 02A0 0 to 7 steepness_vstart steepness detection window vertical start; 4 lines resolution 02A1 0 to 7 steepness_vstop steepness detection window vertical stop; 4 lines resolution 02A2 0 to 7 steepness_hstart steepness detection window horizontal start; 4 pixels resolution 02A3 0 to 7 steepness_hstop steepness detection window horizontal stop; 4 pixels resolution 02A4 0 to 2 pk_alpha peaking α: 1⁄16 (0, 1, 2, 3, 4, 5, 6, 8) 3 to 5 pk_beta peaking β: 1⁄16 (0, 1, 2, 3, 4, 5, 6, 8) 02A5 02A6 6 and 7 − reserved 0 to 2 peaking τ: 1⁄16 (0, 1, 2, 3, 4, 5, 6, 8) pk_tau 3 and 4 pk_delta peaking amplitude dependent attenuation: 1⁄4 (0, 1, 2, 4) 5 and 6 pk_neggain peaking attenuation of undershoots: 1⁄4 (0, 1, 2, 4) 7 − reserved 0 to 3 pk_corthr peaking coring threshold: 0, ±4, ±8 , ±12 , ±16 to ±60 LSB 4 output_range output range: output range = 0: 9 bits for the nominal output signal, black level: 288 and white level: 727; output range = 1: 10 bits for the nominal output signal, black level: 64 and white level: 940 5 to 7 − reserved Host address 02A8H and 02A9H (DCTI) 02A8 02A9 0 to 2 dcti_gain DCTI gain: 0, 1, 2, 3, 4, 5, 6 and 7 3 to 6 dcti_threshold DCTI threshold: 0, 1 to 15 7 dcti_ddx_sel DCTI limit for pixel shift range: 0, 1, 2 and 3 2 dcti_separate DCTI separate processing of U and V signals; 0 = off; 1 = on 3 dcti_protection DCTI over the hill protection; 0 = off; 1 = on 4 dcti_filteron DCTI post-filter; 0 = off; 1 = on 5 dcti_superhill DCTI super hill mode; 0 = off; 1 = on 6 and 7 − 2002 May 28 DCTI selection of first differentiating filter; see Fig.9 0 and 1 dcti_limit reserved 27 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port HOST ADDRESS (HEX) BIT NAME SAA4979H DESCRIPTION Host address 02B0H to 02BBH and 02AAH (post processing) 02B0 0 to 3 sidepanel_u side panel colour U value (4 MSB) 4 to 7 sidepanel_v side panel colour V value (4 MSB) 02B1 0 to 7 sidepanel_y side panel luminance value (8 MSB) 02B2 0 to 7 sidepanel_hstart side panel start position (higher 8 of 10 bits) 02B3 0 to 7 sidepanel_hstop side panel stop position (higher 8 of 10 bits) 02B4 0 to 3 y_delay Y delay relative to UV channel, in clock cycles: −8, −7, −6, −5, −4, −3, −2, −1, 0, 1, 2, 3, 4, 5, 6, and 7 4 uv_inv_out inverts UV output signals: 0 = no inversion, 1 = inversion 5 y_dac_current gain Y digital-to-analog converter: 0 = 2 µA/bit (range 1), 1 = 4 µA/bit (range 0); see Fig.6 6 to 7 − reserved 02B5 0 to 7 bln_hstart blanking window horizontal start position (lower 8 of 10 bits) 02B6 0 to 7 bln_hstop blanking window horizontal stop position (lower 8 of 10 bits) 02B7 0 to 7 bln_vstart blanking window vertical start position (lower 8 of 10 bits) 02B8 0 to 7 bln_vstop blanking window vertical stop position (lower 8 of 10 bits) 02B9 0 to 1 bln_hstart (MSBs) blanking window horizontal start position (higher 2 of 10 bits) 2 to 3 bln_hstop (MSBs) blanking window horizontal stop position (higher 2 of 10 bits) 4 to 5 bln_vstart (MSBs) blanking window vertical start position (higher 2 of 10 bits) 6 to 7 bln_vstop (MSBs) blanking window vertical stop position (higher 2 of 10 bits) 0 to 1 nlp_u non-linear phase filter settings µ: (0, 1⁄4, 1⁄2, 1⁄2) 2 to 3 nlp_l non-linear phase filter settings λ: (0, 1⁄8, 2⁄8, 3⁄8) 4 to 5 sidepanel_hstart (LSBs) side panel start position (lower 2 of 10 bits) 6 to 7 sidepanel_hstop (LSBs) side panel stop position (lower 2 of 10 bits) 02BB 0 to 7 PIP_frame_hstart PIP frame: horizontal start position (lower 8 of 10 bits) 02BC 0 to 7 PIP_frame_hstop PIP frame: horizontal stop position (lower 8 of 10 bits) 02BD 0 to 7 PIP_frame_vstart PIP frame: vertical start position (lower 8 of 10 bits) 02BE 0 to 7 PIP_frame_vstop PIP frame: vertical stop position (lower 8 of 10 bits) 02BF 0 to 1 PIP_frame_vstart (MSBs) PIP frame: vertical start position (higher 2 of 10 bits) 2 to 3 PIP_frame_vstop (MSBs) PIP frame: vertical stop position (higher 2 of 10 bits) 4 to 5 PIP_frame_hstart (MSBs) PIP frame: horizontal start position (higher 2 of 10 bits) 6 to 7 PIP_frame_hstop (MSBs) PIP frame: horizontal stop position (higher 2 of 10 bits) 0 to 3 PIP_frame_width (MSBs) PIP horizontal frame width (0 to 15 pixel) 4 to 7 PIP_frame_height (MSBs) PIP vertical frame width (0 to 15 pixel) 02BA 02AA 2002 May 28 28 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port HOST ADDRESS (HEX) BIT NAME SAA4979H DESCRIPTION Host address 0300H to 0305H (PLL) 0300 0301 0 to 2 PLL_cd_value damping factor 3 to 7 PLL_ck_value time constant 0 to 1 − reserved 2 to 4 PLL_idto (MSBs) signed increment offset of DTO (MSBs) 5 0 to be cleared 6 PLL_off_hif freeze frequency 7 PLL_open disable outer loop: 0 = outer loop closed, 1 = outer loop open 0302 0 to 7 PLL_idto2 signed increment offset of DTO (higher byte) 0303 0 to 7 PLL_idto1 signed increment offset of DTO (lower byte) 0304 0 PLL_freq_shift operating frequency shift: 0 = no shift, 1 = frequency shift of 8% 1 PLL_limiter_off PLL frequency limiter of outer loop: 0 = limiter on, 1 = limiter off 2 to 7 − reserved 0 to 2 PLL_cd_adapt damping factor in adaptive mode 3 to 7 PLL_ck_adapt time constant in adaptive mode 0305 Table 8 Read register at 1fH HOST ADDRESS (HEX) BIT NAME DESCRIPTION Host address 0142H and 0143H (system control) 0142 0 to 7 fieldinf result of field length measurement (lower 8 of 10 bits) 0143 0 to 1 filedinf (MSBs) result of field length measurement (higher 2 of 10 bits) 2 frg field recognition of incoming source 3 to 7 − reserved Host address 01C0H to 01C4H (noise estimator) 01C0 0 to 3 nest noise estimation result 4 to 7 − reserved 01C1 0 to 7 nest_filt noise estimation value filtered 01C2 0 to 7 detail_cnt_h output of detail counter, higher byte 01C3 0 to 7 detail_cnt_l output of detail counter, lower byte 01C4 0 to 7 grey_cnt output of grey counter Host address 01CAH and 01CBH (black bar detection) 01CA 01CB 2002 May 28 0 to 6 bbd_1st_videoline line number of first video line 7 bbd_last_videoline (MSB) line number of last video line (MSB) 0 to 7 bbd_last_videoline line number of last video line 29 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port Table 9 SAA4979H Read register at 2fH HOST ADDRESS (HEX) BIT NAME DESCRIPTION Host address 0242H (system control) 0242 0 to 3 dspflds number of display fields − 1 4 dsp_unlock display unlock: 0 = normal operation, 1 = vertical display timing unlocked 5 to 7 − reserved Host address 02C8H (UV bandwidth detection) 02C8 0 to 7 UV_bw_detect result of UV bandwidth detection (unsigned value) Host address 02D0H (dynamic peaking) 02D0 8.2 0 to 7 steepness_max result of steepness detection (unsigned value) Special Function Registers (SFRs) Table 10 SNERT-bus control SFR ADDRESS (HEX) BIT READ/WRITE NAME DESCRIPTION Special function register 9AH (SNCON); reset value: 00H 9A 0 read TRM SNERT transmit busy flag: TRM is set to logic 1 after SFR 9CH (SNWDA) is accessed, after a transmission TRM is set to logic 0 1 read and write REC SNERT receive busy flag: if REC is set to logic 1 the contents of SFR 9BH (SNADD) is transmitted, after reception is completed REC is set to logic 0 2 to 6 − − reserved 7 read and write MB2 SNERT baud rate: 0 = 1 MHz, 1 = 2 MHz Special function register 9BH (SNADD) 9B 0 to 7 write SNADD SNERT address Special function register 9CH (SNWDA) 9C 0 to 7 write SNWDA SNERT data to be transmitted Special function register 9DH (SNRDA) 9D 2002 May 28 0 to 7 read SNRDA data received from SNERT-bus 30 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979H Table 11 Power control SFR ADDRESS (HEX) BIT READ/WRITE NAME DESCRIPTION Special function register 87H (PCON); reset value: 00H 87 0 read and write IDL Idle mode bit: 0 = normal operation, 1 = Idle mode operation 1 read and write PD Power-down bit: 0 = normal operation, 1 = Power-down mode 2 to 3 − − reserved 4 read and write WLE Watchdog load enable: 0 = loading of Watchdog timer disabled, 1 = loading of Watchdog timer enabled EW enable Watchdog: 0 = Watchdog disabled, 1 = Watchdog enabled; once this bit is set only a synchronous reset can clear it 5 read and write RFI radio frequency interference bit: disables toggling of internal ALE signal during on-chip program access if set to logic 1 6 read and write ARD auxiliary RAM disable: setting this bit will force MOVX instructions to access off-chip memory instead of AUXRAM 7 − − reserved 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDDD digital supply voltage −0.5 +4.0 V VDDA analog supply voltage −0.5 +4.0 V VDDI internal I/O supply voltage −0.5 +4.0 V VDDO I/O supply voltage VDDD = 3.3 V −0.5 +3.8 V VDDP supply voltage for protection circuits −0.5 +5.5 V VI input voltage for all digital input pins VDDP = 5 V −0.5 +5.5 V VDDP = 3.3 V −0.5 +3.8 V VI input voltage for all digital I/O pins −0.5 +3.8 V IDD(tot) total supply current − 300 mA IO short circuit output current − 30 mA Ptot total power dissipation − 1.2 W Tstg storage temperature −25 +150 °C Tj junction temperature 0 +125 °C Tamb ambient temperature Ves electrostatic handling voltage 0 +70 °C note 1 −200 +200 V note 2 −2000 +2000 V Notes 1. Machine model class B, equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor (0 Ω is actually 0.75 µH + 10 Ω). 2. Human body model class B, equivalent to discharging a 100 pF capacitor through a 1500 Ω series resistor. 2002 May 28 31 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979H 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient VALUE UNIT 45 K/W in free air 11 CHARACTERISTICS VDDD = 3.0 to 3.6 V; VDDO = 3.0 to 3.6 V; VDDA = 3.15 to 3.45 V; Tamb = 0 to 70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDD digital supply voltage 3.0 3.3 3.6 V VDDA analog supply voltage 3.15 3.30 3.45 V VDDI internal I/O supply voltage 3.0 3.3 3.6 V VDDO I/O supply voltage 3.0 3.3 3.6 V VDDP protection supply voltage 3.0 5.0 5.5 V IDDD digital supply current − 120 160 mA IDDA analog supply current − 40 50 mA IDDI internal I/O supply current − 0 2 mA IDDO I/O supply current − 10 40 mA IDDP protection supply current − 0 1 mA Output transfer function (sample rate 32 MHz/10 bits) INL integral non linearity −2 − +2 LSB DNL differential non linearity −1 − +1 LSB Luminance output signal: pin YOUT Vo(p-p) Y output level (peak-to-peak value) output range = 0: nominal amplitude digital 288 to 727; output range = 1: nominal amplitude digital 64 to 940 0.94 1.00 1.06 V Vo(black) Y black level (voltage at 288) output range = 0 0.837 0.891 0.944 V Y black level (voltage at 64) output range = 1 0.836 0.889 0.942 V Ro output resistance − 75 85 Ω CL capacitive load − − 25 pF S/N signal-to-noise ratio 46 − − dB nominal amplitude; 0 to 10 MHz Colour difference output signals: pins UOUT and VOUT Vo(p-p) 2002 May 28 U output level (peak-to-peak value) for saturated colour bar with 75% of maximum amplitude 1.25 1.33 1.41 V V output level (peak-to-peak value) for saturated colour bar with 75% of maximum amplitude 0.99 1.05 1.11 V 32 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SYMBOL PARAMETER Vo(colourless) U colourless level (voltage at 512) CONDITIONS SAA4979H MIN. 1.32 TYP. 1.40 MAX. 1.48 UNIT V V colourless level (voltage at 512) 1.32 1.40 1.48 V GD(U-V) gain matching U to V − 1 3 % Ro output resistance − 75 85 Ω − − 25 pF 46 − − dB CL capacitive load S/N signal-to-noise ratio nominal amplitude; 0 to 10 MHz Digital output signals: pins OIE2, RSTR2 and RE2 VOH HIGH-level output voltage IOH = −0.5 mA 2.4 − − V VOL LOW-level output voltage IOL = 0.5 mA − − 0.4 V Digital output signals: all pins except OIE2, RSTR2 and RE2 VOH HIGH-level output voltage IOH = −2.0 mA 2.4 − − V VOL LOW-level output voltage IOL = 2.0 mA − − 0.4 V Digital input signals: pins DI1, DI2, LLC1, LLC2, RSTW2, TDI, TMS,TCK, BCE and TRST VIH HIGH-level input voltage 2 − VDDP + 0.3 V VIL LOW-level input voltage − − 0.8 V ILI input leakage current − − 10 µA Digital input signals: pins UVI, YI, REI and RST VIH HIGH-level input voltage 2.0 − 5.5 V VIL LOW-level input voltage − − 0.8 V IIH HIGH-level input current − − 100 µA IIL LOW-level input current − − 10 µA Digital input signal: pin CLKEXT VIH HIGH-level input voltage 2.0 − 5.5 V VIL LOW-level input voltage − − 0.8 V ILI input leakage current − − 10 µA Digital input/output signals: pins SNRST and P1.2 to P1.5 VOH HIGH-level output voltage IOH = −2.0 mA 2.4 − − V VOL LOW-level output voltage IOL = 2.0 mA 0 − 0.4 V VIH HIGH-level input voltage 2.0 − 3.8 V VIL LOW-level input voltage 0 − 0.8 V IIH HIGH-level input current − − 10 µA IIL LOW-level input current − − 100 µA Digital input/output signal: pin SNDA VOH HIGH-level output voltage IOH = −2.0 mA 2.4 − − V VOL LOW-level output voltage IOL = 2.0 mA 0 − 0.4 V VIH HIGH-level input voltage 2.0 − 5.5 V VIL LOW-level input voltage 0 − 0.8 V ILI input leakage current − − 10 µA 2002 May 28 33 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SYMBOL PARAMETER CONDITIONS SAA4979H MIN. TYP. MAX. UNIT Data output timing: pins OIE2, RSTR2 and RE2 (CL = 15 pF); timing referenced to LLC1 td(o) output delay time see Fig.8 − − 26 ns th(o) output hold time see Fig.8 4 − − ns Data output timing: pins YO, UVO, IE, REO, ADS, HD and VD (CL = 15 pF); timing referenced to CLK32 td(o) output delay time see Fig.8 − − 20 ns th(o) output hold time see Fig.8 3 − − ns Data input timing: pins RSTW2, DI1 and DI2; timing referenced to LLC1 tsu(i) input set-up time see Fig.8 4 − − ns th(i) input hold time see Fig.8 3 − − ns Data input timing: pins YI, UVI and REI; timing referenced to CLK32 tsu(i) input set-up time see Fig.8 4 − − ns th(i) input hold time see Fig.8 3 − − ns Clock input timing: pins LLC1 and LLC2 Tcy cycle time 34 37 40 ns δclk clock duty factor 40 50 60 % tr clock rise time see Fig.8 − − 5 ns tf clock fall time see Fig.8 − − 5 ns Clock input timing: pin CLKEXT Tcy cycle time 29.00 31.25 34.00 ns δclk clock duty factor 40 50 60 % tr clock rise time see Fig.8 − − 5 ns tf clock fall time see Fig.8 − − 5 ns Clock output timing: pin CLK32 (CL = 25 pF) Tcy cycle time 26.00 31.25 38.00 ns δclk clock duty factor 45 50 55 % tr output rise time see Fig.8 − − 4 ns tf output fall time see Fig.8 − − 4 ns locked to stable H signal − 0.4 1.0 ns V PLL function (base frequency 32 MHz) σline-line sigma value of line-to-line jitter I2C-bus signals: pins SDA and SCL; note 1 VIH HIGH-level input voltage 0.7VDDO − 5.5 VIL LOW-level input voltage − − 0.3VDDO V Vhys hysteresis voltage 0.05VDDO − − V VOL LOW-level output voltage − − 0.4 V IOL = 3.0 mA ILI input leakage current − − 10 µA fSCL SCL clock frequency − − 400 kHz tr rise time of SDA and SCL − − 0.3 µs tf fall time of SDA and SCL − − 0.3 µs 2002 May 28 34 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SYMBOL PARAMETER CONDITIONS SAA4979H MIN. TYP. MAX. UNIT tHD;STA hold time START condition 0.6 − − µs tHD;DAT data hold time 0 − 0.9 µs tLOW SCL LOW time 1.3 − − µs tHIGH SCL HIGH time 0.6 − − µs tSU;DAT data set-up time 100 − − ns tSU;STA set-up time repeated START 0.6 − − µs tSU;STO set-up time STOP condition 0.6 − − µs tBUF bus free time between a STOP and START condition 1.3 − − µs SNERT-bus timing (valid for both 1 and 2 Mbaud): pins SNDA and SNCL; note 2 tsu(i) input set-up time 80 − − ns th(i) input hold time 0 − − ns th(o) output hold time 50 − − ns tsu(o) output set-up time 260 − − ns tcy(SNCL) SNCL cycle time 500 − 1000 ns tSNRSTH SNRST pulse HIGH time 500 − − ns 200 − − ns td(SNRST-DAT) delay SNRST pulse to data Notes 1. The AC characteristics are in accordance with the I2C-bus specification for fast mode (clock frequency maximum 400 kHz). Information about the I2C-bus can be found in the brochure “I2C-bus and how to use it” (order number 9398 393 40011). 2. More information about the SNERT-bus protocol can be found in Application Note “The SNERT-bus specification” (AN95127). tr handbook, full pagewidth tf 2.4 V CLOCK 1.5 V 0.6 V t h(i) t su(i) 2.0 V INPUT DATA 0.8 V t d(o) t h(o) 2.4 V OUTPUT DATA 0.4 V MHC203 Fig.8 Timing diagram. 2002 May 28 35 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979H 12 TRANSFER FUNCTIONS MHC204 1 handbook, halfpage signal amplitude 0.8 (1) (2) 0.6 0.4 0.2 0 0 0.05 0.1 0.15 0.2 f/fs 0.25 (1) dcti_ddx_sel = 1. (2) dcti_ddx_sel = 0. Fig.9 DCTI first differentiating filter; transfer function with variation of control signal dcti_ddx_sel. handbook, full pagewidth MHC205 500 digital signal 400 amplitude (1) 300 (4) 200 (2) (3) (5) 100 0 samples −100 −200 −300 (1) (2) (3) (4) (5) input signal. gain = 1. gain = 3. gain = 5. gain = 7. −400 −500 Fig.10 DCTI with variation of gain setting (limit = 1). 2002 May 28 36 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port handbook, full pagewidth SAA4979H MHC206 500 digital signal 400 amplitude (4) (3) (2) 300 (1) 200 100 0 samples −100 −200 −300 −400 (1) (2) (3) (4) input signal. limit = 1. limit = 2. limit = 3. −500 Fig.11 DCTI with variation of limit setting (gain = 7). MHC207 1.2 handbook, halfpage signal amplitude 0.8 0.4 0 0 0.1 0.2 0.3 0.4 f/fs 0.5 Fig.12 DCTI post-filter transfer function. 2002 May 28 37 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979H MHC208 10 handbook, full pagewidth signal amplitude (dB) (7) 8 (6) (5) 6 (4) (3) 4 (2) 2 (1) 0 0 (1) (2) (3) (4) (5) (6) (7) 0.1 0.2 0.3 0.4 f/fs β = 1⁄16. β = 2⁄16. β = 3⁄16. β = 4⁄16. β = 5⁄16. β = 6⁄16. β = 8⁄16. Fig.13 Transfer function of the peaking high-pass filter with variation of β (α = 0; τ = 0). 2002 May 28 38 0.5 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979H MHC209 10 handbook, full pagewidth signal amplitude (dB) (7) 8 (6) (5) 6 (4) (3) 4 (2) 2 (1) 0 0 (1) (2) (3) (4) (5) (6) (7) 0.1 0.2 0.3 0.4 α = 1⁄16. α = 2⁄16. α = 3⁄16. α = 4⁄16. α = 5⁄16. α = 6⁄16. α = 8⁄16. Fig.14 Transfer function of the peaking band-pass with variation of α (β = 0; τ = 0). 2002 May 28 39 f/fs 0.5 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979H MHC210 10 handbook, full pagewidth signal amplitude (dB) 8 (7) (6) 6 (5) (4) 4 (3) (2) 2 (1) 0 0 0.1 0.2 0.3 0.4 (1) τ = 1⁄16. (2) τ = 2⁄16. (3) τ = 3⁄16. (4) τ = 4⁄16. (5) τ = 5⁄16. (6) τ = 6⁄16. (7) τ = 8⁄16. Fig.15 Transfer function of peaking low band-pass with variation of τ (α = 0; β = 0). handbook, halfpage output −cor_thr input cor_thr MHC193 Fig.16 Peaking coring function. 2002 May 28 40 f/fs 0.5 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979H 13 APPLICATION INFORMATION The SAA4979H supports different scan-rate upconversion concepts. The simple one is illustrated in Fig.17. In this application no further components are needed for a 100 Hz conversion based on a field repetition algorithm (AABB mode). The system can be upgraded by a vector based motion estimation and compensation function. In this case the SAA4992H together with two field memories (SAA4955) are needed (see Figs 18 and 19 respectively). In addition the SAA4979H supports field based and frame based picture-in-picture applications. To realize the full performance frame based PIP function a second video decoder (SAA7118) and two additional field memories are required (see Fig.20). 2002 May 28 41 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979H + 3.3 V handbook, full pagewidth 10 µF 8.2 kΩ + 3.3 V n.c. + 3.3 V + 3.3 V + 3.3 V RST RSTW2 8 n.c. RE2 OIE2 n.c. 6 106, 118 113 to 116, 119 to 127 5, 15, 27 1, 17, 29 64, 53, 61, 63, 89, 82, 105 104 99, 94, 117 109 19 to 26 RSTR2 n.c. 18 LLC2 83 2 4 110 28 107 108 SAA4979H CVBS MAIN YC MAIN YUVMAIN RGB MAIN LLC1 SAA7118 VIDEO DECODER SNDA 16 n.c. n.c. n.c. 16 n.c. REO 84 7 to 14 REI 81 16 n.c. 65 to 80 BCE + 3.3 V TCK + 3.3 V TDI + 3.3 V TMS TRST n.c. TDO 128 62 30 CLK32 31 34 to 41, 51, 60 32 33 42 43 44 46 48 45, 49, 50, 56 54 + 3.3 V 55 47, 52, 57 58 + 3.3 V 59 12 MHz 12 pF LOW PASS LOW PASS HD VD MHC194 Fig.17 Application diagram 1. 2002 May 28 SNCL YCRCB 24.576 MHz LOW PASS SNRST 85 to 88, 90 to 93, 95 to 98, 100 to 103 ITU 656 8 FSWMAIN n.c. 3 112 111 SCL SDA IE 42 18 pF n.c. n.c. Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979H + 3.3 V handbook, full pagewidth 10 µF 8.2 kΩ + 3.3 V n.c. + 3.3 V + 3.3 V + 3.3 V RST RSTW2 CVBS PIP 6 106, 118 113 to 116, 119 to 127 5, 15, 27 1, 17, 29 64, 53, 61, 63, 89, 82, 105 104 99, 94, 117 109 YCRCB 19 to 26 YC PIP YUVPIP RGB PIP 18 PIP MODULE ITU 656 8 RSTR2 A 110 B 107 C 108 D 85 to 88, 90 to 93, 95 to 98, 100 to 103 E 84 F 3 OIE2 FSWPIP 83 2 RE2 4 LLC1 28 112 111 SCL SDA SAA4979H LLC1 SAA7118 VIDEO DECODER 16 YCRCB 7 to 14 ITU 656 65 to 80 24.576 MHz BCE + 3.3 V TCK + 3.3 V TDI + 3.3 V TMS TRST n.c. TDO G H 16 128 62 I 30 31 34 to 41, 51, 60 32 33 42 43 LOW PASS REI 81 8 44 46 + 3.3 V 48 45, 49, 50, 56 54 55 47, 52, 57 58 + 3.3 V LOW PASS n.c. 59 12 MHz 12 pF 18 pF LOW PASS HD VD J MHC195 Fig.18 Application diagram 2 (continued in Fig.19). 2002 May 28 43 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979H handbook, full pagewidth + 3.3 V + 3.3 V 19, 22 20, 21 3 to 14 + 3.3 V + 3.3 V 20 19 A + 3.3 V 16, 21, 69, 90, 102, 113, 141, 153, 160 + 3.3 V 18, 22, 56, 57, 101, 103, 138, 142 12 23 25 26 24 2 to 13 + 3.3 V VD CLK32 SAA4955TJ 14 17 146 147 to 152, 154 to 159 15 16 18 12 27 to 38 CLK32 VD IE 1, 2, 39, 40 B SNRST SNCL C SNDA D 25 136, 139, 140, 144 27 26 31 16 E REO F 32 SAA4992H 37 to 52 33 34 60 35 G 53 H 61 to 68, 70 to 77 CLK32 I 79 24, 82 to 89, 29, 91 to 98 30 1, 15, 28, 36, 54, 59, 17, 23, 78, 81, 55, 58, 99, 105, 80, 100, 120, 121, 104, 137, 135, 145 143 n.c. TRST TMS + 3.3 V TDI + 3.3 V TDO TCK 12 n.c. + 3.3 V + 3.3 V + 3.3 V 19, 22 20, 21 3 to 14 122 to 133 107 to 112, 134 114 to 119 106 24 + 3.3 V VD CLK32 SAA4955TJ 17 12 12 27 to 38 n.c. 23 25 26 15 16 18 CLK32 VD IE 1, 2, 39, 40 J MHC196 Fig.19 Application diagram 3 (continued from Fig.18). 2002 May 28 44 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 20, 21 35 to 38 n.c. 8 7 to 14 27 to 34 SAA4955TJ SCL + 3.3 V SDA SWCK2 RSTW2 WE2 IE2 15 16 17 18 26 25 24 23 1, 2, 39, 40 SWCK2 CVBS PIP YC PIP 45 YUVPIP RGB PIP 11 20 RSTW2 SAA7118 74F574 8 2 to 9 12 to 19 VIDEO DECODER FSWPIP 8 1 10 24.576 MHz + 3.3 V + 3.3 V 19, 22 20, 21 3 to 6 35 to 38 YCRCB ITU 656 n.c. 8 7 to 14 27 to 34 Philips Semiconductors 19, 22 3 to 6 + 3.3 V Sample rate converter with embedded high quality dynamic noise reduction and expansion port ndbook, full pagewidth 2002 May 28 + 3.3 V SAA4955TJ SWCK2 RSTW2 WE2 15 16 17 18 26 25 24 23 LLC1 RSTR2 RE2 OIE2 1, 2, 39, 40 MHC197 Product specification SAA4979H Fig.20 PIP module. Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979H 8.2 pF handbook, halfpage 2.7 µH 240 Ω Vin Vout 15 pF 68 pF MHC198 Fig.21 Low-pass filter. +8 V handbook, full pagewidth +8 V 5.1 kΩ +8 V 240 Ω 100 Ω BC856 10 µF BC846 Vin 200 Ω 240 Ω 4.7 pF 4.7 µH Vout 2.7 kΩ 200 Ω 39 pF 39 pF 240 Ω MHC199 Fig.22 Low-pass filter with termination. 2002 May 28 46 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979H 14 PACKAGE OUTLINE QFP128: plastic quad flat package; 128 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height SOT320-2 c y X A 96 65 97 64 ZE e E HE A A2 A1 (A 3) θ wM Lp bp L pin 1 index detail X 33 128 1 32 ZD wM bp e v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 4.07 0.50 0.25 3.70 3.15 0.25 0.45 0.30 0.23 0.13 28.1 27.9 28.1 27.9 0.8 HD HE 31.45 31.45 30.95 30.95 L Lp v w y 1.6 1.03 0.73 0.3 0.2 0.1 Z D (1) Z E(1) 1.8 1.4 1.8 1.4 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT320-2 134E13 MS-022 2002 May 28 EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-27 00-01-19 47 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port If wave soldering is used the following conditions must be observed for optimal results: 15 SOLDERING 15.1 Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 15.2 SAA4979H – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages. 15.3 15.4 Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. 2002 May 28 Manual soldering 48 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port 15.5 SAA4979H Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable(3) HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not PLCC(4), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(2) suitable suitable suitable not recommended(4)(5) suitable not recommended(6) suitable Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2002 May 28 49 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979H 16 DATA SHEET STATUS DATA SHEET STATUS(1) PRODUCT STATUS(2) DEFINITIONS Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 17 DEFINITIONS 18 DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2002 May 28 50 Philips Semiconductors Product specification Sample rate converter with embedded high quality dynamic noise reduction and expansion port SAA4979H 19 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2002 May 28 51 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA74 © Koninklijke Philips Electronics N.V. 2002 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/01/pp52 Date of release: 2002 May 28 Document order number: 9397 750 09561