PHILIPS SAA4945H

INTEGRATED CIRCUITS
DATA SHEET
SAA4945H
LIne MEmory noise Reduction IC
(LIMERIC)
Preliminary specification
File under Integrated Circuits, IC02
1997 Jun 10
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
SAA4945H
FEATURES
GENERAL DESCRIPTION
• 2-D adaptive vertically recursive noise reduction
The SAA4945H, LIMERIC (LIne MEmory noise Reduction
IC) is a 2-D recursive noise reduction filter for both
luminance and colour difference signals. The noise
reduction is automatically adapted to the global noise level
in the image. Ten different preferences of noise reduction
can be set using a synchronous receiver transmitter bus;
SNERT (Synchronous No parity Eight bit Receive
Transmit) bus. Alternatively, the noise reduction can be
switched off. The LIMERIC is generally placed directly
after the ADC in the feature box and works fully in the 1fh
(50/60 Hz) domain.
• Noise reduction for Y, U and V signals in 4 : 1 : 1 format
• Single 5 V ±10% power supply
• Communication by means of serial communication
protocol 83C654 (SNERT bus)
• Via SNERT bus, 10 different types of noise reduction
selectable; the noise reduction function can also be
disabled
• Phase relation write enable input/output signal
simultaneously switchable over one clock period w.r.t.
input/output samples
• 8-bit wide data processing for Y, U and V; in unsigned
format (Y signal) and in 2’s complement (U and V
signals)
• One fixed line locked clock operation frequency up to
16 MHz (typical)
• Exactly one line delay.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD
supply voltage (pins 5, 29 and 30)
4.5
5.0
5.5
V
IDD
supply current
−
70
−
mA
−
350
−
mW
10
16
17.1
MHz
P
power dissipation
fCLK
clock frequency
fSNERT
bus clock frequency
−
−
1
MHz
Tamb
operating ambient temperature
0
−
70
°C
±7%; note 1
Note
1. Maximum number of clocks per line is 1024.
ORDERING INFORMATION
TYPE
NUMBER
SAA4945H
1997 Jun 10
PACKAGE
NAME
DESCRIPTION
VERSION
QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 × 10 × 1.75 mm SOT307-2
2
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
SAA4945H
BLOCK DIAGRAM
VDD1
handbook, full pagewidth
VDD2
VDD3
29
30
5
UI0, UI1
VI0, VI1
16, 15
18, 17
REFORMATTER
NOISE
REDUCTION
FILTER
(MULTIPLEXED)
36, 37
∆t
RAM_UV
FORMATTER
34, 35
UO0, UO1
VO0, VO1
N_thr_UV
NOISE
REDUCTION
FILTER
8
N_thr_Y
8
38 to 44, 1
RAM_Y
N_thr_UV
SAA4945H
26
Wval
TASTE
NTHR
NOISE
ESTIMATOR
TEST
CONTROL
internal
control
signals
YpScale
14 to 7
YI0 to YI7
SNERT
INTERFACE
25
24
31
CONTROL
33
2
SDNA
3
19 21 22
4
CLK
Va
WEI
VRST
SNCL
Fig.1 Block diagram.
1997 Jun 10
3
6
20
23
27
28
YO0 to
YO6, YO7
TST0
TST1
TST2
WEO
n.c.
32
GND2
GND4
GND6
GND3
GND5
GND1
MGK170
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
SAA4945H
PINNING
SYMBOL
PIN
TYPE
DESCRIPTION
YO7
1
output
luminance output bit 7
SNDA
2
input/output
data from interface SNERT bus
SNCL
3
input
clock from interface SNERT bus
VRST
4
input
reset in the vertical blanking interval
VDD1
5
supply
supply voltage 1
GND1
6
ground
ground 1
YI7
7
input
luminance input bit 7 from analog-to-digital converter
YI6
8
input
luminance input bit 6 from analog-to-digital converter
YI5
9
input
luminance input bit 5 from analog-to-digital converter
YI4
10
input
luminance input bit 4 from analog-to-digital converter
YI3
11
input
luminance input bit 3 from analog-to-digital converter
YI2
12
input
luminance input bit 2 from analog-to-digital converter
YI1
13
input
luminance input bit 1 from analog-to-digital converter
YI0
14
input
luminance input bit 0 from analog-to-digital converter
UI1
15
input
U input bit 1 from analog-to-digital converter
UI0
16
input
U input bit 0 from analog-to-digital converter
VI1
17
input
V input bit 1 from analog-to-digital converter
VI0
18
input
V input bit 0 from analog-to-digital converter
CLK
19
input
master clock
GND2
20
ground
ground 2
WEI
21
input
write enable input
Va
22
input
vertical blanking pulse
GND3
23
ground
ground 3
TST2
24
input
test pin 2
TST1
25
input
test pin 1
TST0
26
input
test pin 0
GND4
27
ground
ground 4
GND5
28
ground
ground 5
VDD2
29
supply
supply voltage 2
VDD3
30
supply
supply voltage 3
WEO
31
output
write enable output
GND6
32
ground
ground 6
n.c.
33
−
not connected
VO0
34
output
V output bit 0
VO1
35
output
V output bit 1
UO0
36
output
U output bit 0
UO1
37
output
U output bit 1
YO0
38
output
luminance output bit 0
YO1
39
output
luminance output bit 1
YO2
40
output
luminance output bit 2
1997 Jun 10
4
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
TYPE
DESCRIPTION
YO6
44
output
luminance output bit 6
handbook, full pagewidth
36 UO0
luminance output bit 5
37 UO1
luminance output bit 4
output
38 YO0
output
43
39 YO1
42
YO5
40 YO2
YO4
41 YO3
luminance output bit 3
42 YO4
output
43 YO5
41
44 YO6
YO3
34 VO0
PIN
35 VO1
SYMBOL
SAA4945H
33 n.c.
YO7 1
SNDA 2
32 GND6
SNCL 3
31 WEO
VRST 4
30 VDD3
VDD1 5
29 VDD2
GND1 6
28 GND5
SAA4945H
Fig.2 Pin configuration.
1997 Jun 10
5
Va 22
WEI 21
GND2 20
CLK 19
23 GND3
VI0 18
24 TST2
VI1 17
YI4 10
YI3 11
UI0 16
25 TST1
YI0 14
26 TST0
YI5 9
UI1 15
YI6 8
YI2 12
27 GND4
YI1 13
YI7 7
MGK169
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
SAA4945H
FUNCTIONAL DESCRIPTION
LUMINANCE FILTER
The digital LIMERIC is an effective low noise reduction IC
for luminance and colour difference signals. Noise filtering
is automatically adapted to the global noise level which is
measured within the picture content. The two dimensional
non-linear noise reduction (one for luminance, one for
chrominance) uses only line memory to function.
Furthermore, up to 10 different preferences can be set by
the user.
The taps structure of the luminance filter is as shown in
Table 2.
Table 2
As shown in Fig.1, the main components of the device are
the noise reduction filter with the line memories (RAM) and
the noise estimator. Other components shown are the
reformatter, formatter, controller and a SNERT bus
transceiver.
Luminance processing
X....X...X...X....X
← 5 Y samples from the
filtered line (distance 4 / 5
pixel)
o.O.o
← 3 Y samples from the
incoming line (distance 2
pixels)
A ‘weave’ function is used to reduce any smearing effect
that could occur at edges. As shown in Tables 3 to 6, the
‘weave’ calculates over 4 consecutive lines. The relative
position of the actual pixel changes one position every line.
Noise reduction filter
Both luminance and chrominance signals are filtered with
vertical recursion. This is produced as the filter receives
both filtered samples from the previous line, and unfiltered
samples from the current line. A new replacement value is
calculated for each sample read from the line memory.
This in turn, is the filtered response value for the reference
input pixel. The reference pixel is then placed at the centre
of the delay-line into which the current (unfiltered) video
line is shifted. Tables 1 to 6 show this as an ‘O’.
Table 3
For line 2n
X....X...X...X....X
o.O.o
Table 4
For line 2n + 1
X....X...X...X....X
..o.O.o
Both luminance and colour difference signals are filtered
using the so-called Discriminating Averaging Filter (DAF),
in which filter coefficients are related to the Absolute
Difference (AD) between samples. The filter uses samples
from both present and previous line (using the line delay)
and the result of the filter is stored back in the line memory.
In this way a vertical recursive structure is realized.
Table 5
For line 2n + 2
X....X...X...X....X
o.O.o
Table 6
The filter coefficients are set depending on the noise
measured by the noise estimator or the NTHR (SNERT
register F9).
For line 2n + 3
X....X...X...X....X
o.O.o..
Table 7 Weave configuration
Depending on even and odd fields the ‘weave’ has the
following configuration:
CHROMINANCE FILTER
The basic signal processing for either U or V is via the
same filter. It is used to process both V and U using a
multiplexed operation.
ODD FIELDS
EVEN FIELDS
X
The taps structure of the chrominance filter is as shown in
Table 1.
X
X
X
X
Table 1
Chrominance processing
X
X
XXXXX
← 5 adjacent R − Y samples from the
filtered line
X
oOo
← 3 adjacent R − Y samples from the
incoming line
X
1997 Jun 10
X
X
6
X
X
X
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
SAA4945H
Noise estimator
The threshold value N_thr for the filters is calculated in the noise estimator block (see Fig.3). There are four options for
producing the N_thr value:
1. Pre-filter gain setting (YpScale)
2. Wval selects the sensitivity of the noise estimator
3. TASTE (TS) scales the N_thr linear
4. NTHR is externally applied when the noise estimator is disabled by the control bit ExThr of the Status Register.
handbook, full pagewidth
YI
PRE-FILTER
NOISE ESTIMATOR
×
MUX
N_thr
ExThr
MGK171
4
NTHR
Wval
YpScale
TS0-TS3
Fig.3 Noise estimator.
SIGNAL DESCRIPTION
VI1 AND VI0 (PINS 17 AND 18)
Input signals
• Colour difference signal V
YI7 TO YI0 (PINS 7 TO 14)
• Data in 2’s complement; dynamic range between
−128 and +127
• Eight bit wide digital luminance input bus
• Unsigned data; dynamic range between 0 and 255
• Y : U : V format 4 : 1 : 1; see Table 8 for input data
coding
• The maximum number of input samples equals
852 active samples/line.
• The maximum number of input samples equals
213 samples/line
• Internal data processing of V signals in unsigned format.
UI1 AND UI0 (PINS 15 AND 16)
• Colour difference signal U
• Data in 2’s complement; dynamic range between
−128 and +127
• Y : U : V format 4 : 1 : 1; see Table 8 for input data
coding
• The maximum number of input samples equals
213 samples/line
• Internal data processing of U signals in unsigned format.
1997 Jun 10
7
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
Table 8
SAA4945H
Input /output data coding
INPUT
Y
U
V
BIT
INPUT DATA SEQUENCE
Y7
Y07
Y17
Y27
Y37
Y6
Y06
Y16
Y26
Y36
Y5
Y05
Y15
Y25
Y35
Y4
Y04
Y14
Y24
Y34
Y3
Y03
Y13
Y23
Y33
Y2
Y02
Y12
Y22
Y32
Y1
Y01
Y11
Y21
Y31
Y0
Y00
Y10
Y20
Y30
UI1
U07
U05
U 03
U01
UI0
U06
U04
U 02
U00
VI1
V07
V05
V03
V01
VI0
V06
V04
V02
V00
• The number of input samples is a multiple of 4 (see
Fig.4)
WEI (PIN 21)
• Write enable input
• Start of new line indicated by write enable signal LOW
for at least 4 consecutive clock periods (see Fig.4)
• Write enable indicates the time when active input
samples (Y, U and V) are present
• During active line, WEI is not allowed to be LOW for
more than 1 clock cycle.
• Timing relation (see Fig.4) depending on the logic level
of the Write Enable Select signal (WES) in status
register; to adapt to different external video memories
1997 Jun 10
8
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
SAA4945H
handbook, full
pagewidth
CLK
WEI
line n
(WES = 0 status register)
WEI
(WES = 1 status register)
YI0 to YI7
X
Y0
Y1
X
Y2
X
Y3
UI0, UI1
X
U0. 7,6
U0. 5,4
X
U0. 3,2
X
U0. 1,0
VI0, VI1
X
V0. 7,6
V0. 5,4
X
V0. 3,2
X
V0. 1,0
one sequence; X: non valid data
CLK
WEO
line n + 1
(WES = 0 status register)
WEO
(WES = 1 status register)
YI0 to YI7
X
Y0
Y1
X
Y2
X
Y3
UI0, UI1
X
U0. 7,6
U0. 5,4
X
U0. 3,2
X
U0. 1,0
VI0, VI1
X
V0. 7,6
V0. 5,4
X
V0. 3,2
X
V0. 1,0
one sequence; X: non valid data
MGK172
Fig.4 Write enable timing.
Va (PIN 22)
CLK (PIN 19)
• Vertical synchronization signal, active HIGH
• Line locked system clock, up to 16 MHz typical
• Minimum HIGH period equals one line period
• All clock related signals act on the rising edge of the
system clock.
• Vertical synchronization signals converted to system
clock domain internally. So the Va pulse can be
asynchronous.
TST0, TST1 AND TST2 (PINS 26, 25 AND 24)
• Test mode inputs
• See timing diagram Fig.6 and Table 11 for timing
specification.
1997 Jun 10
• Active HIGH, with internal pull-down resistors.
9
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
Table 9
SAA4945H
Test settings
TST2
0
TST1
TST0
MODE
0
0
application mode
X(1)
1
X(1)
test mode
1
X(1)
X(1)
test mode
X(1)
X(1)
1
test mode
Note
1. X = don’t care.
SNDA, SNCL AND VRST (PINS 2, 3 AND 4)
• Serial interface signals
• SNERT bus protocol (Synchronous No parity 8-bit receiver and Transmission bus)
• SNDA is a bidirectional signal with 8-bit wide data and address (LSB first)
• Serial interface signals converted (internally) to system clock domain. To avoid set-up violations these signals are
clocked two times by the system clock before further processing is performed.
• Synchronization of serial address (every even byte) and data (every odd byte) by VRST.
Tcy(SNCL)
handbook, full pagewidth
SNCL
tsu(i)(D)
SNDA
(receiver
mode)
th(D)
LSB
th(Q)
SNDA
(transmitter
mode)
data
valid
data
valid
data
valid
data
valid
data
valid
data
valid
data
valid
MGK173
td(D)
Fig.5 Timing diagram of serial interface.
Table 10 Timing characteristics (see Fig.5)
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
tcy(SNCL)
SNCL cycle time
1
−
µs
tsu(i)(D)
input set-up time
90
−
ns
th(D)
input hold time
50
−
ns
th(Q)
output data hold time
0
−
ns
td(D)
output data delay time
−
700
ns
1997 Jun 10
10
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
SAA4945H
Output signals
WEO (PIN 31)
YO0 TO YO7 (PINS 38 TO 44 AND 1)
• Write enable output
• 8-bit wide digital luminance output bus
• Write enable indicates the time when active samples (Y,
U and V) are present
• Data format: unsigned, dynamic range between
0 and 255.
• Timing relation (see Fig.6) depending on write enable
select signal (WES) in status register; to adapt to
different external video memories
UO1 AND UO0 (PINS 37 AND 36)
• The number of output samples is a multiple of 4
• Colour difference signal U
• The write enable output sequence is a copy of the write
enable input sequence of the previous line (see Fig.6)
with a shift of one line
• Data format: 2’s complement, dynamic range between
−128 and +127
• Y : U : V format 4 : 1 : 1; see Table 8.
• The last line in field is not processed.
VO1 AND VO0 (PINS 35 AND 34)
• Colour difference signal V
• Data format: 2’s complement, dynamic range between
−128 and +127
• Y : U : V format 4 : 1 : 1; see Table 8.
t(Va-WE)LH
tVa(min)H
handbook, full pagewidth
Va
t(Va-VRST)LH
tsu(Va)
VRST
t(WE-VRST)LH
WEI
L(n−1)
L(n)
WEO
L(n−2)
L(n−1)
L(0)
L(1)
L(2)
L(0)
L(1)
1 clk cycle
internal flag
to mask
WEO
MGK174
Fig.6 Timing diagram for WEO blanking and Va.
1997 Jun 10
11
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
SAA4945H
Table 11 Va versus VRST
SYMBOL
PARAMETER
MIN.
UNIT
tVa(min)H
minimum Va HIGH time
64
µs
tsu(Va)
set-up Va to negative edge of WEI
0
µs
t(Va-WE)LH
Va LOW to WEI HIGH time
0
µs
t(Va-VRST)LH
Va LOW to VRST HIGH time
0
µs
t(WE-VRST)LH
WEI LOW to VRST HIGH time
64
µs
LIST OF SNERT BUS ADDRESSES USED IN LIMERIC
TASTE register
Table 12 TASTE register usage
USE
ACTION
Purpose
to set 4 different types of noise reduction
Address
F3
Read/write
write
Range
0 to 4; 0 = noise filtering disabled
Table 13 TASTE register content
MSB
0
LSB
0
0
0
ts3
ts2
ts1
ts0
REMARK
see Table 14
Table 14 TASTE setting
TS3
TS2
TS1
TS0
0
0
0
0
noise filtering disabled
0
0
0
1
not applicable
0
0
1
0
noise reduction; TASTE 1
0
0
1
1
not applicable
0
1
0
0
noise reduction; TASTE 2
0
1
0
1
not applicable
0
1
1
0
noise reduction; TASTE 3
0
1
1
1
not applicable
1
0
0
0
noise reduction; TASTE 4
1
0
0
1
not applicable
1
0
1
0
not applicable
1
0
1
1
not defined
1
1
0
0
not defined
1
1
0
1
not defined
1
1
1
0
not defined
1
1
1
1
not defined
1997 Jun 10
FUNCTION
12
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
SAA4945H
Status register
Table 15 Status register usage
USE
ACTION
Purpose
internal settings
Address
F4
Read/write
write
Table 16 Status register content
MSB
Tctrl3
LSB
Tctrl2
Tctrl1
X
ExThr
Wv
DEM
WES
Table 17 Status register description
BIT
0
NAME
WES
DESCRIPTION
Write Enable Select
0: data coincides with write enable (both input and output)
1: data is delayed over one clock period with respect to the write enable (both input and output)
see Fig.4
1
DEM
Demo Mode
0: demo mode disabled
1: demo mode on; the noise reduction circuit is switched on for the left half of the screen - the noise
reduction is disabled (split screen function) for the right half of the screen
2
Wv
Weave
0: enable weave
1: disable weave
3
ExThr
External Threshold control bit
0: N_thr calculated by noise estimator
1: value of N_thr from register F9 is used
4
X
don’t care
5
Tctrl1
Test control 1
0: normal operation
1: test mode
6
Tctrl2
Test control 2
0: normal operation
1: test mode
5
Tctrl3
Test control 3
0: normal operation
1: test mode
1997 Jun 10
13
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
SAA4945H
Wval register (wanted value)
Table 18 Wval register usage
USE
ACTION
Purpose
register for setting up noise estimator
Address
F5
Read/write
write
Range
0 to 255
Table 19 Wval register
MSB
LSB
Wval6
Wval7
Wval5
Wval4
Wval3
Wval2
Wval1
Wval0
CONDITIONS
Tctrl2 = 0
Noise threshold register
Table 20 Noise threshold register usage
USE
ACTION
Purpose
register for setting the NTHR value for the noise filter externally
Address
F9
Read/write
write
Range
0 to 255
Table 21 Noise threshold register content
MSB
NTHR[7]
LSB
NTHR[6]
NTHR[5]
NTHR[4]
NTHR[3]
NTHR[2]
NTHR[1]
NTHR[0]
Noise estimator setting register
Table 22 Noise estimator setting register usage
USE
ACTION
Purpose
register for general setting of the noise estimator
Address
FA
Read/write
write
Table 23 Noise estimator setting register
MSB
YpScale1
LSB
YpScale0
0
0
0
0
Table 24 Noise estimator setting description
YpScale1
YpScale0
0
0
noise estimator pre-filter gain setting = 1
0
1
noise estimator pre-filter gain setting = 0.5
1
0
noise estimator pre-filter gain setting = 0.25
1
1
noise estimator pre-filter bypassed
1997 Jun 10
DESCRIPTION
14
0
0
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
SAA4945H
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD1
supply voltage 1
−0.5
+6.5
V
VDD2
supply voltage 2
−0.5
+6.5
V
VI
input voltage
−0.5
+6.5
V
Tstg
storage temperature
−55
+150
°C
Tamb
operating ambient temperature
−40
+85
°C
Ptot
total power dissipation
−
150
mW
PO(pin)
output power dissipation per output pin
−
100
mW
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
1997 Jun 10
PARAMETER
CONDITIONS
thermal resistance from junction to ambient
15
in free air
VALUE
UNIT
65
K/W
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
SAA4945H
CHARACTERISTICS
VDD = 5 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage (pins 5, 29 and 30)
4.5
5.0
5.5
V
IDD
supply current
−
70
−
mA
Tamb
operating ambient temperature
0
−
70
°C
Tstg
storage temperature
−50
−
+150
°C
P
power dissipation
−
350
−
mW
CLK
±7%; note 1
fCLK
clock frequency
10
16
17.1
MHz
δ
duty cycle
40
−
60
%
VIL
LOW-level input voltage
−
−
0.8
V
VIH
HIGH-level input voltage
2
−
−
V
CL
load capacitance
10
−
−
pF
−
−
0.8
V
YI7 to YI0, UI1, UI2, VI1, VI0, WEI and Va
VIL
LOW-level input voltage
2.0
−
−
V
−
−
±20
µA
set-up time
6
−
−
ns
hold time
7
−
−
ns
VIH
HIGH-level input voltage
II
input current
tsu(i)(D)
th(D)
VI = 0 to 5 V
YO7 to YO0, UO1, UO2, VO1, VO0 and WEO
VOL
LOW-level output voltage
IOL = 1.6 mA
−
−
0.4
V
VOH
HIGH-level output voltage
IOH = 0.4 mA
2.4
−
−
V
th(Q)
output hold
CL = 15 pF
7
−
−
ns
td(D)
output delay
CL = 15 pF
−
−
32
ns
SNDA and SNCL
fSNERT
bus clock frequency
−
−
1
MHz
VIL
LOW-level input voltage
−
−
0.8
V
VIH
HIGH-level input voltage
2.0
−
−
V
VOL
LOW-level output voltage
−
−
0.4
V
VOH
HIGH-level output voltage
2.4
−
−
V
TST0, TST1 and TST2
VIL
LOW-level input voltage
−
−
0.8
V
VIH
HIGH-level input voltage
2.0
−
−
V
Note
1. Maximum number of clocks per line is 1024.
1997 Jun 10
16
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
SAA4945H
PACKAGE OUTLINE
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
c
y
X
A
33
23
34
22
ZE
e
Q
E HE
A A2
wM
(A 3)
A1
θ
bp
Lp
pin 1 index
L
12
44
1
detail X
11
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
Q
v
w
y
mm
2.10
0.25
0.05
1.85
1.65
0.25
0.40
0.20
0.25
0.14
10.1
9.9
10.1
9.9
0.8
12.9
12.3
12.9
12.3
1.3
0.95
0.55
0.85
0.75
0.15
0.15
0.1
Z D (1) Z E (1)
1.2
0.8
1.2
0.8
θ
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-02-04
SOT307-2
1997 Jun 10
EUROPEAN
PROJECTION
17
o
10
0o
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
SAA4945H
SOLDERING
Wave soldering
Introduction
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
Reflow soldering
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
Reflow soldering techniques are suitable for all QFP
packages.
The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9398 510 63011).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
1997 Jun 10
18
Philips Semiconductors
Preliminary specification
LIne MEmory noise Reduction IC
(LIMERIC)
SAA4945H
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Jun 10
19
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1997
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/20/01/pp20
Date of release: 1997 Jun 10
Document order number:
9397 750 01608