INFINEON SDA9290-6

Picture Processor
SDA 9290-6
Preliminary Data
CMOS IC
Features
• Noise and cross color reduction by field - or frame
recursive filtering
• Adjustment of degree of noise reduction
• Automatic adaption to signal quality during vertical
blanking
• Pixel adaptive movement detection
• Split screen modes for demonstration purposes
• Multi-picture facilities
• Picture decimation using vertical filtering
• 8 programmable grey levels for framing
• 4:1:1 and 4:2:2 (Y:U:V) compatibility
• 8-bit word size for all components
• IIC-Bus programming of the video line for S/N
measurement in automatic adaption mode
• Optimized characteristics of the recursive filters
P-LCC-68-1
Type
Ordering Code
Package
SDA 9290-6
Q67101-H5193
P-LCC-68-1 (SMD)
Functional Description
The CMOS device SDA 9290-6 is a picture processor and belongs to a family of devices
forming an extended third-generation digital TV signal-processing system for enhanced
picture quality with special functions (Featurebox). Besides the Picture Processor (PP)
that is described here, the system consists of a field memory (at least three triple-port,
1-Mbit generation TV Sequential-Access Memory devices (SDA 9251 X), a Memory
Sync Controller (MSC SDA 9220-5) and a Display Prozessor (SDA 9280). A block
diagram of the Featurebox is shown in figure 4.
The Picture Processor SDA 9290-6 is a follow-on development of the Picture Processor
SDA 9290-5. Modifications of the movement detector and the recursive filters permits
further picture improvement by reducing the video noise and cross-color interference.
The SDA 9290-6 can be set independently at the picture-signal input and output via the
two pins FSBQ/FSI to the 4:1:1 and 4:2:2 formats. A 4:1:1 Featurebox (3 TV-SAMs) can
therefore be operated with 4:2:2 input signals as well.
Semiconductor Group
1
1997-07-22
SDA 9290-6
The necessary decimation and interpolation operations are activated automatically
when the format is set. Together with a corresponding Memory Sync Controller
(SDA 9220) it enables functions like multi-picture, tuner scanning, picture-in-still and
still-in-picture. The different modes can be activated by a microcontroller on the I2C-Bus
interface (slave receiver). The I2C-Bus address for accessing the device is
0
0
1
0
1
0
1
0
Circuit Description
The core of the picture processor (see block diagram) is formed of the Image-lmproving
Processor (IIP) and the Multi-Picture Processor (MPP). The IIP is responsible for noise
and cross-color reduction, while the MPP together with the new Memory Sync Controller
implements the functions multi-picture, tuner scanning, picture-in-still and still-in-picture.
Image-lmproving Processor
The signal inputs Yl0-YI7 and UVI0-UVI7 and the back-channel signal inputs YB0-YB7
and UVB0-UVB7 picture data with 12 bits in quasi-parallel format (4:1:1) and with 16 bits
in parallel format (4:2:2). The clock rate for both signals is 13.5 MHz. For signal
processing in the IIP and MPP the chrominance bit levels have to be separated in the
case of the quasi parallel format by demultiplexers DEMUXS and DEMUXR, these being
largely identical in design.
A reduction in video noise is achieved by correlating the picture contents of two
successive fields, the non-correlated components (noise) being attenuated by the digital
filter. To achieve this, the instantaneous digital picture signal on the outputs of the
demultiplexer DEMUXS and the picture signal delayed by a field interval on the outputs
of the back-channel demultiplexer DEMUXR are fed to the IIP and combined.
The signal-to-noise ratio (S/N) unit detects the noise components of the input signals and
the movement detector uses this information to select an appropriate set of parameters
with filter coefficients and thresholds for the comparators. For this purpose the
luminance signal is assigned to one of three classes according to its S/N ratio, with each
class defining a different degree of maximum noise reduction. The limits between the
middle class and the upper and lower classes can be programmed by the I2C-Bus
registers R1 and R2 with the values for the thresholds SU and SL. When the picture
signals come from a video cassette recorder, the adaptation on the S/N ratio of the input
signal should be disabled by I2L-Bus register R0, VCR bit D2.
Measurement of the signal-to-noise ratio in the automatic mode has been advanced
from line 6 to line 4 in order to avoid conflicts with future text and data services.
The degree of noise reduction for the luminance and chrominance signals can be varied
between 0 dB and 12 dB by selecting the appropriate filter coefficients.
Semiconductor Group
2
1997-07-22
SDA 9290-6
A picture signal with reduced noise and cross-color appears on the output of the IIP for
further processing. The signal will be forwarded via blocks MUXI and MUXO to the
picture memories through the outputs (YQ0-YQ7 and UVQO-UVQ7 respectively).
The coefficients of the selected class are controlled by the movement detector as a
function of pixels to prevent artifacts (loss of focus) in moving parts of the picture. The
video line for S/N measurement can be programmed by the I2C-Bus register R2 (D7-D5).
Multi-Picture Processor
Signals are processed in the 4:1:1 format. The vertical-decimation line memory again
operates with 208 pixels per line to adapt the 1/9th picture format to the new picture
memory with TV-SAMs. Gray frame generation is similarly affected by this change in
pixel value.
The signal processing in the decimation filter of the MPP reduces the picture to
approximately 1/9th of its original size. This produces a basis for new features, the full
implementation of which calls for a matching MSC (SDA 9220).
Figure 8 shows how the screen is divided up. The following modes can be implemented
with the MPP:
1. Multi-Picture (automatic)
Fields are extracted from a sequence of movements at fixed intervals, reduced and
reproduced on the screen as a sequence of stills. At one position it is possible to show
a moving picture.
2. Multi-Picture (manual)
This differs from the above in that the viewer can determine at the push of a button
what phases of movement are to be stored.
3. Multi-Picture (tuner scanning)
The pictures of the sequence of stills are derived from the different TV channels and
give an overview of the programs on offer. In this mode the picture memory is
operated with a crystal-controlled clock to ensure that the picture remains stable when
switching from one channel to another.
4. Still-in-Picture
A field is extracted from the on-going program, reduced and inserted as a still in the
master channel.
5. Picture-in-Still
The on-going program is inserted as a reduced-size moving picture in a still.
The framing block that follows the decimation filter in the MPP permits frames to be
inserted in order to border the reduced-size pictures on the screen. The brightness of the
framing can be varied in eight steps by the I2C Bus.
The format conversion produced in the demultiplexers for signal processing in the IIP
and MPP is reversed again in the multiplexer MUXO. The picture signal appears again
in quasi-parallel format or parallel format on the output of the MUXO block. The inputs
of the TV-SAMs are directly driven by the sixteen outputs YQ0-YQ7 and UVQ0-UVQ7.
Semiconductor Group
3
1997-07-22
SDA 9290-6
1. Field
624
625
1
2
4
5
6
7
317
318
319
320
3
8
CVBS
BLN
VS
SDA 9290-6
000
LINE
001
010
011
100
101
110
111
(4) (Default)
(0)
(1)
(2)
(3)
(5)
(6)
(7)
SDA 9290-5
2. Field
312
313
314
315
316
BLN
VS
SDA 9290-6
000
LINE
001
010
011
100
101
110
111
(4) (Default)
(0)
(1)
(2)
(3)
(5)
(6)
(7)
SDA 9290-5
UED09849
Figure 1
Programmable Video Lines
Semiconductor Group
4
1997-07-22
SDA 9290-6
I2C Bus Interface
An I2C Bus interface configured as a “slave receiver” is used for programming the different functions
and modes of the picture processor. Via this interface up to four registers can be written according
to the following transfer protocol for controlling the operation mode:
S
Slave Address
0 A
Sub Address
Data Byte
A
A
A P
S: Start condition
A: Acknowledge
P: Stop condition
Slave address: 0 0 1 0 1 0 1
(Note: There is a general description of the I2C Bus in the Siemens publication “I2C Bus Technical
Description”.)
After every data byte that is transmitted the internal register address (subaddress) is automatically
incremented to the next register so that, if necessary, several registers can be loaded with one I2C
Bus telegram.
In the multi-picture mode the operating mode transmitted on the I2C Bus is switched within the
vertical blanking interval, i.e. during the high phase of signal VS1, if the Memory Sync Controller
(MSC) activates the DREQ line during this period.
It should be noted that the new operating mode has always to be transmitted to the picture
processor first and immediately afterwards to the MSC on the I2C Bus at an interval not longer than
30 ms.
This is the only way to ensure interference-free synchronization of the picture processor and the
MSC. The four I2C Bus registers are described below in more detail. The values marked “*D” in the
right-hand margin are set by an internally generated reset signal (default values) when the
operating voltage is applied.
Register Subaddress1) D7
D6
D5
D4
D3
D2
D1
D0
R0
00
B1
B0
FR
0
SS
VCR
NR
SUV8
R1
01
YF5
YF4
YF3
SL4
SL3
SL2
SL1
SL0
R2
02
LINE2
LINE1
LINE0
SU4
SU3
SU2
SU1
SU0
R3
03
SNTEN SNT1
SNT0
KTEN
KT3
KT2
KT1
KT0
Semiconductor Group
Data Byte
5
1997-07-22
SDA 9290-6
Register
R0:
This control register sets the operating mode of the picture processor.
Bits D7, D6: Mode
Bit D5:
Bit D4:
Bit D3:
B1
B0
Normal
0
0
Multi-picture (MP)
0
1
Still-in-picture (SIP)
1
0
Picture-in still (PIS)
1
1
MPP: Narrow Frame
FR
Without narrow frame
0
With narrow frame
1
*D
*D
No function; default 0
Display Mode
SS
Full screen
0
Split screen
1
Semiconductor Group
6
*D
1997-07-22
SDA 9290-6
Specialities
Split Screen Display
For demonstration purposes the noise reduction can be disabled for half of the picture
by means of I2C-Bus register R0, bit D3. In this way a direct comparison is possible
between a noise-reduced (filtered) and an unfiltered picture.
Bit D2:
Bit D1:
Bit D0:
Control of SNR adaptation
VCR
TV mode
0
VCR mode
1
Noise reduction ON/OFF
NR
Noise reduction OFF
0
Noise reduction ON
1
Word width input
*D
SUV8
7 bits
0
8 bits
1
Semiconductor Group
*D
7
*D
1997-07-22
SDA 9290-6
Register
R1:
This control register sets the frame luminance for multi-picture and the
threshold SL for S/N adaptation.
Bits D7-D5: Frame Luminance
YF
YF5
YF4
YF3
0
black
0
0
0
:
:
:
7
:
:
:
white
:
:
:
1
:
:
:
1
:
:
:
1
Bits D4-D0: Threshold SL
(S/N adaptation)
*D
SL4
SL3
SL2
SL1
SL0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
4
0
0
1
0
0
:
:
:
:
:
:
:
:
:
:
:
:
31
1
1
1
Semiconductor Group
8
*D
1
1997-07-22
SDA 9290-6
Register
R2:
This control register sets the threshold SU for S/N adaptation, and the
values for the line counter.
Noise Measurement: Decoded Values of the Line Counter
Bits D7-D5: LINE2
LINE1
LINE0
Decoded
Value
0
0
0
4
0
0
1
0
0
1
0
1
0
1
1
2
1
0
0
3
1
0
1
5
1
1
0
7
Bits D4-D0: Threshold SU
(S/N adaptation)
*D
SU4
SU3
SU2
SU1
SU0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
16
1
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
31
1
1
1
1
1
Semiconductor Group
9
*D
1997-07-22
SDA 9290-6
Register
R3:
This register is for testing. certain S/N classes and filter coefficients for the
motion detector can be firmly set.
Bits D7-D5: S/N Class
SNTEN
SNT1
SNT0
Automatic adaptation
0
X
X
Class 0
1
0
0
Class 1
1
0
1
Class 2
1
1
0
Bits D4-D0: Filter Coefficient
*D
KTEN
KT3
KT2
KT1
KT0
Motion detector ON
0
X
X
X
X
K=1
1
0
0
0
0
K = 3/4
1
0
0
0
1
K = 5/8
1
0
0
1
0
K = 9/16
1
0
0
1
1
K = 3/4
1
0
1
0
0
K = 1/2
1
0
1
0
1
K = 3/8
1
0
1
1
0
K = 5/16
1
0
1
1
1
K = 5/8
1
1
0
0
0
K = 3/8
1
1
0
0
1
K = 1/4
1
1
0
1
0
K = 3/16
1
1
0
1
1
K = 9/16
1
1
1
0
0
K = 5/16
1
1
1
0
1
K = 3/16
1
1
1
1
0
K = 1/8
1
1
1
1
1
*D
Note: X is ignored.
*D = Default values after reset.
Semiconductor Group
10
1997-07-22
Figure 2
Block Diagram
Semiconductor Group
V DD
GND
MPP
YI
UVI
8
8
DREQ
LL3X
Clock
Generation
11
BLN
VS1
LLIN
LLSEL
FSI
FSBQ
SDA
SCL
YB
UVB
DEMUXS
16
12 Decimation- 12
4:1:1
Filters
Decimation
Line Memory
IIP
YS
8
"S / N"
Measure
ment
12
16
8
YS
8
YR
YI, MUXI MUXO
8
UIVI
"1"
16
8
"0"
ROM
SN
S1,S2
10
Ι C Bus
Receiver
DEMUXR
YIM,
UIMVIM
16
2
8
16
Framing
YS,
USVS
ControlSignals
8
12
4:2:2
Interpolator
K0,K1
10
KY
5
Movement
5
Detector
KUV
16
Recursive
Filters
YO
UVO
SI
16
YII,
UIIVII
16
YR ,
URVR
1997-07-22
SDA 9290-6
UEB09850
UVQ0
UVQ1
UVQ2
UVQ3
UVQ4
UVQ5
UVQ6
UVQ7
V DD
YQ0
YQ1
YQ2
YQ3
YQ4
YQ5
YQ6
YQ7
SDA 9290-6
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
GND
UVB0
UVB1
UVB2
UVB3
UVB4
UVB5
UVB6
UVB7
YB0
YB1
YB2
YB3
YB4
YB5
YB6
YB7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
SDA 9290-6
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
GND
N.C.
N.C.
N.C.
SPEN
CLKEN
FSI
FSBQ
V DD
VS1
SDA
SCL
LL3X
LLSEL
LLIN
BLN
GND
UVI0
UVI1
UVI2
UVI3
UVI4
UVI5
UVI6
UVI7
YI0
YI1
YI2
YI3
YI4
YI5
YI6
YI7
DREQ
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
UEP09851
Figure 3
Pin Configuration (top view)
Semiconductor Group
12
1997-07-22
SDA 9290-6
Pin Definitions and Functions
Pin No. Symbol
Function
Description
Positive supply
voltage (+ 5 V)
Positive supply voltage (+ 5 V)
1
VDD
2-9
UVQ7 … Data outputs
UVQ0
Push-pull outputs for directly driving the TV-SAM
chrominance inputs:
8 bits for 4:2:2 format;
4 bits for 4:1:1 format;
[UVQ0 … UVQ3 only valid for 4:2:2 format]
10
GND
Ground
Ground (0 V)
11-18
UVB0 …
UVB7
Back-channel
data outputs
Back-channel inputs for chrominance data from TV-SAM
19-26
YB0 …
YB7
Back- channel
data inputs
Back-channel inputs for luminance data from TV-SAM
27-34
UVI0 …
UVI7
Data inputs
Data inputs for chrominance data accept the dig. YUV
signal
35-42
YI0 …
YI7
Data inputs
Data inputs for luminance data accept the dig. YUV
signal
43
DREQ
Data request
signal for multipicture mode
Data-request input; initiates data transfer in multi-picture
mode and switches mode together with signal VS1
44
GND
Ground
Ground (0 V)
45
BLN
Blanking signal
(15.625 kHz)
Input for line-synchronous blanking signal that
determines line blanking interval (active low) and
synchronizes clock and sequence control
46
LLIN
First system clock
(13.5 MHz)
Input for line-locked system clock, 13.5 MHz, from which
internal timing is derived. Positive edge indicates validity
of input data
47
LLSEL
none
Must be connected to VDD (high-level)
48
LL3X
Second system
clock (13.5 MHz)
Input for line-locked 13.5-MHz clock that ensured picture
stability in multi-picture mode and is used as output clock
in every mode
49
SCL
I2C Bus shift clock I2C-Bus shift-clock input
input
50
SDA
I2C Bus data
input/output
51
VS1
Vertical sync input Vertical sync input; determines vertical position of TV
(50 Hz)
picture for 50-Hz or 60-Hz field frequency
52
VDD
Positive supply
voltage (+ 5 V)
Semiconductor Group
I2C-Bus data input/output
Positive supply voltage (+ 5 V)
13
1997-07-22
SDA 9290-6
Pin Definitions and Functions (cont’d)
Pin No. Symbol
Function
53
FSBQ
Selection of output Switching of data output format:
format
Low level for 4:1:1 format; high level for 4:2:2 format
54
FSI
Selection of input
format
55
CLKEN
Connect test pin 2 Has to be grounded (0 V) in normal mode
56
SPEN
Connect test pin 2 Has to be grounded (0 V) in normal mode
57-59
N.C.
Reserved
No connections possible or meaningful
60
GND
Ground
Ground (0 V)
61-68
YQ7 …
YQ0
Data outputs
Push-pull outputs for directly driving TV-SAM inputs for
4:1:1 and 4:2:2 modes; (8-bit luminance)
Semiconductor Group
Description
Switching of data input format: Low level for 4:1:1 format;
high level for 4:2:2 format
14
1997-07-22
SDA 9290-6
Electrical Characteristics
Absolute Maximum Ratings
(all voltages are referred to GND)
Parameter
Ambient temperature
Storage temperature
Total power dissipation
Supply voltage
Input/output voltage
Thermal resistance system-air
Symbol
Limit Values
Unit
min.
max.
TA
Tstg
Ptot
VDD
VI/Q
Rth SA
0
70
°C
– 40
125
°C
1
W
– 0.3
6
V
– 0.3
6
V
38
K/W
VDD
IDD
TA
4.5
5.5
V
180
mA
70
°C
Remarks
with heat
sink
Operating Range
Supply voltage
Supply current
Ambient temperature
0
Note: Stresses above those listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Maximum ratings are absolute ratings; exceeding only one of these values may
cause irreversible damage to the integrated circuit.
Note: In the operating range the functions given in the circuit description are fulfilled.
Semiconductor Group
15
1997-07-22
SDA 9290-6
Characteristics
(all voltages are referred to GND)
Parameter
Symbol
Limit Values
min.
H-input voltage 1)
L-input voltage 1)
Input current 1)
Input capacitance 1)
(except BLN, LLIN)
VIH
VIL
IIR
CI
Input capacitance 1)
(only BLN, LLIN)
CI
H-input voltage 2)
VIH
VIL
CI
IIM
VQH
VQL
VQL
VQM
L-input voltage 2)
Input capacitance 2)
Input current 2)
H-output voltage 3)
L-output voltage 3)
L-output voltage 4)
Permissible output voltage 4)
typ.
Unit
Test Condition
max.
2.0
5.5
V
0
0.8
V
10
µA
10
pF
5
pF
3.0
5.5
V
0
0.8
V
10
pF
10
µA
2.4
V
0.4
V
0.4
V
5.5
V
IQH = – 2.0 mA
IQH = 3.0 mA
IQH = 3.0 mA
1)
Input signals UVI0 … UVI7, YI0 … YI7, UVB0 … UVB7, YB0 … YB7, BLN, LLSEL, FSI, FSBQ, LLIN, LL3X,
DREQ, VS1
2)
Input signals SDA, SCL (refer to figure 6)
3)
Output signals YQ0-YQ7, UVQ0-UVQ7
4)
Output signal SDA (open drain)
Semiconductor Group
16
1997-07-22
SDA 9290-6
Characteristics (cont’d)
(all voltages are referred to GND)
Parameter
Symbol
Limit Values
min.
typ.
Unit
Test Condition
max.
Input Clock LL3X = 13.5 MHz (refer to figure 6)
Cycle
TLLL3X
Fall time
tTHL
tTHL
tWH
tWL
tSK
Rise time
H-pulse width
L-pulse width
Change in rel to LLIN
68
74
80
ns
5
ns
5
ns
25
ns
25
ns
0
15
ns
80
ns
LLSEL = high
Input Clock LLIN (refer to figure 6)
Cycle
TLLIN
68
H-pulse width
tWH
tWL
tTHL
tTHL
25
ns
LLSEL = high
25
ns
LLSEL = high
L-pulse width
Fall time
Rise time
74
2
5
ns
5
ns
Input Clock BLN (refer to figure 5)
H-pulse width
tSU
tIH
tWH
Cycle, 625 lines
Cycle, 525 lines
Setup time
Hold time
Semiconductor Group
15
ns
LLSEL = high
5
ns
LLSEL = high
720
TLL3X
TBLN
864
TLL3X
TBLN
858
TLL3X
17
1997-07-22
SDA 9290-6
Characteristics (cont’d)
(all voltages are referred to GND)
Parameter
Symbol
Limit Values
min.
typ.
Unit
Test Condition
max.
Input Signal VS1
Setup time
tSU
15
ns
Reference
LL3X
Hold time
tIH
5
ns
Reference
LL3X
Cycle, 625 lines
TVS1
312.5
TBLN
Cycle, 525 lines
TVS1
262.5
TBLN
H-pulse width, 625 lines
tWH
tWH
H-pulse width, 525 lines
26.5
TBLN
16.5
TBLN
Input Signal DREQ
Setup time
tSU
15
ns
Reference
LL3X
Hold time
tIH
5
ns
Reference
LL3X
H-pulse width
tWH
1
16
TLL3X
Input Signal (Data) YI0 … YI7, UVI0 … UVI7, YB0 … YB7, UVB0 … UVB7
(refer to figure 5)
Setup time
tSU
15
ns
Reference
LL3X
Hold time
tIH
5
ns
Reference
LL3X
Setup time
tSU
tIH
15
ns
Reference LLIN
5
ns
Reference LLIN
Hold time
Semiconductor Group
18
1997-07-22
SDA 9290-6
Characteristics (cont’d)
(all voltages are referred to GND)
Parameter
Symbol
Limit Values
min.
typ.
Unit
Test Condition
max.
Output Signal (Data) YQ0 … YQ7, UVQ0 … UVQ7 (refer to figure 5)
Hold time
tQH
Delay time
tQD
6
50
ns
Reference
LL3X
ns
Reference
LL3X
CL = 30 pF
Note: The listed characteristics are ensured over the operating range of the integrated
circuit. Typical characteristics specify mean values expected over the production
spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and
the given supply voltage.
Semiconductor Group
19
1997-07-22
Figure 4
Application Circuit (simplified)
Semiconductor Group
Y 8
YI
V DD GND SDA SCL
12
SQB
YB
UVB 13.5 MHz
V DD GND
UVI
PP II
SDA 9290-6
12
SDC
YQ
UVQ 13.5 MHz
3 x TV-SAM
SDA 9251-2X
13.5 MHz
UV 4
13.5 MHz
12
BLN LLIN LLSEL VS1 DREQ LL3X
Y
GND
-( B-Y )
DP
SDA 9280
YI
SQA
27 MHz UVI
OEB
FSBQ
FSI
V DD
-( R-Y )
OEA
SCB WT RB SAC SAR SCAD RE RA SCA
SCA
CLL
BLN
SDA
SCL
V DD
LL1.5X
LL3X WT RB SAC SAR SCAD RE RA SCA MUX
LL1.5X
DREQ
20
VS1
VS
BLN
LL3
CFH
BLN2
FRM
VS
FRM
BLN
VS2
MSC III
SDA 9220-5
LLIN
VS2
LLSEL
HS2
CFH
CSY
HS2
CSY
WEI
ADR
V DD GND V DDA GND OSCI OSCO RST NW RESI RESO SDA SCL
C1
RF
C F1
UES09852
SDA 9290-6
1997-07-22
C 2 C F2
SDA 9290-6
T LLIN ,TLL3X
t WH
t THL
t WL
t TLH
Input Clocks
LL3X, LLIN
2.0V
0.8V
t SU
t IH
2.0V
Input Signals
0.8V
t QH
2.4V
Output Signals
0.4V
t QD
UET02221
Figure 5
Timing Diagram
Semiconductor Group
21
1997-07-22
SDA 9290-6
T LLIN
t WH
t WL
VH
Input Clock
VL
t SK
t THL
t TLH
VQH
Reference Clock
LL3X
VQL
t WH
t THL
t WL
t TLH
T
T LL3X
Output
Reference Clock
2.4V
0.4V
t WH
t THL
t WL
t TLH
t QH
2.4V
Output Signal
0.4V
t QD
T LLIN
t WH
t THL
t WL
t TLH
Input
Reference Clock
2.0V= VIH
0.8V= VIL
t SU
t IH
2.0V
Input Signal
0.8V
UET02222
Figure 6
Timing Diagram
Semiconductor Group
22
1997-07-22
SDA 9290-6
t HD, STA
SDA
t TLH
t BUF
t THL
SCL
Stop
Start
t LOW
t HIGH
t HD, DAT
Stop
t SU, DAT
t SU, STO
UET00130
Figure 7
Timing for I2C Bus
Table 1
All values are referred to specified input levels VIH and VIL.
Parameter
Symbol
Clock frequency
Inactive time before start of new transmission
Hold time for start condition
(after this time first clock pulse is generated)
Low clock phase
High clock phase
Setup time for data
Rise time for SDA and SCL signals
Fall time for SDA and SCL signals
Setup time for SCL clock in stop condition
Semiconductor Group
23
Limit Values
min.
max.
fSCL
tBUF
tHD; STA
0
100
tLOW
tHIGH
tSU; DAT
tTLH
tTHL
tSU; STO
Unit
kHz
4.7
µs
4.0
µs
4.7
µs
4.0
µs
250
ns
4.7
1
µs
300
ns
µs
1997-07-22
SDA 9290-6
720 Pixels
84(71) Lines
18(15) Lines
288(243) Lines
18(15) Lines
48 Pixels
208 Pixels
48 Pixels
1
2
3
4
5
6
7
8
9
Without Frame
Stored
Picture
82(69) Lines
20(17) Lines
2(2) Lines
18(15) Lines
48 Pixels
204 Pixels
52 Pixels
4 Pixels
1
2
3
4
5
6
7
8
9
With Frame
50(60)-Hz Standard
UES02223
Figure 8
Picture Formats for 9-Image Display
Semiconductor Group
24
1997-07-22
SDA 9290-6
Table 2
Assignment of Signal and Pin Names
Format 4:1:1
Y:7-Bit Signal
Y:8-Bit Signal
Picture Processor
Input
Back
Channel
Input
Output
Y6
Y7
YI7
YB7
YQ7
Y5
Y6
YI6
YB6
YQ6
Y4
Y5
YI5
YB5
YQ5
Y3
Y4
YI4
YB4
YQ4
Y2
Y3
YI3
YB3
YQ3
Y1
Y2
YI2
YB2
YQ2
Y0
Y1
YI1
YB1
YQ1
–
Y0
YI0
YB0
YQ0
U6 U4 U2 U0
U7 U5 U3 U1
UVI7
UVB7
UVQ7
U5 U3 U1
U6 U4 U2 U0
UVI6
UVB6
UVQ6
V6 V4 V2 V0
V7 V5 V3 V1
UVI5
UVB5
UVQ5
V5 V3 V1
V6 V4 V2 V0
UVI4
UVB4
UVQ4
Y: Luminance Signal
U: Chrominance Signal
V: Chrominance Signal
Semiconductor Group
25
1997-07-22
SDA 9290-6
Table 3
Assignment of Signal and Pin Names
Format 4:2:2
Signal
Picture Processor
Input
Back Channel
Input
Output
Y7
YI7
YB7
YQ7
Y6
YI6
YB6
YQ6
Y5
YI5
YB5
YQ5
Y4
YI4
YB4
YQ4
Y3
YI3
YB3
YQ3
Y2
YI2
YB2
YQ2
Y1
YI1
YB1
YQ1
Y0
YI0
YB0
YQ0
UV7
UVI7
UVB7
UVQ7
UV6
UVI6
UVB6
UVQ6
UV5
UVI5
UVB5
UVQ5
UV4
UVI4
UVB4
UVQ4
UV3
UVI3
UVB3
UVQ3
UV2
UVI2
UVB2
UVQ2
UV1
UVI1
UVB1
UVQ1
UV0
UVI0
UVB0
UVQ0
Semiconductor Group
26
1997-07-22
SDA 9290-6
Figure 9
Output Data Delay Times
Semiconductor Group
27
1997-07-22
SDA 9290-6
Package Outlines
GPL05099
P-LCC-68-1 (SMD)
(Plastic Leaded Chip Carrier)
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
28
Dimensions in mm
1997-07-22