PHILIPS SAA4998H

INTEGRATED CIRCUITS
DATA SHEET
SAA4998H
Field and line rate converter with
noise reduction and embedded
memory
Product specification
2004 Feb 18
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
CONTENTS
SAA4998H
10
CHARACTERISTICS
11
PACKAGE OUTLINE
12
SOLDERING
12.1
1
FEATURES
2
GENERAL DESCRIPTION
2.1
2.2
Patent notice
Latch-up test
3
QUICK REFERENCE DATA
4
ORDERING INFORMATION
5
BLOCK DIAGRAMS
6
PINNING
12.6
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
Additional soldering information
7
CONTROL REGISTER DESCRIPTION
13
DATA SHEET STATUS
8
LIMITING VALUES
14
DEFINITIONS
9
THERMAL CHARACTERISTICS
15
DISCLAIMERS
2004 Feb 18
12.2
12.3
12.4
12.5
2
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
1
SAA4998H
2
FEATURES
• Motion compensated frame rate upconversion of all 1fH
film and video standards up to 292 active input lines per
field:
GENERAL DESCRIPTION
The SAA4998H is a high performance video processor
featuring Natural Motion(2), for all global TV standards
(PAL, NTSC and SECAM). It is used together with the
picture improvement processor SAA4978H and
SAA4979H.
– 50 Hz interlaced to 60 Hz progressive
{(60p mode for LCD and Plasma Display (PDP) TV}
The SAA4998H is an advanced version of the SAA4993H.
By embedding the field memories it reduces the part count
of the realized concept from 4 to 6 parts to only 2 parts and
reduces the package size from a QFP160 to a QFP100.
– 50 Hz interlaced to 75 Hz interlaced
{75i mode for jumbo screens, Projection TV (PTV)}
– 50 Hz interlaced to 100 Hz interlaced
(high-end 100 Hz TV)
The full FALCONIC mode uses full motion estimation and
motion compensation on 1/4 pixel accuracy to perform
– 50 Hz interlaced to 50 Hz progressive
(progressive scan TV and LCD and PDP TV)
• Frame rate upconversion
– 60 Hz interlaced to 60 Hz progressive
(progressive scan TV and LCD and PDP TV)
• Film mode detection
– 60 Hz interlaced to 90 Hz interlaced
(jumbo screens, PTV)
• Movie judder cancellation
– 60 Hz interlaced to 120 Hz interlaced
(multistandard high-end 100 Hz TV)
• Edge Dependent De-Interlacing (EDDI).
• Dynamic Noise Reduction (DNR)
The motion compensated de-interlacer is improved with a
new patented Edge Dependent De-Interlacing (EDDI)
method. This avoids jagged edges of diagonal lines. The
better de-interlacer leads to a significant better
performance of progressive as well as interlaced output
formats.
• 480 active lines (NTSC like) or 506 active lines in 50 Hz
interlaced to 60 Hz progressive mode
• Motion compensated and Edge Dependent
De-Interlacing (EDDI)(1)
• Motion estimated film mode detection
• Motion compensated movie judder cancellation:
A 60 Hz progressive output frame rate can be generated
for 50 Hz PAL sources to enable the use of 60 Hz LCD or
PDP panels in PAL regions.
– 25 Hz 2 : 2 pull-down (PAL) to 60 Hz progressive or
75 Hz interlaced or 100 Hz interlaced or 50 Hz
progressive
50 Hz interlaced to 75 Hz interlaced and 60 Hz interlaced
to 90 Hz interlaced can be generated to achieve an
increased number of lines and hence a reduction of line
visibility for jumbo screens and PTV applications.
– 30 Hz 2 : 2 pull-down (NTSC) to 60 Hz progressive or
90 Hz interlaced or 120 Hz interlaced
– 24 Hz 3 : 2 pull-down (NTSC) to 60 Hz progressive or
90 Hz interlaced or 120 Hz interlaced
The embedded memory can be used to synchronize the
main channel and the 2nd channel for PIP and double
window applications. This avoids to add additional buffer
memory devices to the application.
• Variable vertical sharpness enhancement
• High quality vertical zoom
• Motion compensated temporal noise reduction with
after-imaging cancellation
For demonstration purposes a split screen mode to show
the Dynamic Noise Reduction (DNR) function, natural
motion, and EDDI is available. The estimated motion
vectors can be made visible by colour overlay mode.
• Split screen demonstration mode
• 2 Mbaud serial interface (SNERT)
• Embedded 2 × 2.9-Mbit DRAM
The SAA4998H supports a Boundary Scan Test (BST)
circuit in accordance with “IEEE Std. 1149.1”.
• Full 8-bit accuracy
• Memory buffer for Picture-In-Picture (PIP)
• Lead-free package.
(1) EDDI is protected with two patents of Koninklijke Philips
Electronics N.V.
2004 Feb 18
(2) Natural Motion is a trademark of Koninklijke Philips
Electronics N.V.
3
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
2.1
Patent notice
SAA4998H
2.2
Latch-up test
Latch-up test in accordance with “Latch-up Resistance
and Maximum Ratings Test; SNW-FQ-303”; the
SAA4998H fulfils the requirements.
Notice is herewith given that the subject integrated circuit
uses one or more of the following US patents and that
each of these patents may have corresponding patents in
other jurisdictions.
US 4740842, US 5929919, US 6034734, US 5534946,
US 5532750, US 5495300, US 5903680, US 5365280,
US 5148269, US 5072293, US 5771074, and
US 5302909.
3
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
VDDD
core supply voltage (internal rail)
VDDA
analog supply voltage
VDDM
field memory supply voltage
VDDS
SRAM supply voltage
VDDE
external supply voltage (output pads)
VDDP
high supply voltage of internal field memories
IDD
sum of supply current
TYP.
MAX.
UNIT
1.65
1.8
1.95
V
3.0
3.3
3.6
V
at 1.8 V supply voltage pins
−
180
−
mA
at 3.3 V supply voltage pins
−
6
−
mA
fCLK
operating clock frequency
−
32
33.3
MHz
Tamb
ambient temperature
0
−
70
°C
4
ORDERING INFORMATION
TYPE
NUMBER
SAA4998H
2004 Feb 18
PACKAGE
NAME
DESCRIPTION
VERSION
QFP100
plastic quad flat package; 100 leads (lead length 1.95 mm);
body 14 × 20 × 2.8 mm
SOT317-2
4
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SNRST
ACV
RST
PIPON
TWOFMON
5
REA
IE
REF
TCK
TDO
TDI
TMS
TRSTN
CLK32
FIELD MEMORY 2
MEMORY CONTROL
FIELD MEMORY 3
94
41
34
33
SNERT
INTERFACE
COMPRESS
DECOMPRESS
25
32
MUX
MUX
36
50
CONTROL
DE-INTERLACER
WITH EDDI
63
68, 69,
71 to 76
64
vectors
67
MPR
LEFT
31
TPM
ESM
MPR
RIGHT
VERTICAL
ZOOM
95, 100,
1, 2,
5 to 8
YF7 to YF0
YG7 to YG0
MOTION ESTIMATOR
30
29
SPM
VERTICAL
PEAKING
Field and line rate converter with noise
reduction and embedded memory
SNCL
SNDA
DYNAMIC
NOISE
REDUCTION
BLOCK DIAGRAMS
VD
55 to 62
Philips Semiconductors
5
2004 Feb 18
YA0 to YA7
BST/ TEST
vectors
28
27
UPCONVERSION
SAA4998H
LUMINANCE PART
83
coc001
Product specification
SAA4998H
Fig.1 Block diagram luminance part in full FALCONIC mode.
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UVA0 to UVA7
42 to 47,
53, 54
DECOMPRESS/
REFORMAT
FIELD MEMORY 3
DECOMPRESS/
REFORMAT
DNR
6
vectors
MPR
LEFT
MPR
RIGHT
UPCONVERSION
FORMAT
VERTICAL
ZOOM
78 to 81,
88, 89,
92, 93
9 to 13,
17 to 19
Philips Semiconductors
COMPRESS/
FORMAT
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
FIELD MEMORY 2
UVF7 to UVF0
UVG7 to UVG0
SAA4998H
CHROMINANCE PART
coc002
Product specification
SAA4998H
Fig.2 Block diagram chrominance part in full FALCONIC mode.
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
6
SAA4998H
PINNING
SYMBOL
PIN
DESCRIPTION(1)(2)(3)
TYPE
YG5/DPIP5
1
output/input
PIP mode disabled: bus G luminance output bit 5;
PIP mode enabled: PIP data input bit 5
YG4/DPIP4
2
output/input
PIP mode disabled: bus G luminance output bit 4;
PIP mode enabled: PIP data input bit 4
VDDE
3
supply
supply voltage of output pads (3.3 V)
VSSE
4
ground
ground of output pads
YG3/DPIP3
5
output/input
PIP mode disabled: bus G luminance output bit 3;
PIP mode enabled: PIP data input bit 3
YG2/DPIP2
6
output/input
PIP mode disabled: bus G luminance output bit 2;
PIP mode enabled: PIP data input bit 2
YG1/DPIP1
7
output/input
PIP mode disabled: bus G luminance output bit 1;
PIP mode enabled: PIP data input bit 1
YG0/DPIP0
8
output/input
PIP mode disabled: bus G luminance output bit 0 (LSB);
PIP mode enabled: PIP data input bit 0 (LSB)
UVG7/QPIP7
9
output
PIP mode disabled: bus G chrominance output bit 7 (MSB);
PIP mode enabled: PIP data output bit 7 (MSB)
UVG6/QPIP6
10
output
PIP mode disabled: bus G chrominance output bit 6;
PIP mode enabled: PIP data output bit 6
UVG5/QPIP5
11
output
PIP mode disabled: bus G chrominance output bit 5;
PIP mode enabled: PIP data output bit 5
UVG4/QPIP4
12
output
PIP mode disabled: bus G chrominance output bit 4;
PIP mode enabled: PIP data output bit 4
UVG3/QPIP3
13
output
PIP mode disabled: bus G chrominance output bit 3;
PIP mode enabled: PIP data output bit 3
n.c./LLC
14
input
PIP mode disabled: not connected;
PIP mode enabled: line locked clock signal for PIP mode
VSSE
15
ground
ground of output pads
n.c./SWCK2
16
input
PIP mode disabled: not connected;
PIP mode enabled: serial write clock for PIP memory
UVG2/QPIP2
17
output
PIP mode disabled: bus G chrominance output bit 2;
PIP mode enabled: PIP data output bit 2
UVG1/QPIP1
18
output
PIP mode disabled: bus G chrominance output bit 1;
PIP mode enabled: PIP data output bit 1
UVG0/QPIP0
19
output
PIP mode disabled: bus G chrominance output bit 0 (LSB);
PIP mode enabled: PIP data output bit 0 (LSB)
n.c./RSTW2
20
input
PIP mode disabled: not connected;
PIP mode enabled: write reset clock for PIP memory
n.c./OIE2
21
input
PIP mode disabled: not connected;
PIP mode enabled: output enable for PIP memory output QPIPx
n.c./IE2
22
input
PIP mode disabled: not connected;
PIP mode enabled: input enable for PIP memory
VDDP
23
supply
high supply voltage of the internal field memories (3.3 V)
n.c./WE2
24
input
PIP mode disabled: not connected;
PIP mode enabled: write enable for PIP memory
2004 Feb 18
7
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
SYMBOL
PIN
SAA4998H
DESCRIPTION(1)(2)(3)
TYPE
ACV/RE2
25
output/input
PIP mode disabled: active video output;
PIP mode enabled: read enable for PIP memory
n.c./RSTR2
26
input
PIP mode disabled: not connected;
PIP mode enabled: read reset for PIP memory
TRSTN
27
input
boundary scan test reset input (active LOW); with internal pull-up resistor
TMS
28
input
boundary scan test mode select input; with internal pull-up resistor
TDI
29
input
boundary scan test data input; with internal pull-up resistor
TDO
30
3-state
boundary scan test data output
TCK
31
input
boundary scan test clock input; with internal pull-up resistor
RST
32
input
reset input; see Fig.4
SNRST
33
input
SNERT bus reset input; with internal pull-down resistor
SNDA
34
input/output
SNERT bus data input and output; with internal pull-down resistor
VDDE
35
supply
supply voltage of output pads (3.3 V)
PIPON
36
input
PIP mode enable input
VSSM
37
ground
field memory ground
VDDM
38
supply
supply voltage of the internal field memories (1.8 V)
VSSM
39
ground
field memory ground
VDDM
40
supply
supply voltage of the internal field memories (1.8 V)
SNCL
41
input
SNERT bus clock input; with internal pull-down resistor
UVA0
42
input
bus A chrominance input bit 0 (LSB)
UVA1
43
input
bus A chrominance input bit 1
UVA2
44
input
bus A chrominance input bit 2
UVA3
45
input
bus A chrominance input bit 3
UVA4
46
input
bus A chrominance input bit 4
UVA5
47
input
bus A chrominance input bit 5
VDDD
48
supply
core supply voltage (1.8 V)
VSSD
49
ground
core ground
TWOFMON
50
input
to be connected to ground
VDDS
51
supply
supply voltage of the internal SRAMs (1.8 V)
VSSS
52
ground
ground of the internal SRAMs
UVA6
53
input
bus A chrominance input bit 6
UVA7
54
input
bus A chrominance input bit 7 (MSB)
YA0
55
input
bus A luminance input bit 0 (LSB)
YA1
56
input
bus A luminance input bit 1
YA2
57
input
bus A luminance input bit 2
YA3
58
input
bus A luminance input bit 3
YA4
59
input
bus A luminance input bit 4
YA5
60
input
bus A luminance input bit 5
YA6
61
input
bus A luminance input bit 6
YA7
62
input
bus A luminance input bit 7 (MSB)
REA
63
output
read enable output for bus A
2004 Feb 18
8
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
SYMBOL
PIN
SAA4998H
DESCRIPTION(1)(2)(3)
TYPE
IE
64
input
input enable for PIP mode
VDDD
65
supply
core supply voltage (1.8 V)
VSSD
66
ground
core ground
REF
67
input
read enable input for bus F and G; note 4
YF7
68
output
bus F luminance output bit 7 (MSB)
YF6
69
output
bus F luminance output bit 6
VSSE
70
ground
ground of output pads
YF5
71
output
bus F luminance output bit 5
YF4
72
output
bus F luminance output bit 4
YF3
73
output
bus F luminance output bit 3
YF2
74
output
bus F luminance output bit 2
YF1
75
output
bus F luminance output bit 1
YF0
76
output
bus F luminance output bit 0 (LSB)
VDDE
77
supply
supply voltage of output pads (3.3 V)
UVF7
78
output
bus F chrominance output bit 7 (MSB)
UVF6
79
output
bus F chrominance output bit 6
UVF5
80
output
bus F chrominance output bit 5
UVF4
81
output
bus F chrominance output bit 4
VSSE
82
ground
ground of output pads
CLK32
83
input
system clock input (32 MHz)
VDDS
84
supply
supply voltage of the internal SRAMs (1.8 V)
VSSS
85
ground
ground of the internal SRAMs
VDDD
86
supply
core supply voltage (1.8 V)
VSSD
87
ground
core ground
UVF3
88
output
bus F chrominance output bit 3
UVF2
89
output
bus F chrominance output bit 2
VSSA
90
ground
analog ground of the internal PLL
VDDA
91
supply
analog supply voltage of the internal PLL (1.8 V)
UVF1
92
output
bus F chrominance output bit 1
UVF0
93
output
bus F chrominance output bit 0 (LSB)
VD
94
input
vertical display synchronization input (reset for field memories)
YG7/DPIP7
95
output/input
PIP mode disabled: bus G luminance output bit 7 (MSB);
PIP mode enabled: PIP data input bit 7 (MSB)
VDDM
96
supply
supply voltage of the internal field memories (1.8 V)
VSSM
97
ground
field memory ground
2004 Feb 18
9
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
SYMBOL
VDDM
PIN
98
DESCRIPTION(1)(2)(3)
TYPE
supply
SAA4998H
supply voltage of the internal field memories (1.8 V)
VSSM
99
ground
field memory ground
YG6/DPIP6
100
output/input
PIP mode disabled: bus G luminance output bit 6;
PIP mode enabled: PIP data input bit 6
Notes
1. Not used input pins should be connected to ground.
2. Because of the noisy characteristic of the supply voltage of output pads (VDDE), it is recommended not to connect
VDDE directly at the high supply voltage of the intern field memories (VDDP). All pins VDDE should be buffered as close
as possible to the device. VDDP needs a low noise supply voltage, therefore, it is recommended that VDDP has to be
separated from VDDE by an external filter structure. Because of the high working frequency of the device, it is also
recommended to filter the core supply voltage (VDDD). All pins VDDD should be buffered as close as possible to the
device.
3. VSSD, VSSM and VSSS are connected internally.
4. REF rising edge must be after rising edge of SNRST in order to be detected.
2004 Feb 18
10
Philips Semiconductors
Product specification
81 UVF4
82 VSSE
83 CLK32
84 VDDS
85 VSSS
86 VDDD
YG5/DPIP5
1
80 UVF5
YG4/DPIP4
2
79 UVF6
VDDE
3
78 UVF7
VSSE
4
77 VDDE
YG3/DPIP3
5
76 YF0
YG2/DPIP2
6
75 YF1
YG1/DPIP1
7
74 YF2
YG0/DPIP0
8
73 YF3
UVG7/QPIP7
9
72 YF4
UVG6/QPIP6 10
71 YF5
UVG5/QPIP5 11
70 VSSE
UVG4/QPIP4 12
69 YF6
UVG3/QPIP3 13
68 YF7
n.c./LLC 14
67 REF
VSSE 15
66 VSSD
SAA4998H
n.c./SWCK2 16
65 VDDD
UVG2/QPIP2 17
64 IE
UVG1/QPIP1 18
63 REA
UVG0/QPIP0 19
62 YA7
n.c./RSTW2 20
61 YA6
n.c./OIE2 21
60 YA5
n.c./IE2 22
59 YA4
VDDP 23
58 YA3
n.c./WE2 24
57 YA2
ACV/RE2 25
56 YA1
n.c./RSTR2 26
55 YA0
11
TWOFMON 50
VSSD 49
VDDD 48
UVA5 47
UVA4 46
UVA3 45
UVA2 44
UVA1 43
UVA0 42
SNCL 41
VDDM 40
VSSM 39
VDDM 38
VSSM 37
PIPON 36
VDDE 35
51 VDDS
SNDA 34
52 VSSS
TDO 30
SNRST 33
53 UVA6
TDI 29
RST 32
54 UVA7
TMS 28
TCK 31
TRSTN 27
Fig.3 Pin configuration.
2004 Feb 18
87 VSSD
88 UVF3
89 UVF2
SAA4998H
90 VSSA
91 VDDA
92 UVF1
93 UVF0
94 VD
95 YG7/DPIP7
96 VDDM
97 VSSM
98 VDDM
99 VSSM
100 YG6/DPIP6
Field and line rate converter with noise
reduction and embedded memory
001aaa057
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NAME
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
DESCRIPTION(2)
DNR/peaking/colour
Kstep10
010
write; S
X X X X set LUT value: k = 1⁄16 if difference below (0 to 15)
Kstep0
Kstep1
Kstep32
X X X X
011
write; S
X X X X set LUT value: k = 2⁄8 if difference below (0 to 30 in multiples of 2)
Kstep2
Kstep3
Kstep54
X X X X
012
X X X X set LUT value: k = 4⁄8 if difference below (0 to 60 in multiples of 4)
Kstep5
X X X X
013
X X X X set LUT value: k = 6⁄8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,
64, 72, 80, 88, 96, 104, 112 or 120)
12
Kstep7
X X X X
014
X X X X set fixed Y value; used when FixY = 1 or in left part of split screen
(0, 1⁄16 to 14⁄16 or 16⁄16)
GainY
X X X
FixY
X
015
set gain in difference signal for adaptive DNR Y (1⁄8, 1⁄4, 1⁄2, 1, 2 or 4)
select fixed Y (adaptive or fixed) (full screen)
write; S
FixvalUV
X X X X set fixed UV value; used when FixUV = 1 or in left part of split screen
(0, 1⁄16 to 14⁄16 or 16⁄16)
GainUV
X X X
X
set gain in difference signal for adaptive DNR UV (1⁄8, 1⁄4, 1⁄2, 1, 2 or 4)
select fixed UV (adaptive or fixed) (full screen)
SAA4998H
Product specification
FixUV
set LUT value: k = 7⁄8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,
64, 72, 80, 88, 96, 104, 112 or 120)
write; S
FixvalY
Gain_fix_uv
set LUT value: k = 5⁄8 if difference below (0 to 60 in multiples of 4)
write; S
Kstep6
Gain_fix_y
set LUT value: k = 3⁄8 if difference below (0 to 30 in multiples of 2)
write; S
Kstep4
Kstep76
set LUT value: k = 1⁄8 if difference below (0 to 15)
Philips Semiconductors
CONTROL REGISTER DESCRIPTION
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
7
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016
write; S
VecComp
X X X set degree of horizontal vector compensation in Y DNR:
(0, 1⁄8, 2⁄8, 3⁄8, 4⁄8, 5⁄8, 6⁄8 or 7⁄8) of the vector
NoiseShape
X
PeakCoef
DNR_Colour_mode
DESCRIPTION(2)
noise shaping enable; this bit is set to logic 1 after reset or power-up
X X X X
017
set vertical peaking level: (0, +2, +3.5, +5, +6, x, x, x, x, x, x, x, x,
−12, −6 or −2.5) dB
write; S
ColourIn
X X select colour input format: (4 : 1 : 1, 4 : 2 : 2, 4 : 2 : 2 DPCM or
4 : 2 : 2)
ColourOut
X
NrofFMs
X
ColOvl
X
SlaveUVtoY
X
13
DnrSplit
X
DnrHpon
select colour output format: (4 : 1 : 1 or 4 : 2 : 2)
set number of field memories used for motion compensation: (1 or 2)
select vector overlay on colour output: (vector overlay or colour
from video path)
slave UV noise reduction to K factor of Y: (separate or slaved)
select split screen mode for DNR: (normal or split screen)
X
Philips Semiconductors
Peak_Vcomp
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
NAME
switch DNR high-pass on (DNR only active on low frequent spectrum:
(all through DNR or high bypassed)
Vertical zoom
Zoom1
018
write; F
ZoomSt98
X X zoom line step bits 9 and 8; line step = vertical distance between
successive output lines; usable range = 0 to 2 frame lines;
resolution 1⁄256 frame line
ZoomPo98
Zoom2
X X
01A
write; F
ZoomSt70
Zoom3
ZoomPo70
X X X X X X X X zoom line step bits 7 to 0 (see above)
X X X X X X X X zoom start position bits 7 to 0 (see above)
Product specification
write; F
SAA4998H
019
zoom start position bits 9 and 8; start position = vertical position of the
top display line; usable range = 1 to 3 frame lines; resolution 1⁄256
frame line
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01B
DESCRIPTION(2)
write; F
ZoomEnVal
X X X X zoom run in value = number of lines without zoom active
(0 to 15 lines)
ZoomDiVal
X X X X
zoom run out value = number of lines without zoom active
(−8 to +7 lines)
De-interlacer
Proscan1
01C
write; S
KlfLim
X X X X limitation of recursion factor in calculation of original line positions:
(1 to 16); 1 limits to almost full recursion, 16 limits to no recursion
KlfOfs
X X X X
14
Proscan2
01D
write; S
PlfLim
X X X X limitation of recursion factor in calculation of interpolated line
positions: (1 to 16); 1 limits to almost full recursion, 16 limits to no
recursion
PlfOfs
Proscan3
X X X X
01E
see KlfOfs; this offset applies to interpolated lines
write; S
PeakLim
DeiOfs
The transfer curve of the de-interlacing filter coefficient is determined
by the difference (Diff) between a line in the input field and the
counterpart in the previous field shifted over the estimated motion
vector. KlfOfs determines the bias of the transfer curve for the original
input line, such that coefficient = KlfOfs + F(Diff), where the function F
is calculated in the SAA4998H. The bias can take a value in the range
(0 to 15), representing decreasing filter strength.
Philips Semiconductors
Zoom4
SNERT
READ/
7 6 5 4 3 2 1 0
ADDRESS
WRITE(1)
(HEX)
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
NAME
X X X X Maximum that the peaked pixel is allowed to deviate from original pixel
value: deviation (0 to 30 in steps of 2). Above this deviation, the
peaked pixel is clipped to (original pixel + or − PeakLim).
X X X X
offset to bias between average and median in the initial de-interlacing,
if the KplFad = MIX option is chosen
Product specification
SAA4998H
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01F
write; F
PlfThr
X X X Multiplier threshold at which to switch the lower limit of the filter
coefficient for interpolated lines. Above this threshold, the differences
corresponding to the two neighbouring lines are used as clipping
parameters, below this threshold, the interpolated line difference is
used as clipping level. This parameter can be used to optimize the
de-interlacing quality in slowly moving edges; it is not likely to have
effect if PlfLim is high.
AdRecOut
X
ProDiv
Scaling factor to control the strength of the filtering for the interpolated
lines. A value 0 means no scaling (normal filtering), while 3 means
scaling by factor 8 (very strong filtering). This parameter can be used
to adjust the de-interlacing to varying level of noise in the input picture;
use higher scaling for higher noise.
15
X
0CB
disable all recursion in calculating pixels for frame memory (recursive
or non recursive)
write; S
VecRbf
X X X X Roll back factor on vectors used for motion-compensated
de-interlacing. Values 0 to 14 (on a scale of 16) indicate attenuation.
A value of 15 indicates no attenuation.
FadDiv
X X X
KplFad
Proscan6
select adaptive recursive or order statistic output (order statistic or
adaptive)
X X
KplOff
Proscan5
sensitivity scaling factor in transition from average to median in initial
de-interlacing
X
0F0
chooses between majority selection and median/average mix for initial
de-interlacing (majority or mix); when KplFad = 0, FadDiv and
DeiOfs are don’t cares
write; S
EddiOut
X turns EDDI on and off (off or on)
activates split screen demonstration mode for EDDI (off or on)
Factor to specify the size of the additional compensation area left and
right of the ‘real’ edge. A high factor (e.g. 1) can increase the
compensation in regions far away from the true edge (1, 1⁄2, 1⁄4 or 1⁄8).
Product specification
X
X X
SAA4998H
EddiDemo
EddiCmp
DESCRIPTION(2)
Philips Semiconductors
Proscan4
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
NAME
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0F1
write; S
EddiMR
X X Factor for the comparison of the monotonous regions belonging to two
edge points to verify an edge (1, 1⁄2, 1⁄4 or 1⁄8).
EddiED
X X
EddiDif
Proscan8
X X X X
0F2
Factor for the comparison of the monotonous regions belonging to two
edge points and the edge point distance to verify an edge
(1, 1⁄2, 1⁄4 or 1⁄8).
minimal required Y difference at edge point position to be a reliable
edge point; higher values result in higher reliability of EDDI, but less
edges will be detected (0 to 60 in multiples of 4)
write; S
EddiFil
X X X X minimal required edge filter value at start and end of the monotonous
region to be a reliable edge point; should be set higher in pictures with
noise (0 to 60 in multiples of 4)
EddiLng
X X
16
Proscan9
DESCRIPTION(2)
0F3
minimal required length of monotonous region to be reliable; higher
values result in higher reliability of EDDI, but less steep edges will be
detected (2, 3, 4 or 5)
Philips Semiconductors
Proscan7
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
NAME
write; S
EddiOfs
X X X X offset to increase or decrease the amount of EDDI compensation;
lower values increase the amount of compensation (1 to 16)
EddiLim
X X X X
limitation of the compensation factor of EDDI; 1 limits to full EDDI
compensation, 16 limits to almost no EDDI compensation (1 to 16)
General
NrBlks
020
write; S
NrBlks
X X X X X X number of blocks in active video (6 to 53, corresponds to
96 to 848 pixels), to be set as 1⁄16 (number of active pixels per
line + 15); take remarks on TotalPxDiv8 into consideration
TotalLnsAct98
write; S
X X X X X X X X total number of output lines (bits 7 to 0)
Product specification
021
total number of output lines (bits 9 and 8)
SAA4998H
TotalLnsAct70
X X
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DESCRIPTION(2)
TotalPxDiv8
022
write; S
X X X X X X X X Total number of pixels per line divided-by-8 (80 to 128, corresponds to
640 to 1024 pixels). The horizontal blanking interval is calculated as
TotalPxDiv8 − 2 × NrBlks and has to be in the range from 12 to 124
(corresponds to 96 to 992 pixels). Conclusion: TotalPxDiv8 has to be
set to 12 + 2 × NrBlks < TotalPxDiv8 < 124 + 2 × NrBlks and NrBlks
TotalPxDiv8 – 124
TotalPxDiv8 – 12
has to be set to ------------------------------------------------ < NrBlks < --------------------------------------------2
2
REaShift
023
write; S
X X X shift of REA signal in number of pixels (0, +1, +2, +3, −4, −3, −2 or −1)
WEbdREceShift
024
write; S
WEbdShift
X X X reserved
REceShift
X X X
025
write; S
ScalingFactor
0D6
write; S
FieldMemoryControl
000
write; F
17
POR
reserved
X power-on reset command, to be set high temporarily during start-up
(normal or reset); note 3
X X X X X X X X 8-bit scaling factor for EggSliceMix, EggSliceRgt and global activity
(the same factor for all registers).
ScalingFactor
output value (n+1) = ------------------------------------ × output value (n)
128
PIPON
X Picture-In-Picture (PIP) field memory mode enable
TWOFMON
0
PIPDataDelay
PIPStillPicture
Philips Semiconductors
SNERT
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ADDRESS
WRITE(1)
(HEX)
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
NAME
X
X
has to be set to logic 0
input data will be delayed by one clock cycle with respect to WE2
(write enable)
no new data will be written into the field memory
Product specification
SAA4998H
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DESCRIPTION(2)
Mode control
Control1
026
write; F
EstMode
X Set estimator mode; 0 = line alternating use of left and right estimator:
use in progressive scan except with vertical compress. 1 = field
alternating use of left and right estimator: use in field doubling and
progressive scan with vertical compress.
FilmMode
X
UpcMode
X X
MatrixOn
X
EmbraceOn
X
18
MemComp
MemDecom
X
X
set film mode; 0 = video camera mode; 1 = film mode
select upconversion quality; 00 = full, 01 = economy (DPCM),
10 = single memory with motion compensation, 11 = single memory
without motion compensation
set matrix output mode; 1 = double output, disabling vertical peaking;
0 = normal single output mode; this bit setting is the AND function of
BusGControl bits
Master enable for embrace mode (off or on); SwapMpr in control2
should be at ‘swap’ position to really cross-switch FM1 and FM3 field
outputs. Should be set to logic 0 except in film mode and FM3 is
present.
Philips Semiconductors
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
NAME
set memory compression (luminance DPCM) (off or on)
set memory decompression (luminance DPCM) (off or on)
Product specification
SAA4998H
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027
write; F
QQcurr
X Quincunx phase of current field (in TPM) (phase0 or phase1); this
needs to toggle each time a new field comes from FM1. In phase0 the
estimator operates on a checker-board pattern that starts with the left
upper block; in phase1 the other blocks are estimated.
QQprev
X
FldStat
X
FieldWeYUV
X
19
OddFM1
X
SwapMpr
VecOffs
DESCRIPTION(2)
X
X X
Quincunx phase of previous field (in TPM) (phase0 or phase1); this is
the value of QQcurr during the last estimate written into the temporal
prediction memory
Field status (same input field or new input field); reflects whether
the output of FM1 is a new or a repeated field. This bit will toggle field
by field in field doubling mode and is continuously HIGH in progressive
output mode.
enable writing FM2 and FM3 for both luminance and chrominance
(recirculation of data for luminance alone can be controlled with
OrigFmEnY and IntpFmEnY in Control3) (off or on)
odd input field (even or odd), this is to be set equal to the detected
field interlace for the field that comes out of FM1
Philips Semiconductors
Control2
SNERT
READ/
7 6 5 4 3 2 1 0
ADDRESS
WRITE(1)
(HEX)
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
NAME
Swap multi port RAMs (normal or swap); this bit needs to be set to
get real frame data at the temporal position from FM1. If swapped, the
current field (FM1) will be stored in the right line memory tree, while
the original lines from the stored frame (FM2/3) are stored in the left
memory tree. Should be set only in film mode if FM3 is present;
EmbraceOn must be set as well.
Product specification
SAA4998H
Set vertical vector offset (0, +1, − or −1) frame lines; vertical offset of
the right line memory tree with respect to the left line memory tree.
A higher offset value means: on the right memory tree access to less
delayed video lines is taken; in interlaced video operation, the vertical
offset will be −1 with an odd field on the left side and +1 with an even
field on the left. With non-interlaced input, vertical offset should be
constantly 0. In film mode, vertical offset is dynamically switched
between +1, 0 and −1.
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028
OddLeft
write
F
X interlace (even or odd) phase of the field which is written to the left
line memory tree (left MPRAM)
OrigFmEnY
X
IntpFmEnY
X
FillTPM
X
VertOffsDNR
X X
20
BusGControl
DESCRIPTION(2)
S
X X
enables writing luminance from de-interlacer in original field memory
(FM2), otherwise recirculation of luminance that is just read from FM2
(recirculate or update)
enables writing luminance from de-interlacer in interpolated field
memory (FM3), otherwise recirculation of luminance that is just read
from FM3 (recirculate or update)
Enables writing in temporal prediction memory (keep or update);
FillTPM should be set to ‘keep’ in single memory film mode, in those
output fields where FM1 and FM2 contain the same motion phase.
FillTPM should be set to ‘update’ in all other situations.
Set vertical vector offset of DNR (0, +1, − or −1) frame lines; vertical
offset of the right line memory tree with respect to the left line memory
tree, before the swap action. A higher offset value means: on the right
memory tree access to less delayed video lines is taken; in interlaced
video operation, the vertical offset will be −1 with an odd field on the
left side and +1 with an even field on the left. With non-interlaced
input, vertical offset should be constantly logic 0; in film mode, vertical
offset is dynamically switched between +1, 0 and −1. It should be
noted that the signal OddFM1 is used to determine this offset.
Philips Semiconductors
Control3
SNERT
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ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
NAME
Select output mode of bus G; 00 = normal single output mode (bus G
in 3-state), 01 = output of motion vectors to UVG (motion_x on U and
motion_y on V), 10 = copy bus F to G, 11 = double output, disabling
vertical peaking. Only when double output is selected, the MatrixOn
bit in register Control1 should be set, otherwise it needs to be cleared.
Upconversion
write; F
X X X X X X temporal interpolation factor used in luminance upconverter; value
ranges from 0 (for current field position) to 32 (for previous field
position)
SAA4998H
UpcShFac
029
Product specification
Upconv1
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02A
write
YVecClip
S
RollBack
F
Upconv3
02B
X X X value used for coring the vertical vector component before application
in the upconverter; range: 0 to 3.5 in steps of 0.5 line; should remain
at logic 0 in normal operation
X X X X X
roll back factor ranging from 0 (use 0% of estimated vectors) to 16
(use 100% of estimated vectors)
write; S
MelzLfbm
X single memory type local fallback method instead of more robust local
fallback (double memory or single memory type fallback)
Melzmemc
X
MelDeint
X
21
MixCtrl
X X X X X
UpcColShiFac
0C4
write; F
Upconv4
0C5
write; S
use horizontal motion compensated median for upconverter
de-interlacing (full FALCONIC or single memory type
de-interlacing)
Bits 3 and 4 are used to control sensitivity to local vector smoothness
(0 = sensitive to unsmoothness, 3 = hardly sensitive to
unsmoothness). Bits 5 to 7 define the maximum contribution of
non-motion compensated pixels to the output
(0, 1⁄8, 2⁄8, 3⁄8, 4⁄8, 5⁄8, 6⁄8 or 7⁄8).
X X X Number of consecutive lines to have bad egg-slice values before
upconverter goes into protection mode (0, 1, 2, 4, 8, 16, 32 or 64).
A value of 0 switches off the possibility to go into protection.
MCDemo
X
write; S
X X X X X X X X Reference line number at which the egg slice measurement should
start. SAA4998H defines a window internally as number of lines
between EggStartLine and (MaxRefLine − EggStartLine).
Product specification
0C6
mode switch on left side of the screen; 0 (natural motion); 1 (digital
scan-like processing)
SAA4998H
EggStartLine
single memory film mode control (double memory or single memory
type); should be set in single memory film mode to ensure that only
original lines are selected as output when UpcShFac is 0 or 32
X X X X X X temporal interpolation factor used in chrominance upconverter; value
ranges from 0 (for current field position) to 32 (for previous field
position)
LfIndex
EggSlice1
DESCRIPTION(2)
Philips Semiconductors
Upconv2
SNERT
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7 6 5 4 3 2 1 0
ADDRESS
WRITE(1)
(HEX)
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
NAME
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0C7
write; S
EggSlcThr
X X X X X X Minimum line egg slice right value to activate reliability measurement.
The parameter is multiplied internally by 4.
EggRelInd
SafeShiFac
DESCRIPTION(2)
X X
0C8
write; F
02C
write; S
The egg slice reliability is computed internally as
EggSliceRgt (ESR) > RelFactor × EggSliceMix (ESM). RelFactor is
determined by EggRelInd (2⁄8, 3⁄8, 4⁄8 or 6⁄8).
X X X X X X upconverter shift factor to be used in protection mode; 0 (for current
field position) to 32 (for previous field position)
Motion estimator
Motest1
PenOdd
X X X additional penalty on vector candidates with odd vertical component
(0, 8, 16, 32, 64, 128, 256 or 511)
SpcThr
X X X
22
Active when EstMode = 0; replace the spatial prediction of one
estimator (left or right) by that of the other if the match error of the
former exceeds that of the latter by more than (0, 8, 16, 32, 64, 128,
256 or 511). A higher threshold means the two estimators are very
independent.
BmsThr
Motest2
X X
02D
Active when EstMode = 0; select as estimated vector the output of the
right estimator unless its match error exceeds that of the left estimator
by more than (0, 8, 16 or 32). This parameter should normally be set
to logic 0.
write; S
TavLow
X If the difference between the current vector and the previous one in
the same spatial location is within a small window, then the two
vectors are averaged to improve temporal consistency. TavLow is the
lower threshold of this window (1 or 2).
TavUpp
X X
X X
scaling factor to reduce all sizes of update vectors in the ensemble
with large sized vector templates (1, 1⁄2, 1⁄4 or 1⁄8)
SAA4998H
X X
see above; TavUpp is the upper threshold (0, 4, 8 or 16)
scaling factor to reduce all sizes of update vectors in the ensemble
with medium sized vector templates (1, 1⁄2, 1⁄4 or 1⁄8)
Product specification
MedEns
LarEns
Philips Semiconductors
EggSlice2
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
NAME
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02E
write; F
MotShiFac
Motest4
X X X X X X Motion estimator shift factor, being the temporal position used in the
estimator at which the matching is done; value 32 for matching at
previous field position down to 0 for matching at current field position.
Keeping MotShiFac equal to UpShiFac in the next upconverted output
field estimates for minimum matching errors (minimum Halo’s).
MotShiFac at value 16 gives the largest natural vector range (twice as
large as with value 0 or 32). Going above the range with
MotShiFac ≠ 16 is dealt with in SAA4998H by shifting towards 16, but
for the horizontal and vertical component separately (consequence is
that vector candidates tend to rotate towards the diagonal directions).
02F
write; S
PenRng
23
X Penalty for vectors estimated on the first row and the first column (if
left estimator is used) or the right column (if right estimator is used),
whenever the spatial prediction candidate is selected (64 or 511).
For noisy pictures, this register could be set to logic 1 to improve
border processing in the estimator.
CndSet
X
ErrThr
X X X
ErrHbl
X X
TstMod
Motest5
DESCRIPTION(2)
X
0CC
Philips Semiconductors
Motest3
SNERT
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ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
NAME
choice of candidate set (left or right) for which data (Candidate1 to
Candidate8) is written in this field (becomes active in next field);
note 3
threshold on block match error for considering a block to be bad
(16, 32, 64, 128, 256, 512, 1024 or 2032)
number of horizontally adjacent blocks that have to be all bad before
considering an occurrence of a burst error (1, 2, 4 or 8) (counting of
burst errors is read out with BlockErrCnt, address 0A8H)
to be kept to logic 1 for normal operation
write; S
ActOption
X
write zeros in the temporal prediction memory
(no writing or writing zeros)
LoActThr
0CD
write; S
X X X X X X X X blocks having an activity value below or equal to this threshold are
counted as having LOW activity
HiActThr
0CE
write; S
X X X X X X X X blocks having an activity value above this threshold are counted as
having HIGH activity
SAA4998H
ClearTPM
Product specification
X X selection of the vector component to take in the activity count
(x + y, x, y or −)
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0CF
DESCRIPTION(2)
write; S
LeftBorder
X X X X X X X estimator left border (in 8-pixel blocks)
WinNullWrite
X
enable writing of null vectors outside estimators’ active window
(off or on)
RightBorder
0D0
write; S
X X X X X X X estimator right border (in 8-pixel blocks)
TopBorder
0D1
write; S
X X X X X X X estimator top border (in 4-line blocks)
BottomBorder
0D2
write; S
X X X X X X X estimator bottom border (in 4-line blocks)
Candidate1
090
write; S
Candidat1
X X X selection Candidate1 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update1
X X
Penalty1
Candidate2
X X X
091
penalty for Candidate1 (0, 8, 16, 32, 64, 128, 256 or 511)
write; S
24
Candidat2
X X X selection Candidate2 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update2
X X
Penalty2
Candidate3
X X X
092
penalty for Candidate2 (0, 8, 16, 32, 64, 128, 256 or 511)
X X X selection Candidate3 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update3
X X
Penalty3
X X X
093
update for Candidate3 (zero update, medium update, large update
or zero update)
penalty for Candidate3 (0, 8, 16, 32, 64, 128, 256 or 511)
write; S
Update4
X X
X X X
update for Candidate4 (zero update, medium update, large update
or zero update)
penalty for Candidate4 (0, 8, 16, 32, 64, 128, 256 or 511)
Product specification
X X X selection Candidate4 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
SAA4998H
Candidat4
Penalty4
update for Candidate2 (zero update, medium update, large update
or zero update)
write; S
Candidat3
Candidate4
update for Candidate1 (zero update, medium update, large update
or zero update)
Philips Semiconductors
LeftBorder
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
NAME
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094
write; S
Candidat5
X X X selection Candidate5 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update5
X X
Penalty5
Candidate6
X X X
095
write; S
X X X selection Candidate6 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update6
X X
Penalty6
X X X
096
update for Candidate6 (zero update, medium update, large update
or zero update)
penalty for Candidate6 (0, 8, 16, 32, 64, 128, 256 or 511)
write; S
Candidat7
25
X X X selection Candidate7 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update7
X X
Penalty7
Candidate8
update for Candidate5 (zero update, medium update, large update
or zero update)
penalty for Candidate5 (0, 8, 16, 32, 64, 128, 256 or 511)
Candidat6
Candidate7
DESCRIPTION(2)
X X X
097
update for Candidate7 (zero update, medium update, large update
or zero update)
Philips Semiconductors
Candidate5
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
NAME
penalty for Candidate7 (0, 8, 16, 32, 64, 128, 256 or 511)
write; S
Candidat8
X X X selection Candidate8 (SpatLeft, SpatRight, TemporalRight,
TemporalLeft, TemporalCentre, Null, Panzoom or Max)
Update8
X X
Penalty8
X X X
update for Candidate8 (zero update, medium update, large update
or zero update)
penalty for Candidate8 (0, 8, 16, 32, 64, 128, 256 or 511)
write; S
X X X X X X X position of LeftUpp measurement point for pan-zoom calculations
(resolution: 16 pixels)
PZpositionLeftUppY
099
write; S
X X X X X X X Y position of LeftUpp measurement point for pan-zoom calculations
(resolution: 4 lines)
PZpositionRightLowX 09A
write; S
X X X X X X X position of RightLow measurement point for pan-zoom calculations
(resolution: 16 pixels)
PZpositionRightLowY 09B
write; S
X X X X X X X Y position of RightLow measurement point for pan-zoom calculations
(resolution: 4 lines)
PZvectorStartX
write; F
09C
X X X X X X X X X start value of pan-zoom vectors
Product specification
098
SAA4998H
PZpositionLeftUppX
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DESCRIPTION(2)
PZvectorDeltaX
09D
write; F
X X X X X X X X X delta value of pan-zoom vectors
PZvectorStartY
09E
write; F
X X X X X X X X Y start value of pan-zoom vectors
PZvectorDeltaY
09F
write; F
X X X X X X X X Y delta value of pan-zoom vectors
GlobalMSEmsb
0A0
read; F
GlobalMSElsb
0A1
read; F
X X X X X X X X Global Mean Square Error (MSE) = summation within a field period of
X X X X X X X X squared differences in comparing vector shifted video from frame
memory (FM2/3) with new field input (FM1) in those lines coinciding
with new field lines. The window for the measurement is kept at
40 pixels horizontal and 20 field lines vertical from the border of the
video. Measurements is only done in fields where the de-interlacer is
active, otherwise reading is zero. In field doubling mode, MSE is zero
at the end of every new input field.
GlobalMTImsb
0A2
read; F
GlobalMTIlsb
0A3
read; F
GlobalACTmsb
0A4
read; F
GlobalACTlsb
0A5
read; F
VectTempCons
0A6
read; F
X X X X X X X X Vector temporal consistency = summation over a field period of
absolute differences of horizontal plus vertical components of vectors
newly estimated for each block compared with those vectors
estimated in the previous run at the same spatial block position.
It should be noted that a lower figure implies better consistency.
VectSpatCons
0A7
read; F
X X X X X X X X Vector spatial consistency = summation over a field period of absolute
differences of horizontal and vertical components of vectors compared
with those of the neighbour blocks (L, R, U and D); in the comparison,
all vector data is used from the previous estimator run. It should be
noted that a lower figure implies better consistency.
BlockErrCnt
0A8
read; F
X X X X X X X X burst error count (number of burst errors)
Read data; note 3
26
X X X X X X X X Global Motion Trajectory Inconsistency (MTI) = summation within a
X X X X X X X X field period of squared differences comparing shifted video from frame
memory (FM2/3 output) with filtered data that is rewritten to the frame
memory (FM2/3 input) in those lines coinciding with new field lines.
The window for the measurement is kept at 40 pixels horizontal and
20 field lines vertical from the border of the video. Measurement is
done only in fields where de-interlacer is active, otherwise reading is
zero; in field doubling mode, MTI is zero at the end of every new input
field.
Philips Semiconductors
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
NAME
X X X X X X X X global activity (ACT) = summation over a field period of the horizontal
X X X X X X X X plus the vertical components of the vectors of all blocks
Product specification
SAA4998H
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DESCRIPTION(2)
read; F
X X X X X X X X least error sum (summation over a field period of the smallest match
error that the estimator has found for each block: indicates reliability of
the estimation process)
YvecRangeErrCntmsb 0AA
read; F
X X X X X X X X Y vector range error count (number of vectors that have a vertical
component that is out of range for upconversion at the chosen
temporal position) (15 to 8)
YvecRangeErrCntlsb
0AB
read; F
X X X X X X X X Y vector range error count (7 to 0)
RefLineCountPrev
0AC
read; F
X X X X X X X X read out of [number of input (run-) lines − 40] used in previous field
RefLineCountNew
0AD
write; F
X X X X X X X X Write of [number of input (run-) lines − 40] to be used in new field
(actual maximum number of input lines in normal operation: 292;
register value 252). Nominally this is to be set as an exact copy of the
value read from RefLineCountPrev before a new field starts. In case
the effective number of input (run-) lines has increased,
RefLineCountNew should, for one field, be set to 255. This will occur
e.g. with decreasing vertical zoom magnification or changing from
525 lines video standard to 625 lines standard. If this is not done, a
deadlock will occur with too few lines processed correctly by the
motion estimator.
PanZoomVec0-X
0B0
read; F
X X X X X X X X pan-zoom vector 0 (8-bit X value)
PanZoomVec0-Y
0B1
read
27
0A9
FalconIdent
S
PanZoomVec0-Y
0
F
PanZoomVec1-X
0B2
read; F
PanZoomVec1-Y
0B3
read
PanZoomVec1-Y
F
PanZoomVec2-X
0B4
read; F
PanZoomVec2-Y
0B5
read
StatusJump1
S
PanZoomVec2-Y
F
X X X X X X X pan-zoom vector 0 (7-bit Y value)
X X X X X X X X pan-zoom vector 1 (8-bit X value)
X
1: both field memories are in use by the motion estimation and motion
compensation function; see Fig.1
0: field memory 2 is in use by the motion estimation and motion
compensation function; field memory 3 for PIP application; see Fig.1
X X X X X X X pan-zoom vector 1 (7-bit Y value)
X X X X X X X X pan-zoom vector 2 (8-bit X value)
1
logic 1
X X X X X X X pan-zoom vector 2 (7-bit Y value)
Product specification
S
SAA4998H identification: fixed bit, reading this bit as zero means
SAA4998H is present
SAA4998H
StatusJump0
Philips Semiconductors
LeastErrSum
SNERT
READ/
ADDRESS
7 6 5 4 3 2 1 0
WRITE(1)
(HEX)
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
NAME
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DESCRIPTION(2)
28
read; F
X X X X X X X X pan-zoom vector 2 (8-bit X value)
PanZoomVec3-Y
0B7
read; F
X X X X X X X pan-zoom vector 3 (7-bit Y value)
PanZoomVec4-X
0B8
read; F
X X X X X X X X pan-zoom vector 4 (8-bit X value)
PanZoomVec4-Y
0B9
read; F
X X X X X X X pan-zoom vector 4 (7-bit Y value)
PanZoomVec5-X
0BA
read; F
X X X X X X X X pan-zoom vector 5 (8-bit X value)
PanZoomVec5-Y
0BB
read; F
X X X X X X X pan-zoom vector 5 (7-bit Y value)
PanZoomVec6-X
0BC
read; F
X X X X X X X X pan-zoom vector 6 (8-bit X value)
PanZoomVec6-Y
0BD
read; F
X X X X X X X pan-zoom vector 6 (7-bit Y value)
PanZoomVec7-X
0BE
read; F
X X X X X X X X pan-zoom vector 7 (8-bit X value)
PanZoomVec7-Y
0BF
read; F
X X X X X X X pan-zoom vector 7 (7-bit Y value)
PanZoomVec8-X
0AE
read; F
X X X X X X X X pan-zoom vector 8 (8-bit X value)
PanZoomVec8-Y
0AF
read; F
EggSliceRgtMSB
0C0
read; F
X X X X X X X X result of right pixels egg-slice detector (15 to 8)
EggSliceRgtLSB
0C1
read; F
X X X X X X X X result of right pixels egg-slice detector (7 to 0)
EggSliceMixMSB
0C2
read; F
X X X X X X X X result of mixed pixels egg-slice detector (15 to 8)
EggSliceMixLSB
0C3
read; F
X X X X X X X X result of mixed pixels egg-slice detector (7 to 0)
SafeFbLine
0C9
read; F
X X X X X X X X reference line number (divided by two) at which the upconverter goes
into protection mode
EggBinGoodness
0CA
read; F
X X X X X X X X Goodness of the four egg-slice sections, from top to bottom, 2 bits per
section. Each section is represented with 2 bits in this register, where
bits 0 and 1 represent the top section and bits 6 and 7 represent the
lowest of the 4 sections. Each pair of bits indicate
00 = (ESR > 3⁄4ESM), 01 = (1⁄2ESM < ESR ≤ 3⁄4ESM),
10 = (1⁄4ESM < ESR ≤ 1⁄2ESM), 11 = (ESR ≤ 1⁄4ESM).
LoActCnt
0D3
read; F
X X X X X X X X number of blocks having low activity
HiActCnt
0D4
read; F
X X X X X X X X number of blocks having high activity
NullErrSum
0D5
read; F
X X X X X X X X sum of errors for the null candidate over the complete field; when no
null candidate is selected a value of FFH will be read
X X X X X X X pan-zoom vector 8 (7-bit Y value)
Product specification
0B6
SAA4998H
PanZoomVec3-X
Philips Semiconductors
SNERT
READ/
7 6 5 4 3 2 1 0
ADDRESS
WRITE(1)
(HEX)
Field and line rate converter with noise
reduction and embedded memory
2004 Feb 18
NAME
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
SAA4998H
Notes
1. S means semi static, used at initialization or mode changes; F means field frequent, in general updated in each
display field.
2. Selectable items are marked bold.
3. Almost all of the R(ead) and W(rite) registers of SAA4998H are double buffered. The write registers are latched by
a signal called New_field. New_field gets set, when REF rises after SNRST (New_field is effectively at the start of
active video). The read registers are latched by a signal called Reg_upd. Reg_upd gets set, when half the number
of active pixels of the fourth line of vertical blanking have entered the SAA4998H (Reg_upd will effectively be
active 31⁄2 lines after the REA has ended). The only exception are the registers which are not double buffered, these
are as follows:
a) Write register 025H: power_on_reset
b) Write register 02FH, bit 1: CndSet
c) Read register 0B0H to 0BFH, 0AEH and 0AFH: pan_zoom_vectors, including FalconIdent (= 0), StatusJump0
and StatusJump1.
8 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
−0.5
+2.5
V
−0.5
+4.6
V
input voltage of all I/O pins
−0.5
+6(1)
V
Io
output current
−
4
mA
Tstg
storage temperature
−40
+125
°C
Tj
junction temperature
Vesd
electrostatic discharge voltage on all pins
VDDD
core supply voltage (internal rail)
VDDA
analog supply voltage
VDDM
field memory supply voltage
VDDS
SRAM supply voltage
VDDE
external supply voltage (output pads)
VDDP
high supply voltage of internal field memories
Vi
0
125
°C
MM; note 2
−400
+400
V
HBM; note 3
−3000
+3000
V
Notes
1. Only valid, if VDDE is present.
2. In accordance with “Transient energy (ESD machine model); SNW-FQ-302B” class C, discharging a 200 pF
capacitor via a 0.75 µH series inductance.
3. In accordance with “Transient energy (ESD human body model); SNW-FQ-302A” class 2, discharging a 100 pF
capacitor via a 1.5 kΩ series resistor.
9
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
Rth(j-a)
thermal resistance from junction to ambient
Rth(j-c)
thermal resistance from junction to case
2004 Feb 18
CONDITIONS
in free air
29
VALUE
UNIT
45
K/W
10
K/W
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
SAA4998H
10 CHARACTERISTICS
VDDE = 3.0 to 3.6 V; Tamb = 0 to 70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDD
core supply voltage (internal rail)
1.65
1.8
1.95
V
VDDA
analog supply voltage
VDDM
field memory supply voltage
VDDS
SRAM supply voltage
VDDE
external supply voltage (output pads)
3.0
3.3
3.6
V
VDDP
high supply voltage of internal field
memories
IDD
sum of supply current
at 1.8 V supply voltage pins
−
180
−
mA
at 3.3 V supply voltage pins
−
6
−
mA
General
VOH
HIGH-level output voltage
VDDE − 0.4
−
−
V
VOL
LOW-level output voltage
−
−
0.4
V
VIH
HIGH-level input voltage
2
−
−
V
VIL
LOW-level input voltage
−
−
0.8
V
IOH
HIGH-level output current
10 ns slew rate output;
VOH = VDDE − 0.4 V
−4
−
−
mA
IOL
LOW-level output current
10 ns slew rate output;
VOL = 0.4 V
−
−
4
mA
Ci
input capacitance
−
−
8
pF
ILI
input leakage current
−
−
1
µA
note 1
Outputs; see Fig.5; note 2
IOZ
output current in 3-state mode
−
−
1
µA
td(o)
output delay time
−0.5 < Vo < 3.6
−
−
23
ns
th(o)
output hold time
4
−
−
ns
tr
rise time
−
−
30
ns
tf
fall time
−
−
30
ns
tsu(i)
input set-up time
see Fig.5; note 3
6
−
−
ns
th(i)
input hold time
see Fig.5; note 3
2
−
−
ns
Inputs
Input CLK32; see Fig.5
tr
rise time
−
−
4
ns
tf
fall time
−
−
4
ns
δ
duty factor
40
−
60
%
Tcy
cycle time
30
−
39
ns
2004 Feb 18
30
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
SYMBOL
PARAMETER
SAA4998H
CONDITIONS
MIN.
TYP.
MAX.
UNIT
BST interface; see Fig.6
Tcy(BST)
BST cycle time
−
1
−
µs
tsu(i)(BST)
input set-up time
3
−
−
ns
th(i)(BST)
input hold time
6
−
−
ns
th(o)(BST)
output hold time
4
−
−
ns
td(o)(BST)
output delay
−
−
30
ns
500
−
−
ns
td(SNRST-SNCL) delay SNRST pulse to SNCL LOW
time
200
−
−
ns
Tcy(SNCL)
SNCL cycle time
0.5
−
1
µs
tsu(i)(SNCL)
input set-up time to SNCL
53
−
−
ns
th(i)(SNCL)
input hold time to SNCL
10
−
−
ns
th(o)
output hold time
30
−
−
ns
td(o)
output delay
−
−
330
ns
to(en)
output enable time
210
−
−
ns
SNERT interface; see Fig.7
tSNRST(H)
SNRST pulse HIGH time
Notes
1. All inputs except inputs with internal pull-up or pull-down resistor. These inputs have an absolute leakage current of
maximum 50 µA.
2. Timing characteristics are measured with CL = 15 pF.
3. All inputs except SNERT interface inputs, CLK32 input and BST/TEST inputs.
stable power supply
CLK32
≥10 cycles of CLK32
RST
coc003
Fig.4 Timing for RST input.
2004 Feb 18
31
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
tf
handbook, full pagewidth
90%
SAA4998H
tr
90%
CLOCK
1.5 V
10%
10%
INPUT
DATA
MHB175
tsu(i)
OUTPUT
DATA
th(i)
data
valid
data transition
period
th(o)
td(o)
Fig.5 Data input/output timing diagram.
Tcy(BST)
handbook, full pagewidth
TCK
TDI, TMS
t su(i)(BST)
t h(i)(BST)
TDO
t h(o)(BST)
t d(o)(BST)
Fig.6 Boundary scan test interface timing diagram.
2004 Feb 18
32
MHB649
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
SAA4998H
SNCL
write sequence:
SNDA
a0
a1
a2
a3
a4
a5
a6
a7
a0
a1
a2
a3
a4
a5
a6
a7
w0
w1
w2
w3
w4
w5
w6
w7
r0
r1
r2
r3
r4
r5
r6
r7
read sequence:
SNDA
driven by
master
SNDA
driven by
SAA4998H
SNCL
t su(i)(SNCL)
write sequence:
SNDA
read sequence:
SNDA
driven by
master
50 %
50 %
50 %
t h(i)(SNCL)
a6
a7
a6
a7
w0
t o(en)
SNDA
driven by
SAA4998H
w1
t h(o)
90 %
r0
t d(o)
10 %
r1
t d(o)
coc004
Fig.7 SNERT interface timing diagram.
2004 Feb 18
33
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
Table 1
SAA4998H
YUV formats
FORMAT(2)(3)
I/O PIN(1)
4:1:1
4:2:2
4 : 2 : 2 DPCM
Yx7
Y07
Y17
Y27
Y37
Y07
Y17
Y07
Y17
Yx6
Y06
Y16
Y26
Y36
Y06
Y16
Y06
Y16
Yx5
Y05
Y15
Y25
Y35
Y05
Y15
Y05
Y15
Yx4
Y04
Y14
Y24
Y34
Y04
Y14
Y04
Y14
Yx3
Y03
Y13
Y23
Y33
Y03
Y13
Y03
Y13
Yx2
Y02
Y12
Y22
Y32
Y02
Y12
Y02
Y12
Yx1
Y01
Y11
Y21
Y31
Y01
Y11
Y01
Y11
Yx0
Y00
Y10
Y20
Y30
Y00
Y10
Y00
Y10
UVx7
U07
U05
U03
U01
U07
V07
UC03
VC03
UVx6
U06
U04
U02
U00
U06
V06
UC02
VC02
UVx5
V07
V05
V03
V01
U05
V05
UC01
VC01
UVx4
V06
V04
V02
V00
U04
V04
UC00
VC00
UVx3
X
X
X
X
U03
V03
X
X
UVx2
X
X
X
X
U02
V02
X
X
UVx1
X
X
X
X
U01
V01
X
X
UVx0
X
X
X
X
U00
V00
X
X
Notes
1. Digit x refers to different I/O buses:
a) A = input from 1st field memory
b) F = main output
c) G = 2nd output for matrix purposes.
2. The first index digit defines the sample number and the second defines the bit number.
3. X = don’t care or not available.
2004 Feb 18
34
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
SAA4998H
11 PACKAGE OUTLINE
QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT317-2
c
y
X
80
A
51
81
50
ZE
e
E HE
A
A2
(A 3)
A1
θ
wM
pin 1 index
Lp
bp
L
31
100
detail X
30
1
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
3.2
0.25
0.05
2.90
2.65
0.25
0.40
0.25
0.25
0.14
20.1
19.9
14.1
13.9
0.65
24.2
23.6
18.2
17.6
1.95
1.0
0.6
0.2
0.15
0.1
Z D (1) Z E(1)
0.8
0.4
1.0
0.6
θ
o
7
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT317-2
2004 Feb 18
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-25
MO-112
35
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
To overcome these problems the double-wave soldering
method was specifically developed.
12 SOLDERING
12.1
Introduction to soldering surface mount
packages
If wave soldering is used the following conditions must be
observed for optimal results:
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
12.2
SAA4998H
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Driven by legislation and environmental forces the
worldwide use of lead-free solder pastes is increasing.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 270 °C depending on solder paste material. The
top-surface temperature of the packages should
preferably be kept:
Typical dwell time of the leads in the wave ranges from
3 to 4 seconds at 250 °C or 265 °C, depending on solder
material applied, SnPb or Pb-free respectively.
• below 225 °C (SnPb process) or below 245 °C (Pb-free
process)
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
– for all BGA, HTSSON-T and SSOP-T packages
12.4
– for packages with a thickness ≥ 2.5 mm
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
– for packages with a thickness < 2.5 mm and a
volume ≥ 350 mm3 so called thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free
process) for packages with a thickness < 2.5 mm and a
volume < 350 mm3 so called small/thin packages.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
Moisture sensitivity precautions, as indicated on packing,
must be respected at all times.
12.3
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
2004 Feb 18
Manual soldering
36
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
12.5
SAA4998H
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
REFLOW(2)
BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA,
USON, VFBGA
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,
HTQFP, HTSSOP, HVQFN, HVSON, SMS
not suitable(4)
suitable
PLCC(5), SO, SOJ
suitable
suitable
not
recommended(5)(6)
suitable
SSOP, TSSOP, VSO, VSSOP
not
recommended(7)
suitable
CWQCCN..L(8), PMFP(9), WQCCN..L(8)
not suitable
LQFP, QFP, TQFP
not suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account
be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature
exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature
must be kept as low as possible.
4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted
on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar
soldering process. The appropriate soldering profile can be provided on request.
9. Hot bar or manual soldering is suitable for PMFP packages.
12.6
Additional soldering information
The package QFP100 (lead-free; SOT317GC11, subpackage of the SOT317-2) is granted the Moisture Sensitivity
Level (MSL) 3.
Soldering temperature of > 215 °C is recommended or RMA flux.
2004 Feb 18
37
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
SAA4998H
13 DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
Development
DEFINITION
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
14 DEFINITIONS
15 DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2004 Feb 18
38
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA76
© Koninklijke Philips Electronics N.V. 2004
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R24/01/pp39
Date of release: 2004
Feb 18
Document order number:
9397 750 12217