MOTOROLA MTP5N40E

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by MTP5N40E/D
SEMICONDUCTOR TECHNICAL DATA
 
Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
5.0 AMPERES
400 VOLTS
RDS(on) = 1.0 OHM
This advanced high voltage TMOS E–FET is designed to
withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a drain–to–source diode
with fast recovery time. Designed for high voltage, high speed
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against
unexpected voltage transients.
• Avalanche Energy Capability Specified at Elevated
Temperature
• Low Stored Gate Charge for Efficient Switching
• Internal Source–to–Drain Diode Designed to Replace External
Zener Transient Suppressor — Absorbs High Energy in the
Avalanche Mode
• Source–to–Drain Diode Recovery Time Comparable to Discrete
Fast Recovery Diode

D
G
S
CASE 221A–06, Style 5
TO–220AB
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
Drain–Source Voltage
VDSS
400
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR
400
Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–repetitive
VGS
VGSM
± 20
± 40
Vdc
Vpk
Drain Current — Continuous
Drain Current — Pulsed
ID
IDM
5.0
12
Adc
Total Power Dissipation @ TC = 25°C
Derate above 25°C
PD
75
0.6
Watts
W/°C
TJ, Tstg
– 55 to 150
°C
WDSR (1)
mJ
WDSR (2)
290
46
7.4
RθJC
RθJA
1.67
62.5
°C/W
TL
260
°C
Rating
Operating and Storage Temperature Range
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (TJ < 150°C)
Single Pulse Drain–to–Source Avalanche Energy — TJ = 25°C
Single Pulse Drain–to–Source Avalanche Energy — TJ = 100°C
Repetitive Pulse Drain–to–Source Avalanche Energy
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient°
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
(1) VDD = 50 V, ID = 5.0 A
(2) Pulse Width and frequency is limited by TJ(max) and thermal response
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
TMOS
 Motorola
Motorola, Inc.
1996
Power MOSFET Transistor Device Data
1
MTP5N40E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
V(BR)DSS
400
—
—
Vdc
—
—
—
—
0.25
1.0
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0, ID = 250 µAdc)
Zero Gate Voltage Drain Current
(VDS = 400 V, VGS = 0)
(VDS = 320 V, VGS = 0, TJ = 125°C)
IDSS
mAdc
Gate–Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0)
IGSSF
—
—
100
nAdc
Gate–Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0)
IGSSR
—
—
100
nAdc
2.0
1.5
—
—
4.0
3.5
—
0.8
1.0
—
—
—
—
6.2
5.0
gFS
2.0
—
—
mhos
Ciss
—
775
—
pF
Coss
—
96
—
Crss
—
22
—
td(on)
—
24
—
ON CHARACTERISTICS*
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
(TJ = 125°C)
VGS(th)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 2.5 Adc)
RDS(on)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 5.0 A)
(ID = 2.5 A, TJ = 100°C)
VDS(on)
Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc)
Vdc
Ohm
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 25 V, VGS = 0,
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS*
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
(VDD = 250 V, ID ≈ 5.0 A,
RG = 12 Ω, RL = 50 Ω,
VGS(on) = 10 V)
Fall Time
Total Gate Charge
Gate–Source Charge
(VDS = 320 V, ID = 5.0 A,
VGS = 10 V)
Gate–Drain Charge
tr
—
34
—
td(off)
—
60
—
tf
—
36
—
Qg
—
27
32
Qgs
—
3.5
—
Qgd
—
14
—
VSD
—
—
1.4
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS*
Forward On–Voltage
Forward Turn–On Time
(IS = 5.0 A, di/dt = 100 A/µs)
Reverse Recovery Time
ton
trr
Vdc
ns
**
—
—
660
—
—
3.5
4.5
—
—
—
7.5
—
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
Ld
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
Ls
nH
* Indicates Pulse Test: Pulse Width = 300 µs Max, Duty Cycle ≤ 2.0%.
** Limited by circuit inductance.
2
Motorola TMOS Power MOSFET Transistor Device Data
MTP5N40E
10
VGS = 10 V
I D, DRAIN CURRENT (AMPS)
TJ = 25°C
7V
8
6V
6
4
5V
2
4V
0
0
4
8
12
16
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
20
VGS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)
TYPICAL ELECTRICAL CHARACTERISTICS
1.2
1
0.9
0.8
–50
Figure 1. On–Region Characteristics
VBR(DSS), DRAIN–TO–SOURCE BREAKDOWN
VOLTAGE (NORMALIZED)
I D, DRAIN CURRENT (AMPS)
VDS ≥ 10 V
8
6
4
TJ = 25°C
2
125°C
0
–55°C
2
4
6
8
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
10
1.1
25°C
0.8
–55°C
VGS = 10 V
0
4
6
8
VGS = 0
ID = 0.25 mA
1
0.9
0.8
–50
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
1.2
2
150
0
50
100
150
200
Figure 4. Breakdown Voltage Variation
With Temperature
TJ = 100°C
0
125
TJ, JUNCTION TEMPERATURE (°C)
2
0.4
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
1.2
Figure 3. Transfer Characteristics
1.6
–25
Figure 2. Gate–Threshold Voltage Variation
With Temperature
10
0
VDS = VGS
ID = 0.25 mA
1.1
10
2.5
2
VGS = 10 V
ID = 2.5 A
1.5
1
0.5
0
–50
0
50
100
150
ID, DRAIN CURRENT (AMPS)
TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance versus Drain Current
Figure 6. On–Resistance Variation
With Temperature
Motorola TMOS Power MOSFET Transistor Device Data
200
3
MTP5N40E
SAFE OPERATING AREA INFORMATION
14
VGS = 20 V
SINGLE PULSE
TC = 25°C
12
10 µs
10
0.1 ms
1 ms
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
10 ms
I D, DRAIN CURRENT (AMPS)
I D, DRAIN CURRENT (AMPS)
100
10
8
6
TJ ≤ 150°C
4
2
dc
0
10
100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
1
1000
0
100
200
300
400
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Maximum Rated Forward Biased
Safe Operating Area
500
Figure 8. Maximum Rated Switching
Safe Operating Area
FORWARD BIASED SAFE OPERATING AREA
10000
VDD = 250 V
ID = 5 A
VGS = 10 V
TJ = 25°C
1000
tf
tr
td(on)
100
10
1
SWITCHING SAFE OPERATING AREA
td(off)
t, TIME (ns)
The FBSOA curves define the maximum drain–to–source
voltage and drain current that a device can safely handle
when it is forward biased, or when it is on, or being turned on.
Because these curves include the limitations of simultaneous
high voltage and high current, up to the rating of the device,
they are especially useful to designers of linear systems. The
curves are based on a case temperature of 25°C and a maximum junction temperature of 150°C. Limitations for repetitive
pulses at various case temperatures can be determined by
using the thermal response curves. Motorola Application
Note, AN569, “Transient Thermal Resistance–General Data
and Its Use” provides detailed instructions.
1000
10
100
RG, GATE RESISTANCE (OHMS)
The switching safe operating area (SOA) of Figure 8 is the
boundary that the load line may traverse without incurring
damage to the MOSFET. The fundamental limits are the
peak current, IDM and the breakdown voltage, V(BR)DSS. The
switching SOA shown in Figure 8 is applicable for both turn–
on and turn–off of the devices for switching times less than
one microsecond.
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
D = 0.5
0.5
0.3
0.2
0.2
0.1
0.1
0.05
P(pk)
0.05
RθJC(t) = r(t) RθJC
RθJC = 1.67°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
0.02
t1
0.03
0.02
0.01
0.01
t2
DUTY CYCLE, D = t1/t2
0.01
SINGLE PULSE
0.02
0.05
0.1
0.2
0.5
1
2
5
t, TIME (ms)
10
20
50
100
200
500
1000
Figure 10. Thermal Response
4
Motorola TMOS Power MOSFET Transistor Device Data
MTP5N40E
2000
VGS, GATE SOURCE VOLTAGE (VOLTS)
16
TJ = 25°C
VGS = 0
C, CAPACITANCE (pF)
1500
1000
Crss
Ciss
500
VDS = 0 V
0
Coss
TJ = 25°C
ID = 5 A
VDS = 100 V
12
200 V
320 V
8
4
0
10
5
10
20
25
5
0
15
VGS
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
10
0
20
30
Qg, TOTAL GATE CHARGE (nC)
40
50
Figure 12. Gate Charge versus
Gate–To–Source Voltage
Figure 11. Capacitance Variation
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of
Figure 14 defines the limits of safe operation for commutated
source–drain current versus re–applied drain voltage when
the source–drain diode has undergone forward bias. The
curve shows the limitations of IFM and peak VDS for a given
rate of change of source current. It is applicable when waveforms similar to those of Figure 11 are present. Full or half–
bridge PWM DC motor controllers are common applications
requiring CSOA data.
Device stresses increase with increasing rate of change of
source current so dIs/dt is specified with a maximum value.
Higher values of dIs/dt require an appropriate derating of IFM,
peak VDS or both. Ultimately dIs/dt is limited primarily by device, package, and circuit impedances. Maximum device
stress occurs during trr as the diode goes from conduction to
reverse blocking.
VDS(pk) is the peak drain–to–source voltage that the device
must sustain during commutation; IFM is the maximum forward source–drain diode current just prior to the onset of
commutation.
VR is specified at 80% of V(BR)DSS to ensure that the
CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only
a second order effect on CSOA.
Stray inductances in Motorola’s test circuit are assumed to
be practical minimums. dVDS/dt in excess of 10 V/ns was attained with dIs/dt of 400 A/µs.
15 V
VGS
0
IFM
dls/dt
90%
IS
10%
trr
ton
IRM
0.25 IRM
VDS(pk)
VR
VDS
dVDS/dt
VdsL
Vf
MAX. CSOA
STRESS AREA
Figure 15. Commutating Waveforms
6
I D, DRAIN CURRENT (AMPS)
RGS
4
DUT
–
VR
+
di/dt ≤ 90 A/µs
2
IS
+
VGS
0
IFM
0
100
200
300
400
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
500
Figure 13. Commutating Safe Operating Area (CSOA)
Motorola TMOS Power MOSFET Transistor Device Data
Li
VDS
20 V
–
VR = 80% OF RATED VDS
VdsL = Vf + Li ⋅ dls/dt
Figure 14. Commutating Safe Operating Area
Test Circuit
5
MTP5N40E
V(BR)DSS
Vds(t)
IO
L
VDS
ID(t)
C
4700 µF
250 V
ID
VDD
VDD
t
WDSR
Figure 16. Unclamped Inductive Switching
Test Circuit
ǒ Ǔǒ
Ǔ
t, (TIME)
tP
RGS
50 Ω
+
1 LI 2
O
2
V(BR)DSS
V(BR)DSS – VDD
Figure 17. Unclamped Inductive Switching
Waveforms
RESISTIVE SWITCHING
VDD
ton
td(on)
RL
Vout
Vin
PULSE GENERATOR
Rgen
50 Ω
tf
90%
OUTPUT, Vout
INVERTED
10%
90%
50 Ω
INPUT, Vin
50%
50%
10%
PULSE WIDTH
* Note: The Mirror is shorted to the Kelvin terminal for this test.
Figure 18. Switching Test Circuit
Figure 19. Switching Waveforms
+18 V
VDD
1 mA
47 k
Vin
td(off)
tr
90%
DUT
z = 12 Ω
toff
10 V
15 V
SAME
DEVICE TYPE
AS DUT
100 k
2N3904
0.1 µF
2N3904
100 k
47 k
100
FERRITE
BEAD
DUT
Vin = 15 Vpk; PULSE WIDTH ≤ 100 µs, DUTY CYCLE ≤ 10%
Figure 20. Gate Charge Test Circuit
6
Motorola TMOS Power MOSFET Transistor Device Data
MTP5N40E
PACKAGE DIMENSIONS
–T–
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
SEATING
PLANE
C
F
T
S
4
A
Q
1 2 3
STYLE 5:
PIN 1.
2.
3.
4.
U
H
K
Z
L
R
V
J
G
D
N
GATE
DRAIN
SOURCE
DRAIN
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
–––
–––
0.080
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
–––
–––
2.04
CASE 221A–06
ISSUE Y
Motorola TMOS Power MOSFET Transistor Device Data
7
MTP5N40E
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8
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*MTP5N40E/D*
Motorola TMOS Power MOSFET Transistor
Device Data
MTP5N40E/D