MOTOROLA MTW6N100E

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SEMICONDUCTOR TECHNICAL DATA
 
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TMOS POWER FET
6.0 AMPERES
1000 VOLTS
RDS(on) = 1.5 OHM
N–Channel Enhancement–Mode Silicon Gate
This high voltage MOSFET uses an advanced termination
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
• Isolated Mounting Hole Reduces Mounting Hardware

D
G
CASE 340K–01, Style 1
TO–247AE
S
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
VDSS
1000
Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ)
VDGR
1000
Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 40
Vdc
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 µs)
ID
ID
IDM
6.0
4.2
18
Adc
Total Power Dissipation
Derate above 25°C
PD
180
1.43
Watts
W/°C
TJ, Tstg
– 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 27.77 mH, RG = 25 Ω)
EAS
720
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
RθJC
RθJA
0.70
40
°C/W
TL
260
°C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
Apk
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 3
TMOS
Motorola
Motorola, Inc.
1996 Power MOSFET Transistor Device Data
1
MTW6N100E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
1000
—
—
1,270
—
—
Vdc
mV/°C
—
—
—
—
10
100
—
—
100
nAdc
2.0
—
3.0
7.0
4.0
—
Vdc
mV/°C
—
1.28
1.5
Ohm
—
—
8.0
—
14.4
12.6
gFS
4.0
7.2
—
mhos
Ciss
—
3000
4210
pF
Coss
—
219
440
Crss
—
43
90
td(on)
—
27
45
tr
—
29
65
td(off)
—
93
170
tf
—
43
95
QT
—
66
100
Q1
—
12.5
—
Q2
—
25.9
—
Q3
—
26
—
—
—
0.808
0.64
1.0
—
trr
—
735
—
ta
—
188
—
tb
—
547
—
QRR
—
4.7
—
µC
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
LD
—
4.5
—
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
LS
—
13
—
nH
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 1000 Vdc, VGS = 0 Vdc)
(VDS = 1000 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
µAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
VGS(th)
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 3.0 Adc)
RDS(on)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 6.0 Adc)
(ID = 3.0 Adc, TJ = 125°C)
VDS(on)
Forward Transconductance (VDS = 10 Vdc, ID = 3.0 Adc)
Vdc
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc,
Vdc VGS = 0 Vdc,
Vdc
f = 1.0 MHz)
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
(VDD = 500 Vdc,
Vd ID = 6
6.0
0 Ad
Adc,
VGS = 10 Vdc
Vdc,
RG = 9
9.1 Ω))
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
Vd ID = 6
0 Ad
(VDS = 800 Vdc,
6.0
Adc,
VGS = 10 Vdc)
ns
nC
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 6.0 Adc, VGS = 0 Vdc)
(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(See Figure
Fig re 14)
((IS = 6.0
6 0 Adc,
Ad , VGS = 0 Vdc,
Vd ,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
VSD
Vdc
ns
INTERNAL PACKAGE INDUCTANCE
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
2
Motorola TMOS Power MOSFET Transistor Device Data
MTW6N100E
TYPICAL ELECTRICAL CHARACTERISTICS
12
12
VGS = 10 V
VDS ≥ 10 V
6V
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
TJ = 25°C
10
5V
8
6
4
100°C
8
6
25°C
4
2
2
0
10
TJ = –55°C
4V
0
2
4
6
8
10
12
14
16
18
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
0
2.0
20
2.4
2.9
TJ = 100°C
2.5
2.1
1.7
25°C
1.3
0.9
– 55°C
0.5
0
4
6
8
ID, DRAIN CURRENT (AMPS)
2
10
12
4.4
4.8
5.2
TJ = 25°C
1.52
1.48
1.44
1.40
VGS = 10 V
1.36
15 V
1.32
1.28
1.24
0
1
2
3
4
5
6
7
8
9
ID, DRAIN CURRENT (AMPS)
10
11
12
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
VGS = 0 V
VGS = 10 V
ID = 3 A
TJ = 125°C
10000
I DSS , LEAKAGE (nA)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
4.0
100000
2.8
2.0
1.6
1.2
100°C
1000
100
25°C
10
0.8
0.4
–50
3.6
1.56
Figure 3. On–Resistance versus Drain Current
and Temperature
2.4
3.2
Figure 2. Transfer Characteristics
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
Figure 1. On–Region Characteristics
VGS = 10 V
2.8
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
1
–25
0
25
50
75
100
TJ, JUNCTION TEMPERATURE (°C)
125
Figure 5. On–Resistance Variation with
Temperature
Motorola TMOS Power MOSFET Transistor Device Data
150
0
100
200 300 400 500 600 700 800 900 1000
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
3
MTW6N100E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
t = Q/IG(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
10000
C, CAPACITANCE (pF)
6000
VDS = 0 V
Ciss
VGS = 0 V
TJ = 25°C
VGS = 0 V
C, CAPACITANCE (pF)
7000
5000
4000
Crss
Ciss
3000
2000
1000
0
5
VGS
5
10
Coss
100
Crss
15
20
25
VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7a. Capacitance Variation
4
TJ = 25°C
1000
Coss
Crss
0
10
Ciss
10
10
100
1000
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance
Variation
Motorola TMOS Power MOSFET Transistor Device Data
400
ID = 6 A
TJ = 25°C
14
12
350
300
QT
250
10
8
200
VGS
Q1
6
Q2
150
100
4
2
0
0
10
50
VDS
Q3
20
30
40
50
60
70
0
1000
VDD = 480 V
ID = 6 A
VGS = 10 V
TJ = 25°C
t, TIME (ns)
16
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
MTW6N100E
100
td(off)
tf
td(on)
tr
10
1
10
QG, TOTAL GATE CHARGE (nC)
100
RG, GATE RESISTANCE (OHMS)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
I S , SOURCE CURRENT (AMPS)
6
VGS = 0 V
TJ = 25°C
5
4
3
2
1
0
0.50
0.54
0.58
0.62
0.66
0.70
0.74
0.78
0.82
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed
(TJ(MAX) – TC)/(RθJC).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
Motorola TMOS Power MOSFET Transistor Device Data
able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a constant. The energy rating decreases non–linearly with an increase of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.
5
MTW6N100E
SAFE OPERATING AREA
10
VGS = 20 V
SINGLE PULSE
TC = 25°C
EAS, SINGLE PULSE DRAIN–TO–SOURCE
AVALANCHE ENERGY (mJ)
I D , DRAIN CURRENT (AMPS)
100
10 µs
100 µs
1.0
1 ms
10 ms
0.1
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1
1.0
700
500
400
300
200
100
0
25
1000
100
10
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
ID = 6 A
600
50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1.0
D = 0.5
0.2
0.1
P(pk)
0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
1.0E–05
t1
t2
DUTY CYCLE, D = t1/t2
1.0E–04
1.0E–03
1.0E–02
1.0E–01
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) – TC = P(pk) RθJC(t)
1.0E+00
1.0E+01
t, TIME (s)
Figure 13. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 14. Diode Reverse Recovery Waveform
6
Motorola TMOS Power MOSFET Transistor Device Data
MTW6N100E
PACKAGE DIMENSIONS
0.25 (0.010)
M
–T–
–Q–
T B M
E
–B–
C
4
L
U
A
R
1
K
2
3
–Y–
P
V
H
F
D
0.25 (0.010)
M
Y Q
J
G
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
DIM
A
B
C
D
E
F
G
H
J
K
L
P
Q
R
U
V
MILLIMETERS
MIN
MAX
19.7
20.3
15.3
15.9
4.7
5.3
1.0
1.4
1.27 REF
2.0
2.4
5.5 BSC
2.2
2.6
0.4
0.8
14.2
14.8
5.5 NOM
3.7
4.3
3.55
3.65
5.0 NOM
5.5 BSC
3.0
3.4
INCHES
MIN
MAX
0.776
0.799
0.602
0.626
0.185
0.209
0.039
0.055
0.050 REF
0.079
0.094
0.216 BSC
0.087
0.102
0.016
0.031
0.559
0.583
0.217 NOM
0.146
0.169
0.140
0.144
0.197 NOM
0.217 BSC
0.118
0.134
S
STYLE 1:
PIN 1.
2.
3.
4.
GATE
DRAIN
SOURCE
DRAIN
CASE 340K–01
ISSUE O
Motorola TMOS Power MOSFET Transistor Device Data
7
MTW6N100E
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8
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*MTW6N100E/D*
Motorola TMOS Power MOSFET TransistorMTW6N100E/D
Device Data