FAIRCHILD NDS9953A

February 1996
NDS9953A
Dual P-Channel Enhancement Mode Field Effect Transistor
General Description
Features
These P-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance,
provide superior switching performance, and withstand high
energy pulses in the avalanche and commutation modes.
These devices are particularly suited for low voltage
applications such as notebook computer power management
and other battery powered circuits where fast switching, low
in-line power loss, and resistance to transients are needed.
-2.9A, -30V. RDS(ON) = 0.13Ω @ VGS = -10V.
High density cell design for extremely low RDS(ON).
High power and current handling capability in a widely used
surface mount package.
Dual MOSFET in surface mount package.
________________________________________________________________________________
Absolute Maximum Ratings
4
6
3
7
2
8
1
T A= 25°C unless otherwise noted
Symbol
Parameter
VDSS
VGSS
ID
Drain Current - Continuous
PD
Power Dissipation for Dual Operation
NDS9953A
Units
Drain-Source Voltage
-30
V
Gate-Source Voltage
± 20
V
± 2.9
A
(Note 1a)
- Pulsed
Power Dissipation for Single Operation
± 10
2
(Note 1a)
1.6
(Note 1b)
1
(Note 1c)
TJ,TSTG
5
Operating and Storage Temperature Range
W
0.9
-55 to 150
°C
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
(Note 1a)
78
°C/W
RθJC
Thermal Resistance, Junction-to-Case
(Note 1)
40
°C/W
© 1997 Fairchild Semiconductor Corporation
NDS9953A.SAM
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
-30
Typ
Max
Units
-2
µA
OFF CHARACTERISTICS
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = -250 µA
IDSS
Zero Gate Voltage Drain Current
VDS = -24 V, VGS = 0 V
V
-25
µA
IGSSF
Gate - Body Leakage, Forward
VGS = 20 V, VDS = 0 V
100
nA
IGSSR
Gate - Body Leakage, Reverse
VGS = -20 V, VDS= 0 V
-100
nA
V
TJ = 55°C
ON CHARACTERISTICS (Note 2)
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = -250 µA
TJ = 125°C
RDS(ON)
Static Drain-Source On-Resistance
-1
-1.6
-2.8
-0.85
-1.25
-2.5
0.11
0.13
0.15
0.21
VGS = -10 V, ID = -1.0 A
TJ = 125°C
VGS = -4.5 V, ID = -0.5 A
TJ = 125°C
ID(on)
gFS
On-State Drain Current
Forward Transconductance
VGS = -10 V, VDS = -5 V
-10
VGS = -4.5 V, VDS = -5 V
-1.5
0.17
0.2
0.24
0.32
Ω
A
VDS = -15 V, ID = -2.9 A
4
S
VDS = -10 V, VGS = 0 V,
f = 1.0 MHz
350
pF
260
pF
100
pF
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
tD(on)
Turn - On Delay Time
tr
Turn - On Rise Time
tD(off)
Turn - Off Delay Time
tf
Turn - Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = -10 V, ID = -1 A,
VGEN = -10 V, RGEN = 6 Ω
VDS = -10 V,
ID = -2.9 A, VGS = -10 V
9
40
ns
21
40
ns
21
90
ns
8
50
ns
10
25
nC
1.6
nC
3.4
nC
NDS9953A.SAM
Electrical Characteristics (TA = 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
-1.2
A
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS
Maximum Continuous Drain-Source Diode Forward Current
VSD
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = -1.25 A
trr
Reverse Recovery Time
VGS = 0 V, IF = -1.25 A, dIF/dt = 100 A/µs
-0.8
(Note 2)
-1.3
V
100
ns
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by
design while RθCA is determined by the user's board design.
PD (t ) =
TJ
−TA
R θJ A(t )
=
TJ
−TA
R θJ C+RθCA(t )
= I 2D (t ) × RDS(ON )
TJ
Typical RθJA for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment:
a. 78oC/W when mounted on a 0.5 in2 pad of 2oz cpper.
b. 125oC/W when mounted on a 0.02 in2 pad of 2oz cpper.
c. 135oC/W when mounted on a 0.003 in2 pad of 2oz cpper.
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
NDS9953A.SAM
Typical Electrical Characteristics
-20
3
-8.0
-7.0
R DS(on) , NORMALIZED
-6.0
-15
-5.5
-5.0
-10
-4.5
-4.0
-5
D
-3.5
I
-3.0
0
0
-1
V
DS
-2
-3
, DRAIN-SOURCE VOLTAGE (V)
-4
DRAIN-SOURCE ON-RESISTANCE
, DRAIN-SOURCE CURRENT (A)
VGS = -10V
R DS(on), NORMALIZED
1
0.8
-25
0
25
50
75
100
TJ , JUNCTION TEMPERATURE (°C)
125
DRAIN-SOURCE ON-RESISTANCE
R DS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
V G S = -10V
-5.5
-6.0
1.5
-7.0
-8.0
-10
1
0
-3
-6
-9
I D , DRAIN CURRENT (A)
-12
-15
V GS = -10V
TJ = 125°C
1.5
25°C
1
-55°C
0.5
150
Figure 3. On-Resistance Variation with
Temperature.
0
-3
-6
-9
I D , DRAIN CURRENT (A)
-12
-15
Figure 4. On-Resistance Variation with Drain
Current and Temperature.
1.2
V DS = -10V
TJ = -55°C
25°C
125°C
V th , NORMALIZED
-8
-6
-4
-2
-1
-2
-3
-4
-5
V GS , GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics.
-6
GATE-SOURCE THRESHOLD VOLTAGE
-10
ID , DRAIN CURRENT (A)
-5.0
2
I D = -2.9A
1.2
0
-4.5
Figure 2. On-Resistance Variation with Gate
Voltage and Drain Current.
1.6
0.6
-50
-4.0
2
0.5
-5
Figure 1. On-Region Characteristics.
1.4
VGS = -3.5V
2.5
VDS = V GS
1.1
I D = -250µA
1
0.9
0.8
0.7
-50
-25
0
25
50
75
100
TJ , JUNCTION TEMPERATURE (°C)
125
150
Figure 6. Gate Threshold Variation with
Temperature.
NDS9953A.SAM
Typical Electrical Characteristics (continued)
10
I D = -250µA
5
1.08
-I S , REVERSE DRAIN CURRENT (A)
BV DSS , NORMALIZED
DRAIN-SOURCE BREAKDOWN VOLTAGE
1.1
1.06
1.04
1.02
1
0.98
0.96
0.94
-50
-25
0
25
50
75
100
TJ , JUNCTION TEMPERATURE (°C)
125
150
1
0.5
T = 125°C
J
25°C
-55°C
0.1
0.01
0.001
0.2
Figure 7. Breakdown Voltage Variation with
Temperature.
0.4
0.6
0.8
1
1.2
-VSD , BODY DIODE FORWARD VOLTAGE (V)
1.4
Figure 8. Body Diode Forward Voltage
Variation with Current and Temperature.
1000
10
-V GS , GATE-SOURCE VOLTAGE (V)
800
500
C iss
CAPACITANCE (pF)
V GS = 0V
300
C oss
200
f = 1 MHz
100
C rss
V GS = 0V
50
0.1
0.2
0.5
1
2
5
10
-VDS , DRAIN TO SOURCE VOLTAGE (V)
30
I D = -2.9A
V DS = -10V
-20V
8
-15V
6
4
2
0
0
2
4
6
8
Q g , GATE CHARGE (nC)
10
12
Figure 10. Gate Charge Characteristic.
Figure 9. Capacitance Characteristics.
6
TJ = -55°C
25°C
4
125°C
3
2
1
g
FS
, TRANSCONDUCTANCE (SIEMENS)
V DS = -15V
5
0
0
-2
ID
-4
-6
, DRAIN CURRENT (A)
-8
-10
Figure 11. Transconductance Variation with Drain
Current and Temperature.
NDS9953A.SAM
Typical Thermal Characteristics
5
I D , STEADY-STATE DRAIN CURRENT (A)
STEADY-STATE POWER DISSIPATION (W)
2.5
Total Power for Dual Operation
2
1a
Power for Single Operation
1.5
1b
1
1c
4.5"x5" FR-4 Board
TA = 25 o C
Still Air
0.5
0
0.2
0.4
0.6
0.8
2oz COPPER MOUNTING PAD AREA (in 2 )
1
30
10
-I D , DRAIN CURRENT (A)
3
RD
S(O
N)
LI
1m
T
MI
10
10
1
1a
1b
2
1c
4.5"x5" FR-4 Board
TA = 2 5 o C
Still Air
1
VG S = - 1 0 V
0
0.1
0.2
0.3
0.4
2oz COPPER MOUNTING PAD AREA (in 2 )
0.5
0u
s
s
ms
s
1s
10
s
DC
0.3
V GS = -10V
0.1
0m
3
Figure 13. Maximum Steady-State Drain
Current versus Copper Mounting Pad
Area.
Figure 12. SO-8 Dual Package Maximum
Steady-State Power Dissipation versus
Copper Mounting Pad Area.
10
4
SINGLE PULSE
R
0.03
θJ A
= See Note 1c
T A = 25°C
0.01
0.1
0.2
0.5
1
2
5
10
- V DS , DRAIN-SOURCE VOLTAGE (V)
30
50
Figure 14. Maximum Safe Operating Area.
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
1
0.5
D = 0.5
0.2
0.2
0.1
0.05
0.02
0.01
R θJA (t) = r(t) * R θJA
R JA = See Note 1c
θ
0.1
0.05
P(pk)
0.02
0.01
t1
Single Pulse
0.005
0.002
0.001
0.0001
t2
TJ - TA = P * R JA (t)
θ
Duty Cycle, D = t 1 / t 2
0.001
0.01
0.1
1
10
100
300
t1 , TIME (sec)
Figure 15. Transient Thermal Response Curve.
Note:
Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change
depending on the circuit board design.
NDS9953A.SAM
SO-8 Tape and Reel Data and Package Dimensions
SOIC(8lds) Packaging
Configuration: Figure 1.0
Packaging Description:
EL ECT ROST AT IC
SEN SIT IVE DEVICES
DO NO T SHI P OR STO RE N EAR ST RO NG EL ECT ROST AT IC
EL ECT RO M AGN ETI C, M AG NET IC O R R ADIO ACT IVE FI ELD S
TNR D ATE
PT NUMB ER
PEEL STREN GTH MIN ___ __ ____ __ ___gms
MAX ___ ___ ___ ___ _ gms
Antistatic Cover Tape
ESD Label
SOIC-8 parts are shipped in tape. The carrier tape is
made from a dissipative (carbon filled) polycarbonate
resin. The cover tape is a multilayer film (Heat Activated
Adhesive in nature) primarily composed of polyester film,
adhesive layer, sealant, and anti-static sprayed agent.
These reeled parts in standard option are shipped with
2,500 units per 13" or 330cm diameter reel. The reels are
dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 500 units per 7" or
177cm diameter reel. This and some other options are
further described in the Packaging Information table.
These full reels are individually barcode labeled and
placed inside a standard intermediate box (illustrated in
figure 1.0) made of recyclable corrugated brown paper.
One box contains two reels maximum. And these boxes
are placed inside a barcode labeled shipping box which
comes in different sizes depending on the number of parts
shipped.
Static Dissipative
Embossed Carrier Tape
F63TNR
Label
Customized
Label
F852
NDS
9959
F852
NDS
9959
F852
NDS
9959
F852
NDS
9959
F852
NDS
9959
Pin 1
SOIC (8lds) Packaging Information
Packaging Option
Packaging type
Qty per Reel/Tube/Bag
Standard
(no flow code)
TNR
2,500
L86Z
F011
D84Z
Rail/Tube
TNR
TNR
95
4,000
500
13" Dia
-
13" Dia
7" Dia
343x64x343
530x130x83
343x64x343
184x187x47
Max qty per Box
5,000
30,000
8,000
1,000
Weight per unit (gm)
0.0774
0.0774
0.0774
0.0774
Weight per Reel (kg)
0.6060
-
0.9696
0.1182
Reel Size
Box Dimension (mm)
SOIC-8 Unit Orientation
Note/Comments
343mm x 342mm x 64mm
Standard Intermediate box
ESD Label
F63TNR Label sample
F63TNLabel
F63TN Label
LOT: CBVK741B019
QTY: 2500
FSID: FDS9953A
SPEC:
D/C1: D9842
D/C2:
QTY1:
QTY2:
SPEC REV:
CPN:
N/F: F
ESD Label
(F63TNR)3
SOIC(8lds) Tape Leader and Trailer
Configuration: Figure 2.0
Carrier Tape
Cover Tape
Components
Trailer Tape
640mm minimum or
80 empty pockets
Leader Tape
1680mm minimum or
210 empty pockets
July 1999, Rev. B
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC(8lds) Embossed Carrier Tape
Configuration: Figure 3.0
P0
D0
T
E1
F
K0
Wc
W
E2
B0
Tc
A0
D1
P1
User Direction of Feed
Dimensions are in millimeter
Pkg type
A0
B0
SOIC(8lds)
(12mm)
6.50
+/-0.10
5.30
+/-0.10
W
12.0
+/-0.3
D0
D1
E1
E2
1.55
+/-0.05
1.60
+/-0.10
1.75
+/-0.10
F
10.25
min
5.50
+/-0.05
P1
P0
8.0
+/-0.1
4.0
+/-0.1
K0
2.1
+/-0.10
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481
rotational and lateral movement requirements (see sketches A, B, and C).
T
Wc
0.450
+/0.150
9.2
+/-0.3
0.06
+/-0.02
0.5mm
maximum
20 deg maximum
Typical
component
cavity
center line
B0
Tc
0.5mm
maximum
20 deg maximum component rotation
Typical
component
center line
Sketch A (Side or Front Sectional View)
A0
Component Rotation
Sketch C (Top View)
Component lateral movement
Sketch B (Top View)
SOIC(8lds) Reel Configuration: Figure 4.0
Component Rotation
W1 Measured at Hub
Dim A
Max
Dim A
max
See detail AA
Dim N
7" Diameter Option
B Min
Dim C
See detail AA
W3
13" Diameter Option
Dim D
min
W2 max Measured at Hub
DETAIL AA
Dimensions are in inches and millimeters
Tape Size
Reel
Option
Dim A
Dim B
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
2.165
55
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.469 – 0.606
11.9 – 15.4
0.059
1.5
512 +0.020/-0.008
13 +0.5/-0.2
0.795
20.2
7.00
178
0.488 +0.078/-0.000
12.4 +2/0
0.724
18.4
0.469 – 0.606
11.9 – 15.4
12mm
7" Dia
7.00
177.8
12mm
13" Dia
13.00
330
 1998 Fairchild Semiconductor Corporation
Dim C
Dim D
Dim N
Dim W1
Dim W2
Dim W3 (LSL-USL)
July 1999, Rev. B
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC-8 (FS PKG Code S1)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in:
inches [millimeters]
Part Weight per unit (gram): 0.0774
9
September 1998, Rev. A
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effectiveness.
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. E