MITSUBISHI <DIGITAL ASSP> ARY N I M I REL M66013FP tion. ange. ifica h spec t to c l c a n je fi ub not a s are s is it is h m tric li ce: T Noti parame e Som P 8-BIT I/O EXPANDER WITH ADDRESS DESCRIPTION FEATURES • Is capable of providing high speed serial communication at 8 MHz. • Provides two modes: echo back mode and normal mode. ADDRESS SET INPUT BLOCK DIAGRAM A0 A1 5 6 DATA ENABLE INPUT EN 4 CLOCK INPUT CLK 1 A2 A3 7 8 PIN CONFIGURATION (TOP VIEW) 1 20 VCC 2 19 3 18 RESET RESET INPUT D7 4 17 D6 16 D5 15 D4 14 D3 8 13 D2 9 12 D1 GND 10 11 D0 CLOCK INPUT CLK SERIAL DATA DI INPUT SERIAL DATA DO OUTPUT DATA ENABLE INPUT EN A0 ADDRESS SET A1 INPUT A2 ADDRESS SET/OUTPUT A3 SET INPUT /PNSET MODE SET INPUT MD 5 6 7 M66013FP The M66013FP is a semiconductor IC that is capable of performing serial-parallel conversion of data. This IC can set addresses. The microcomputer uses the four signal lines of EN, CLK, DI and DO to send and receive data. The IC adopts the two types of operation modes: echo-back mode and normal mode. In the echo-back mode, data received in serial can be sent to the sender within the same sequence (*1) as it is. In the normal mode, restriction is given to the data to be sent to the sender. However, the normal mode supports the same communication protocol as that of the M66009FP. (*1): one of the higher order command bits is excluded. Three bits in the echo-back mode and four bits in the normal mode are available for addresses. The echo-back mode and the normal mode have 8 types and 16 types of address, respectively, and any address can be set. Receiving serial data from the microcomputer, the M66013 compares address data included in the data with an address entered in address setting. Only when these addresses match each other, a specified command provided are to be executed. For serial input-parallel output operation, low order 8 bits of the received 16 bit serial data is converted to parallel data to output to pins D0 to D7. High order 8 bits are handled as address or command bits. Since the writing operation to the data register for parallel output and the outputting operation of register contents to pins D0 to D7 are performed with different commands and can be controlled independently, the register contents must be checked before output of the specified data to pins D0 to D7. For parallel input-serial output operation, parallel data of pins D0 to D7 are outputted to low order 8 bits of the sended 16 bit serial data. The contents of high order 8 bits of the sended 16 bit serial data differs in the using operation mode. In echo mode, the I/O port output format is capable of setting to either N-ch or P-ch open drain. In normal mode, the I/O port output format is fixed to P-ch open drain. PARALLEL DATA INPUT/OUTPUT Outline 20P2N-A (20 pin SOP) • Is capable of reading serial input data in echo back mode. (However, 3 bits are available for the address.) • Is capable of achieving communication protocol of current M66009FP in the normal mode. (However, 4 bits are available for the address.) • Uses different commands in operations for output of data to I/O port: command for writing data into an output register and command for output operation to the I/O port. • Provides an I/O port data read only command. • Is capable of reading an output register. • Adopts a decision by majority by reading three types of data when serial data is received. • Is capable of setting the I/O port output format to either N-ch or Pch open drain. (In echo mode) APPLICATIONS Inter board communication in VTR, AV and OA equipment, expansion of microcomputer I/O port, etc. MODE SET INPUT MD 9 ACK BIT, OUTPUT SET FLAG COMMAND CONTROL CIRCUIT 16 SERIAL DATA INPUT DI SHIFT REGISTER FOR SERIAL INPUT (16 bits) 2 11 D0 16 SELECTOR 12 D1 13 D2 DATA REGISTER FOR PARALLEL OUTPUT (16 bits) 14 D3 8 SERIAL DATA DO OUTPUT RESET INPUT 3 RESET 19 15 D4 SHIFT REGISTER FOR SERIAL OUTPUT (16 bits) PARALLEL DATA INPUT/OUTPUT 16 D5 17 D6 VCC 20 8 18 D7 GND 10 1 MITSUBISHI <DIGITAL ASSP> ARY N I M I REL M66013FP tion. ange. ifica h spec t to c l c a n je fi ub not a s are s is it is h m tric li ce: T Noti parame e Som P 8-BIT I/O EXPANDER WITH ADDRESS BASIC PROTOCOL FOR SENDING AND RECEIVING DATA The following diagram shows the basic protocol for sending and receiving data between the microcomputer and the M66013. Falling of EN from "H" to "L" starts a series of sequence and rising of EN from "L" to "H" terminates the sequence. The concrete operation sequence is as follows: (1) At a falling edge of EN, 8-bit parallel data of I/O pins D0 to D7 are loaded into the shift register for serial output. (2) At a rising edge of CLK, DI pin input data is read into the shift register for serial input and the counter for CLK counts up. (3) When all address bits are read, a received address is compared with an address set in the address set pin to start the specified operation only when these addresses matches each other. The DO pin is kept in a high impedance status until the address comparison is complete. When these addresses do not match, the DO pin keeps the high impedance status until the next sequence. (4) When the addresses match each other, the operation for reading serial data from the DI pin and the operation for output serial data from the D0 pin in synchronization with a falling edge of CLK is carried out. (5) When 16-bit data has been completely sent or received, the following operations are carried out in synchronization with a rising edge of EN. (a)The DO output pin is placed in a high impedance status. (b)When the CLK counter does not count 16 CLK rising edges, operation (c) below is skipped and the counter is reset to wait for the next access. (c)When the counter value is 16, operation for writing to the data register for parallel output, operation for output to the I/O port or operation for setting/resetting the data setting flag is carried out, and the counter is then reset to wait for the next address. EN 1T 2T 3T 4T 5T 6T 7T 8T 9T C2 C1 C0 DI7 10T 11T 12T 13T 14T 15T 16T DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO2 DO1 CLK In the normal mode DI X A3 A2 A1 A0 Arbitrary Address bit Command bit ACK DO Data bit DO7 DO6 DO5 DO4 DO3 DO0 "Z" "Z" (High impedance status) Data bit Acknowledge bit 1T 2T 3T 4T 5T 6T 7T 8T C2 C1 C0 X X A2 A1 A0 C1 C0 9T 10T 11T 12T 13T 14T 15T 16T DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO7 DO6 DO5 DO4 DO3 DO2 DO1 CLK In the echo back mode DI DO A2 A1 "Z" A0 "Z" Basic Protocol (The actual protocol differs depending on the command.) 2 DO0