NEC UPD7228

DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16434
1/8, 1/16 DUTY LCD CONTROLLER/DRIVER
DESCRIPTION
µ PD16434 is LCD controller/driver containing the interfacing features for a dot-matrix mode 8-, 16-time division
LCD and a microprocessor. µ PD16434 contains a 5- by 7-dot matrix character generator corresponding to
ASCII/JIS. Therefore, user original patterns can be easily displayed.
FEATURES
• DOT matrix LCD controller/driver
• 8- or 16-time division drive possible with a single chip
8-time-division : 400 (50 by 8) dots
16-time-division : 672 (42 by 16) dots
• 8- or 16-time division drive possible with no chip
8-time-division : n × 400 (50 by 8) dots
16-time-division : n × 800 (50 by 16) dots
• Display data storage RAM : 20 × 50 × 8 bits
• Programmer specified dot (graphic) display
• Capable of alphanumeric and symbolic displays thorough built-in ROM (5 by 7 dots)
160 characters
• Parallel data input/output (Switch able between 4 and 8 bits)
• Cursor manipulation command
• Upgraded version of µ PD7228, µ PD7228A, µ PD7229, µ PD7229A
ORDERING INFORMATION
Part Number
Package
µ PD16434G-xxx-12
80-PIN PLASTIC QFP (14 × 20)
µ PD16434G-001-12
80-PIN PLASTIC QFP (14 × 20), Standard ROM code
★
µ PD16434GF-xxx-3B9
80-PIN PLASTIC QFP (14 × 20)
★
µ PD16434GF-001-3B9
80-PIN PLASTIC QFP (14 × 20), Standard ROM code
Note
Note
Note This package is only available in European market.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S10299EJ4V0DS00 (4th edition)
Date Published April 2000 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
1994, 1999
µ PD16434
PIN CONFIGURATION (Top View)
µ PD16434G-xxx-12
80-PIN PLASTIC QFP (14 × 20)
µ PD16434GF-xxx-3B9 80-PIN PLASTIC QFP (14 × 20)
C37
C36
C35
C34
C33
C32
C31
C30
C29
C28
C27
C26
C25
C24
C23
C22
★
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1
64
63
2
62
3
61
4
5
60
6
59
58
7
57
8
9
56
55
10
11
54
53
12
52
13
51
14
50
15
49
16
48
17
47
18
46
19
45
20
44
21
43
22
42
23
41
24
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VLC2
VLC3
D0/SI
D1(P, /S)
D2(CAE)
D3/SO
SYNC
/BUSY
VDD
VSS
/STB, /SCK
C, /D
CA0
CA1
/CS
RESET
C38
C39
C40
C41
C42/R15
C43/R14
C44/R13
C45/R12
C46/R11
C47/R10
C48/R9
C49/R8
R15/R7
R14/R6
R13/R5
R12/R4
R11/R3
R10/R2
R9/R1
R8/R0
VLC5
VLC1
NC
VLC4
Remark /xxx indicates active low signal.
2
Data Sheet S10299EJ4V0DS00
C21
C20
C19
C18
C17
C16
C15
C14
C13
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
NC
CLOCK
R8/C49 to R15/C42
C0 to C41
8
8
42
ROW DRIVER
ROW/COLUMN
DRIVER
COLUMN DRIVER
R-S
R-NS
16
16
C-S
C-NS
16
8
VDD
R-S
Data Sheet S10299EJ4V0DS00
VLC1
VLC2
50
DATA MEMORY
DATA MEMORY
BANK 0
(50 x 8 BITS)
16
R-NS
VOLTAGE
BANK 1
8
(50 x 8 BITS)
C-S
VLC3
VLC4
42
50
LCD
BLOCK DIAGRAM
R0/R8 to R7/R15
CONTROL
C-NS
DATA
POINTER
VLC5
COMMAND
DECODER
VSS
LCD TIMING
8
16
SYNC
CHARACTER
GENERATOR
(160 x 5 x 7 BITS)
7
8
8
CONTROL
8
STOP
SERIAL/PARALLEL INTERFACE
D0/SI
D1(P, /S)
D2(CAE)
D3/SO
/STB, /SCK
/BUSY
C, /D
CA0
CA1
/CS
RESET
µ PD16434
CLOCK
CLOCK
BUFFER
SYSTEM
CLOCK
CONTROL
3
µ PD16434
TABLE OF CONTENTS
1. PIN FUNCTIONS ……………………………………………………………………………………………… 6
1.1 D0 to D3 (Data Bus) … 3-state input/output ……………………………………………….…………………..... 6
1.2 SI (Serial Data In) … Also serves as D0 input ……………………………………………………….………..… 6
1.3 SO (Serial Data Out) … Also serves as D3 output ………………………………….……………….…………. 6
1.4 P, /S (Parallel/Serial Select) … Also serves as D1 input ……………………………………………………… 6
1.5 CAE (Chip Address Enable) … Also serves as D2 input ……………………………………………………… 6
1.6 CA0, CA1 (Chip Address) … Input ………………………………………………………………………………… 6
1.7 /CS (Chip Select) … Input …………………………………………………………………………………………... 7
1.8 /STB, /SCK (Strobe/Serial Clock) … Input .……………………………………………………….……………… 7
1.9 C, /D (Command/Data) … Input ………………………………………………………………….………………… 7
1.10 /BUSY (Busy) … 3-state output …………………………………………………………………………………..
7
1.11 SYNC (Synchronous) … 3-state input/output …………………………………………………………………. 8
1.12 C0 to C41 (Column) … Output …………………………………………..………………………………………..
9
1.13 R8/C49 to R15/C42 (Row/Column) … Output ..…………………………………………...……………………. 9
1.14 R0/R8 to R7/R15 (Row) … Output .………………………….……………………………………………………. 9
1.15 VLC1 to VLC5 (LCD Drive Voltage Supply) … Input ……………….…………………………….……………… 9
1.16 CLOCK (Clock) … Input ……………………………………………………………………………………………
9
1.17 RESET (Reset) … Input ………………………………………………………………….………………………… 9
1.18 VDD ……………………………………………………………………………………………………….….……….… 9
1.19 VSS …………………………………………………………………………………………………………..……….… 9
2. INTERNAL BLOCK FUNCTIONS …………………………………………………………………………..
10
2.1 Serial/Parallel Interface ……………………………………………………………………………………………... 10
2.2 Command Decoder ………………………………………………………………………………………………….. 11
2.3 Character Generator …………………………………………………………………………………………………
11
2.4 Data Pointer …………………………………………………………………………………………………………… 14
2.5 Data Memory ………………………………………………………………………………………………………….. 15
2.6 LCD Voltage Control Circuit ………………………………………………………………………………………..
19
2.7 LCD Timing Control Circuit ………………………………………………………………………………………… 19
2.8 Row/Column Driver ………………………………………………………………………………………………….. 19
3. DATA INPUT/OUTPUT OPERATION ……………………………………………………………………… 21
4. SELECTING µ PD16434 INTERFACE FUNCTION WITH CPU ………………………………………… 27
4.1 Functions of Shared Pins …………………………………………………………………………………………… 27
4.2 Chip Address Selection Function ………………………………………………………………….……………… 28
5. LCD DRIVE REFERENCE VOLTAGE SUPPLY ………………………………………………………….. 29
5.1 Supplying LCD Drive Reference Voltage by Resistor Network ……………………………………………… 29
5.2 Reduction in Current Consumption by RESET Signal ………………………………………………………… 30
6. DISPLAY EXAMPLES ……………………………………………………………………………………….. 31
7. STANDBY MODE …………………………………………………………………………………………….. 35
7.1 Clearing Standby Mode ……………………………………………………………………………………………..
4
Data Sheet S10299EJ4V0DS00
35
µ PD16434
7.2 Stopping Clock Supply and Retaining Data at Low Voltage in Standby Mode ………………………. 36
8. RESET OPERATION …………………………………………………………………………………….. 38
9. COMMANDS ……………………………………………………………………………………………… 40
9.1 LCD Display Mode Setting Commands ……………………………………………………………………...
40
9.2 Data Pointer Load Command ………………………………………………………………………………….
42
9.3 Data Processing Mode Setting Commands ………………………………………………………………… 42
9.4 Memory Bit Manipulation Commands ……………………………………………………………………….. 45
9.5 Standby Operation Setting Command ………………………………………………………………………. 47
10. SYSTEM CONFIGURATION EXAMPLE …………………………………………………………….. 48
11. ELECTRICAL SPECIFICATION ………………………………………………………………………. 49
12. PACKAGE DRAWINGS ………………………………………………………………………………... 60
13. RECOMMENDED SOLDERING CONDITIONS ……………………………………………………..
Data Sheet S10299EJ4V0DS00
62
5
µ PD16434
1. PIN FUNCTIONS
1.1 D0 to D3 (Data Bus) … 3-state input/output
In the parallel interface mode, these pins serve as 4-bit parallel data input/output pins.
Data on the D0 to D3 lines is read at the /STB signal rising edge. The 4-bit data, read at the first rising edge of the
/STB, is loaded into the upper 4 bits of the serial/parallel register, and the data read at the second rising edge is loaded
into the lower 4 bits of the register.
The serial/parallel register contents are output to the D0 to D3 pins in synchronization with the /STB signal falling
edge. In the same manner as read operation, the upper 4 bits of the serial/parallel register are output in the first /STB
signal falling edge, and the lower 4bits are output in the second /STB falling edge.
In the serial interface mode, the D0 serves as the serial data input pin (SI), and the D3 pin serves as the serial
data output pin (SO).
The D1 pin serves as the parallel/serial interface mode selection pin (P, /S), and the D2 pin serves as the chip
address enable pin (CAE).
1.2 SI (Serial Data In) … Also serves as D0 input
This pin serves as the serial data input pin in the serial interface mode. Data on the SI line is loaded into the
serial/parallel register at the /SCK rising edge. The first data becomes the MSB. This is a Schmitt trigger input with
hysteresis, in order to prevent erroneous operation caused by noise.
1.3 SO (Serial Data Out) … Also serves as D3 output
This pin serves as the serial data output pin in the serial interface mode. The serial/parallel register contents are
output to the SO pin with the MSB first in synchronization with the /SCK pin falling edge.
1.4 P, /S (Parallel/Serial Select) … Also serves as D1 input
This pin is sampled at the RESET signal falling edge (when the reset is released). If this pin is high, the parallel
interface mode is set. If it is low, the serial interface mode is set. This is a Schmitt trigger input with hysteresis in
order to prevent erroneous operation caused by noise.
1.5 CAE (Chip Address Enable) … Also serves as D2 input
The CAE input has a meaning, if P, /S input is low (when the serial interface mode is specified) at the RESET
signal falling edge (when reset is released). If the CAE signal is high at this timing, the chip address function is enabled.
If the CAE signal is low, the chip address function is disabled. This is a Schmitt trigger input with
hysteresis in order to prevent erroneous operation caused by noise.
1.6 CA0, CA1 (Chip Address) … Input
This is the input pin used to allocate the inherent address to select each µ PD16434 chip, when interfacing with
the CPU in a multi-chip configuration. In the parallel interface mode, CA0 and CA1 inputs are compared with the
chip address information sent from the CPU, regardless of the CAE input. In the serial interface mode, these inputs are
compared with the chip address information sent from the CPU, when the chip address selection function is enabled by
the CAE input.
6
Data Sheet S10299EJ4V0DS00
µ PD16434
Table 1–1. Processing CA1, CA0 Pins
Mode
CA1, CA0
With chip address function
Set to 00, 01, 10, or 11
- Always in parallel mode
(always 00 in single chip configuration)
- When CAE = 1 in serial mode
Without chip address function
Always set to 00
- When CAE = 0 in serial mode
Remark In a multi-chip configuration in the serial interface mode, chip selection is also
possible by providing decoded /CS signals for the number of chips used, without
using the chip address function. In this case, CAE for each chip must be set to 0,
and CA1 and CA0 pins must be set to 00.
These are Schmitt trigger inputs with hysteresis in order to prevent erroneous operation caused by noise.
1.7 /CS (Chip Select) … Input
This is the chip select input, which is low active.
When the chip address function is not used, if a low is input to the /CS input, the /STB, /SCK and C, /D inputs
become effective, so that commands and data can be input/output.
When the chip address function is used, in order for the /STB, /SCK and C, /D inputs to become effective, the chip
address information and CA0 and CA1 inputs must coincide, and moreover, the /CS input should become low.
When the /CS input is set to high, D3-D0 and /BUSY pins unconditionally become high impedance.
This is a Schmitt trigger input with hysteresis in order to prevent erroneous operation caused by noise.
1.8 /STB, /SCK (Strobe/Serial Clock) … Input
In the parallel interface mode, this pin serves as the strobe signal input pin (STB) for 4-bit parallel data
input/output operation. In the serial interface mode, this pin serves as the serial clock input pin (/SCK) for serial data
input/output operation.
1.9 C, /D (Command/Data) … Input
This pin is used to identify whether serial or parallel data input is a command or data. When inputting a command,
set the C, /D pin to high. When inputting data, set to low.
When inputting a command or data in the parallel interface mode, the command or data is latched at the second
/STB rising edge. In the serial interface mode, the command or data is latched at the rising edge of the 8th /SCK.
However, in parallel input, switching C, /D must be performed, before the falling edge of the 1st /STB.
When outputting data, C, /D input must always be set to low, regardless of whether the mode is parallel or serial.
This is a Schmitt trigger input with hysteresis in order to prevent erroneous operation caused by noise.
1.10 /BUSY (Busy) … 3-state output
This pin outputs a /BUSY signal which indicates to the CPU that the µ PD16434 is busy because of internal
processing.
If this signal is low, µ PD16434 is busy, and the CPU cannot execute read/write to the µ PD16434.
The /BUSY signal becomes low at second rising of the /STB signal in the parallel interface mode. In the serial
interface mode, the /BUSY signal becomes low at the rising edge of the 8th /SCK.
The µ PD16434 sets the /BUSY signal to high, when the µ PD16434 completes the internal processing.
The /BUSY output becomes high impedance, when the chip is not selected (/CS = high or the chip address does
not coincide).
Data Sheet S10299EJ4V0DS00
7
µ PD16434
1.11 SYNC (Synchronous) … 3-state input/output
In a multi-chip configuration, in which the row drive signal is commonly used, this pin inputs/outputs the
synchronous signal in order to synchronize the phases of all LCD drive alternate cycle signals (row/column signals)
with the frame period.
One chip in the multi-chip configuration is selected as the master, and the SYNC pin of the master is set to the
output mode.
The remaining chips all serve as slave chips, and these SYNC pins are set to the input mode.
The SMM command is used to specify whether the pin functions as an input or output pin.
The master chip, set in the output mode, outputs the SYNC pulse in the last cycle in each frame. A slave chip
reads the SYNC pulse output from the master chip for synchronization with the master chip.
Figure 1-1 and Figure 1-2 show SYNC pulse output timing waveforms in 8-time-division and 16-time-division
modes, respectively.
In single chip configuration, the SYNC pin can be set in either the input or output mode. However, when it is set in
the input mode, the SYNC pin must be fixed to VSS. If it is set in the output mode, the SYNC pin must be left open.
Figure 1–1. SYNC Signal in 8-Time-Division Mode
1 frame
ROW0
SYNC
Figure 1–2. SYNC Signal in 16-Time-Division Mode
1 frame
ROW0
SYNC
8
Data Sheet S10299EJ4V0DS00
µ PD16434
1.12 C0 to C41 (Column) … Output
These pins serve as LCD column drive signal output pins.
1.13 R8/C49 to R15/C42 (Row/Column) … Output
These pins serve as LCD row drive signals R8 to R15 or column drive signals C49 to C42 output pins. Whether or
not these pins are used as row or column pins is specified by the SMM command.
1.14 R0/R8 to R7/R15 (Row) … Output
These pins serve as LCD row drive signals R0 to R7 or R8 to R15. Whether or not these pins are used as R0 to
R7 or R8 to R15 is specified by the SMM command.
1.15 VLC1 to VLC5 (LCD Drive Voltage Supply) … Input
These pins input the reference voltage for determining the LCD row/column drive signal voltage level.
1.16 CLOCK (Clock) … Input
This pin inputs the external clock.
1.17 RESET (Reset) … Input
This is the high active reset signal input pin. The reset operation has priority over all other operations.
This input is also used for cleaning the standby mode or operation to retain data in the data memory at a low
power supply voltage.
1.18 VDD
Positive voltage power supply pin.
1.19 VSS
Ground pin.
Data Sheet S10299EJ4V0DS00
9
µ PD16434
2. INTERNAL BLOCK FUNCTIONS
2.1 Serial/Parallel Interface
The µ PD16434 contains both serial and parallel interface functions. Whether the serial interface or the parallel
interface is used is determined by whether the P, /S input is high (specifying the parallel interface) or low
(specifying the serial interface) at the RESET signal falling edge.
The interface circuit is used to write commands and data from the CPU or output data to the CPU.
The operation of the serial/parallel interface differs, depending on the data processing mode setting. When a
RESET is input, the data processing mode is initialized to the write mode, so that the first command input can be
accepted. Afterwards, the mode can be set to write related or read related data processing mode by the data
processing set command.
If the data processing mode is set to the write, AND, OR, or the character write related mode, the serial/parallel
interface is set to the data input mode, and the µ PD16434 clocks in the data from the SI pin (serial data) or from the D3
to D0 pins (4-bit parallel data) in synchronization with the rising edge of the /SCK or the /STB, respectively.
If the data processing mode is set to the read mode, the serial/parallel interface becomes the data output mode
and outputs data from the SO pin (serial data) or from the D3 to D0 pins (4-bit parallel data) in synchronization with the
falling edge of the /SCK or the /STB.
The serial/parallel register serves as the buffer, between 8-bit serial data or two 4-bit parallel data transferred
through the serial input/output (SI, SO) or parallel input/output (D3 to D0) and 8-bit parallel data of the data memory.
Figure 2–1. Serial/Parallel Interface
Internal bus
8
/STB, /SCK
/STB'
RESET
/CS
Read/write
control
CA0,CA1
/SCK'
SI'
C, /D
/BUSY
8-bit serial/parallel register
bit 0-3
bit 4-7
4
4
D0/SI
D1(P, /S)
Data
control
D2(CAE)
D3/SO
10
Data Sheet S10299EJ4V0DS00
SO'
µ PD16434
If the C, /D input indicates command specifications, the data input from the CPU to the serial/parallel interface is
sent from the serial/parallel register to the command decoder for decoding.
In the write mode, if the C, /D input indicates data specifications, the data loaded to the serial/parallel register is
directly transferred to the data memory.
In the AND or OR mode, the data loaded into the serial/parallel register is ANDed or ORed with the data memory
contents, and the result is transferred to the data memory. In the character mode, the data loaded into the
serial/parallel register is regarded as ASCII or JIS code and is sent to the character generator. It is decoded to 5 ×
7-bit character display pattern, and is stored into 5 successive data memory addresses.
Only when set to the read mode, can the serial/parallel interface output data to the CPU. When set to the read
mode, the serial/parallel interface always reads 8-bit data from the data memory and sets it in the serial/parallel register
for the next read operation.
In the serial interface mode, the data in the serial/parallel register is output from the SO pin with the MSB first at
each /SCK falling edge.
In the parallel interface mode, the upper 4 bits of the data in the serial/parallel register are output from the D3 to
D0 pins at the first falling edge of the /STB, and the lower 4 bits of the data in the serial/parallel register are output from
those pins at the second falling edge of the /STB.
In either the serial/parallel interface mode, each time 8 bits of data are output, the next 8 bits of data are
automatically read out from the data memory and set in the serial/parallel register.
2.2 Command Decoder
If the 8-bit data, input through the serial/parallel interface, is specified as a command (C, /D = 1), the data is
clocked in as a command, and is decoded to generate an internal control signal.
2.3 Character Generator
The character generator becomes effective, when a character mode setting command (SCML, SCMR) is
executed. In this case, 8-bit data written through the serial/parallel interface is interpreted as a character code, and the
5 × 7-dot matrix pattern, corresponding to the code, will be generated. It is transferred to the 5 successive addresses in
the data memory (7 bits × 5 times).
The character generator contains the following 160 different pattern data :
ASCII
JIS
Upper-case alphabets 26
KATAKANA 55
Lower-case alphabets 26
Symbols
Numerical characters
10
Symbols
34
9
Figure 2–2 shows correspondence of character codes (ASCII/JIS) and 5 dots × 7 dots display patterns. 96 codes
of 20H to 7FH correspond to ASCII characters, and A0H to DFH correspond to JIS characters.
Data Sheet S10299EJ4V0DS00
11
µ PD16434
Figure 2–2. Character codes and Display Pattern (Standard ROM code: 001)
7
4 0
3
Character code
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
12
Data Sheet S10299EJ4V0DS00
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
µ PD16434
Figure 2–3 shows the LCD configuration for the character generator. A character is configured in 5 × 7-dot
configuration.
The most significant bit (bit 7) of the data memory is not used by the character generator. Therefore, LCD dots,
corresponding to the most significant bit (R7 in 8-time-division, or R7 and R15 in 16-time-division), can be used for the
cursor or indicator display pattern, independently from the character generator.
The most significant bits are manipulated by a cursor manipulation command (WRCURS, CLCURS), etc.
Figure 2–3. LCD Configuration When Using Character Generator
(a) 8-time-division
(b) 16-time-division
R0
R0
R1
R1
R2
R2
R3
R3
R4
R4
R5
R5
R6
R6
R7
R7
R8
Cn+3
Cn+4
Cn+1
Cn+2
R9
Cn
R10
R11
R12
R13
R14
R15
Cn+3
Cn+4
Data Sheet S10299EJ4V0DS00
Cn+1
Cn+2
Cn
13
µ PD16434
2.4 Data Pointer
The data pointer consists of a 6-bit binary counter (DP5 to DP0) and 1-bit bank flag (BNKF). It specifies the data
memory address.
Figure2–4. Data Pointer Organization
6-bit binary counter
BNKF
DP5
DP4
DP3
DP2
DP1
DP0
The contents of the bank flag and the 6-bit binary counter are set simultaneously by the immediate data from the
LDPI command.
The bank flag contents specify the data memory bank (BNKF=0 : Bank 0, BNKF=1 : Bank 1), and the 6-bit binary
counter contents specify the address (00H to 31H) in the bank specified by the bank flag. The 6-bit binary counter is an
up/down counter. Its contents are modified (+1, −1, or held) each time a read, write, or AND operation is performed, or
an 8-bit data is input/output in the OR mode, according to the specifications for each mode setting command.
When the BSET or BRESET command is executed, the 6-bit binary counter contents are modified (+1, −1, or
held) each time according to the command specification.
In addition, in the character mode, the 6-bit binary counter contents are modified (+5, −5) each time an 8-bit data
is input or a cursor processing command is executed.
Remark
The 6-bit binary counter value can exceed the limit of the data memory address space. For example, if
the 6-bit binary counter is decremented (−1) from 00H, the value will be 3FH, or it is incremented (+1)
from 31H, the value will be 32H. However, the data memory will perform nothing for the command
specifying an address from 32H to 3FH.
14
Data Sheet S10299EJ4V0DS00
µ PD16434
2.5 Data Memory
The data memory is a static RAM configured by two 50-word × 8-bit banks. It is used for storing display data.
Figure 2–5. Data Memory Configuration
00H
Bank 0
(50 x 8)
31H
00H
Bank 1
(50 x 8)
31H
The data memory bank is specified by the bank flag in the data pointer, and the address in the bank is specified
by the 6-bit binary counter in the data pointer.
The 8-bit data, written to the serial/parallel interface by the CPU, is used for operation or decoded according to
the specified data processing mode, and is written into the data memory.
The data memory contents can be directly manipulated by a bit manipulation instruction.
When the µ PD16434 is set in the read mode, the data memory contents are output to the CPU through the
serial/parallel interface.
The data memory contents are read out in bit units in synchronization with the row drive signal and are sent to the
column driver for driving the LCD. This operation is performed independently from command/data write/read operation
with the CPU, which is performed through the serial/parallel interface. Display data read out operation differs,
depending on the number of time-divisions.
(1) 8-time-division (single/multi-chip configuration)
The contents of the display data in bank 0 or bank 1, whichever is specified by the SMM command, are read
out to the column driver.
Figure 2–6 shows bits correspondence for the row driver and column driver for the data memory. If the data
located at the Rn and Cm intersection is 1, the corresponding LCD dot is ON. If the data is 0, the dot is OFF.
Data Sheet S10299EJ4V0DS00
15
µ PD16434
Figure 2–6. Data Memory (8-Time-Division, Single/Multi-Chip)
31H
30H
01H
00H
bit 0
R0
1
R1
2
R2
3
R3
4
R4
5
R5
6
R6
7
R7
C49
C48
C1
C0
To column driver
16
Data Sheet S10299EJ4V0DS00
Corresponding
row signal
µ PD16434
(2) 16-time-division (single-chip configuration)
Bank 0 and bank 1 are used in a pair, and the contents are read out to the column driver as 42 × 16-bit display
data.
Figure 2–7 shows correspondence of bits for the row driver and column driver for the data memory. If the data
located at the Rn and Cm intersection is 1, the corresponding LCD dot is ON. If the data is 0, the dot is OFF.
Figure 2–7. Data Memory (16-Time-Division, Single-Chip)
29H
Bank 0
Bank 1
28H
01H
00H
bit 0
R0
1
R1
2
R2
3
R3
4
R4
5
R5
6
R6
7
R7
0
R8
1
R9
2
R10
3
R11
4
R12
5
R13
6
R14
7
R15
C41
C40
C1
Corresponding
row signal
C0
To colmn driver
Data Sheet S10299EJ4V0DS00
17
µ PD16434
(3) 16-time-division (multi-chip configuration)
Bank 0 and bank 1 are used in a pair, and the contents are read out to the column driver as 50 × 16-bit display
data.
The row driver signals, output from each µ PD16434, are R0 to R7 or R8 to R15.
Figure 2–8 shows bits correspondence for the row driver and column driver for the data memory for each chip.
Figure 2–8. Data Memory (16-Time-Division, Multi-chip)
31H
Bank 0
Bank 1
30H
01H
00H
bit 0
R0
1
R1
2
R2
3
R3
4
R4
5
R5
6
R6
7
R7
0
R8
1
R9
2
R10
3
R11
4
R12
5
R13
6
R14
7
R15
C49
C48
C1
C0
To colmn driver
18
Data Sheet S10299EJ4V0DS00
Corresponding
row signal
µ PD16434
2.6 LCD Voltage Control Circuit
This circuit multiplexes the DC voltage supplied from the LCD drive reference voltage inputs (VLC1 to VLC5) with
the AC signal synchronized with the CLOCK and SYNC signal, and supplies the signals to determine the select and
non-select level of the row and column signals and the phase for the row and column drivers.
Table 2–1 indicates these signal levels and the phase.
Table 2–1. LCD Driver Voltage Signal Levels and Phase
8-time-divisions
–
Row
Column
16-time-divisions
+
–
+
Select
VLC0
VLC5
VLC0
VLC5
Non-select
VLC4
VLC1
VLC4
VLC1
Select
VLC5
VLC0
VLC5
VLC0
Non-select
Note
VLC2
VLC2
VLC3
VLC2
Note VLC2 = VLC3
2.7 LCD Timing Control Circuit
This circuit generates the timing signals from the clock signal, according to the frame frequency specified by the
SFF command, and the number of time divisions specified by the SMM command.
The timing signals are necessary for automatically reading the display data and driving the LCD, and are supplied
to the data memory row/column driver, and LCD voltage control circuit.
If the SYNC signal is set to the output mode by the SMM command, the SYNC signal is output for each frame. If
the SYNC mode is specified to the input mode, the SYNC signal supplied from some other chip is input to generate the
timing signals in synchronization with each frame interval.
The SYNC signal input/output function is used to synchronize the LCD drive timing between chips in multi-chip
configuration.
2.8 Row/Column Driver
The row/column driver consists of the column driver for C0 to C41 signals, row/column driver for R15 to R8 and
C42 to C49, and a dual mode row driver for R0 to R7 or R8 to R15.
The dual mode row driver function is determined by the SMM command.
Data Sheet S10299EJ4V0DS00
19
µ PD16434
Table 2–2. LCD Dual Mode Row Driver Function Selection
Note 1
M2, M1, M0
Number of time
R0/R8 to R7/R15
R15/C42 to R8/C49
divisions
000
8
R0 to R7
C42 to C49
16
R8 to R15
001
010
011
100
Note 2
101
Note 3
R0 to R7
110
111
R15 to R8
Notes 1. M2, M1, M0 is code specified by SMM command.
2. Some other chip handles R0 to R7 outputs.
3. Some other chip handles R8 to R15 outputs.
M2, M1, M0 = 111 is for single chip configuration. In this case, R15/C42 to
R8/C49 are used as row signal outputs, and all 16 row signals are output
from this chip.
These drivers perform switching of the analog level in correspondence to the contents of the display data read out
from the data memory and the timing signals supplied from the LCD timing control circuit, according to the select level,
non-select level, and phase supplied from the LCD voltage control circuit, and generates and outputs row and column
driver signals in order to directly drive the LCD.
20
Data Sheet S10299EJ4V0DS00
µ PD16434
3. DATA INPUT/OUTPUT OPERATION
In the µ PD16434, a command/data consists of 1 byte (8 bits), and processing is performed each time a byte of
data is transferred in either the serial or parallel mode.
The end of a byte data transfer is confirmed by the byte counter (octal/binary counter) which counts eight /SCK
counts or two /STB counts.
This counter is unconditionally cleared, when /CS = high or RESET = high, and becomes ready to count a new byte
or data. Therefore, if /CS is set to high or RESET is input in the middle of a byte transfer, the byte transfer is not
guaranteed.
In the serial interface mode, data is treated as 8-bit serial data. It is regarded that 1 byte of data has been input or
output, when eight serial clock pulses (/SCK) are counted in the chip selected condition, then internal processing is
started. At the 8th rising edge of the /SCK, the µ PD16434 sets the /BUSY signal to low to inform the CPU that the
µ PD16434 is in a busy state.
When the internal processing completes, the µ PD16434 sets the /BUSY signal to high to inform the CPU that the
µ PD16434 is ready for the next byte transfer.
The serial data is input/output with the MSB first (refer to Figure 3–1 and Figure 3–2).
If the chip address selection function is specified in the serial interface mode, the 8-bit serial data (only the lower 2
bits have a meaning) for chip address information must be written first after the /CS falling edge. Only the chip, whose
address coincides with this information, can enter command input or data input/output operation (refer to Figure 3–3 and
Figure 3–4).
In the parallel interface mode, since the data bus (D3 to D0) is a 4-bit bus, data is treated as 4-bit × 2 parallel data.
When the parallel data strobe signal (/STB) is counted twice in the chip selected state, it is regarded that a byte of data
has been input/output, then the µ PD16434 enters the internal processing.
At the 2nd rising edge of the /STB, the µ PD16434 sets the /BUSY signal to low, to inform the CPU that the
µ PD16434 is in a busy state. When the internal processing completes, the µ PD16434 sets the /BUSY signal to high, to
inform the CPU that the µ PD16434 is ready for the next byte transfer.
In both input and output operation, the upper 4 bits of parallel data correspond to the first /STB, and the lower 4 bits
of parallel data correspond to the second /STB.
The parallel interface of the µ PD16434 is compatible with the µ PD82C43 I/O expander, so that the parallel data
can be input to the µ PD16434 in the same manner as sending 4-bit data twice to the µ PD82C43. In addition, 8-bit data
can be read out from the serial/parallel register of the µ PD16434 in the same way as reading 4-bit data twice from the
µ PD82C43.
The chip address selection function is always specified in the parallel interface mode. After the /CS falling edge, the
data on the D1 and D0 lines, read at the first falling edge of the /STB, becomes the chip address information. The lower 2
bits of the command code, output from the CPU as the data for selecting port 4 to port 7 of the µ PD82C43, are used as
the chip address information. After the /CS falling edge, the command code, output from the CPU at the second and
successive falling edges of the /STB, has no meaning for the µ PD16434 (refer to Figure 3–5 and Figure 3–6). Refer to 4.
SELECTING µ PD16434 INTERFACE FUNCTION WITH CPU for details on chip address function
selection.
Data Sheet S10299EJ4V0DS00
21
µ PD16434
Figure 3–1. Serial Input Timing Waveforms (Without Chip Address Selection Function)
/CS
/SCK
SI
MSB
LSB
C, /D
/BUSY
Internal
processing time
Figure 3–2. Serial Output Timing Waveforms
/CS
/SCK
SO
MSB
LSB
/BUSY
Internal
processing time
C, /D
22
Data Sheet S10299EJ4V0DS00
/SCK
7th
8th
SI
Data Sheet S10299EJ4V0DS00
MSB
LSB
Chip address
To all chips
To newly selected chip
C, /D
/BUSY
Hi-Z
/BUSY output for chip that
was selected before /CS
was set to high
/BUSY output
for selected
chip
µ PD16434
Same chip
/BUSY output for newly selected chip
Figure 3–3. Serial Input Timing Waveforms (With Chip Address Selection Function)
/CS
23
24
/SCK
7th
8th
SI
Data Sheet S10299EJ4V0DS00
Chip address
To all chips
SO
MSB
From newly selected chip
C, /D
/BUSY
/BUSY output for
selected chips
Hi-Z
/BUSY output for chip that
was selected before /CS was
set to high
/BUSY output for newly selected chip
LSB
Figure 3–4. Serial Output Timing Waveforms (With Chip Address Selection Function)
/CS
µ PD16434
µ PD16434
Figure 3–5. Parallel Input Timing
/CS
/STB
D3 to D0
1st
Chip
address
2nd
Upper
4 bits
CPU→16434 CPU→16434
Invalid
data
Lower
4 bits
CPU→16434 CPU→16434
C, /D
/BUSY
/BUSY output for newly
selected chip
/BUSY output for
chip that was selected before
/CS was set to high
Data Sheet S10299EJ4V0DS00
25
µ PD16434
Figure 3–6. Parallel Output Timing
/CS
"L"
/STB
D3 to D0
1st
Invalid
data
2nd
Upper
4 bits
CPU→16434 16434→CPU
Invalid
data
Lower
4 bits
CPU→16434 16434→CPU
/BUSY
Internal
processing time
C, /D
26
Data Sheet S10299EJ4V0DS00
µ PD16434
4. SELECTING µ PD16434 INTERFACE FUNCTION WITH CPU
The command/data for the µ PD16434 is 8 bits long. However, serial interfacing with the CPU is made in 8-bit
transfer or parallel interfacing is made in two 4-bit transfers. In addition, the µ PD16434 is provided with a chip address
selection function for multi-chip system configuration. Whether the serial or parallel interface is used and whether or not
the chip address select function is used are specified by the data on the D2 (CAE) line and D1 (P, /S) line at the RESET
signal release timing (falling edge).
Figure 4–1. Interface Specification Timing Waveforms
RESET
D2(CAE)
D1(P, /S)
Table 4–1. Interface Specification Code
D2(CAE)
D1(P, /S)
0
0
1
0
0/1
1
Serial/parallel
Chip address
specification
selection function
Serial
Unprovided
Provided
Parallel
4.1 Functions of Shared Pins
The function of the /STB, /SCK, D3/SO, and the D0/SI pins used for clock input and data input/output differ,
depending on whether the serial interface or the parallel interface is specified, as indicated in Table4–2.
Table 4–2. Function of Shared Pins
Pin name
Serial (P, /S = 0)
Parallel (P, /S = 1)
/STB, /SCK
/SCK input
/STB input
D3/SO
SO output
D3 to D0 input/output
D2(CAE)
–
D1(P, /S)
–
D0/SI
(4-bit parallel data bus)
SI input
Data Sheet S10299EJ4V0DS00
27
µ PD16434
4.2 Chip Address Selection Function
In a multi-chip system configuration, the chip address selection function compares the chip address assigned to
each µ PD16434 (by CA0, CA1 inputs) in advance and the chip address information (2 bits) sent from the CPU in the
serial or parallel data format. Only the chip whose address coincides with the chip address information is seleceted
(enables command/data input/output).
Thus, the CPU need not send two or more chip select signals (/CS).
This function is unconditionally provided in the parallel interface mode. However, in the serial interface mode, this
function is provided, when D2(CAE) = 1 (at reset release), is specified.
(1) Parallel interface mode (refer to Figure 3–5 and Figure 3–6)
After the falling edge of the /CS, the data read into D1 (corresponds to CA1) and D0 (corresponds to CA0) at the
first falling edge of the /STB becomes the 2-bit chip address information.
The parallel interface is equivalent to that for the µ PD82C43 I/O expander. Therefore, the chip address
information (0 to 3) for the µ PD16434 can be obtained on the D1 and D0 lines at the falling edge of the /STB by
executing an output or input instruction for port 4 to port 7 of the µ PD82C43, when the µ PD50H is connected to the
µ PD16434 using the µ PD82C43 interface function.
(2) Serial interface mode (refer to Figure 3–3 and Figure 3–4)
After the falling edge of the /CS, the data read in to SI at the rising edge of the 7th /SCK (corresponds to CA1)
and 8th /SCK (corresponds to CA0), that is the lower 2 bits of the first 8-bit serial data, becomes the chip
address information.
Remarks 1. When a RESET is input, the chip address comparison data (data compared with CA1 and CA0) in the
µ PD16434 is cleared to "00". Therefore, in multi-chip configuration, if the /CS is set to low
immediately after the RESET input is released, a chip whose CA1 and CA0 are set to "00" sets the
/BUSY to high, informing the CPU that the chip can be accessed.
If no chip address is sent, a chip whose CA1 and CA0 are "00" will be accessed.
2. The following points must be noted for a multi-chip configuration system using the parallel interface;
when transferring the process from chip A, which has already been in the read mode to chip B, and
again selecting chip A after that, the data pointer must be set by the data pointer load command
reading data.
28
Data Sheet S10299EJ4V0DS00
µ PD16434
5. LCD DRIVE REFERENCE VOLTAGE SUPPLY
The value of the LCD drive reference voltage to the µ PD16434 differs, depending on whether the number of time
divisions is 8 or 16, so that the LCD drive reference voltage should be set as shown in Figure 5–1 and Figure 5–2.
Figure 5–1. 8-Time-Divisions
Figure 5–2. 16-Time-Divisions
VDD
(VLC0)VDD
(VLC0) VDD
1
VLCD
4
VLC1
VDD −
VLC2
2
VDD − 4 VLCD
µPD16434
VDD
VDD −
VLC2
2
VDD − 5 VLCD
VLC3
VDD − 3
5 VLCD
µPD16434
VLC3
1
VLCD
5
VLC1
VLC4
3
VDD − 4 VLCD
VLC4
VDD − 4
5 VLCD
VLC5
VDD − VLCD
VLC5
VDD − VLCD
Remark For both 8 and 16-time-divisions, the LCD drive voltage (LLCD) must not exceed VDD.
5.1 Supplying LCD Drive Reference Voltage by Resistor Network
Figure 5–3 and Figure 5–4 show circuit examples, which supply the LCD drive reference voltage indicated in
Figure 5–1 and Figure 5–2 using register networks which divide the voltage level between VDD and VSS.
Figure 5–3. 8-Time-Divisions Circuit Example
(VLC0) VDD
Figure 5–4. 16-Time-Divisions Circuit Example
VDD
VDD
(VLC0) VDD
R1
R1
VLC1
VLC1
R1
R1
VLC2
VLC2
R1
µPD16434
µPD16434
VLC3
VLC3
R1
R1
VLC4
VLC4
R1
R1
VLC5
VLC5
R2
VSS
−6.0 V
R2
VSS
−6.0 V
The values of R1 and R2, which divide the voltage for 8-time-divisions and 16-time-divisions, are determined by
the following expressions:
R1 =
VLCD
× R2 (8-time-divisions)
4(V − VLCD)
DD
Data Sheet S10299EJ4V0DS00
29
µ PD16434
R1 =
VLCD
× R2 (16-time-divisions)
5(VDD − VLCD)
5.2 Reduction in Current Consumption by RESET Signal
If a resistor network is used to supply the LCD drive reference voltage, some current is drained by the resistor
network connected across VDD and VSS when no display operation is performed, such as when the µ PD16434 is in
the STOP mode or when it is being reset. Therefore, for a system to which reducing the current draw is extremely
important, the current path thorough the resistor network must be cut off by an external circuit, when no displaying is
performed, to eliminate unnecessary current flow.
Figure 5–5 shows a circuit which cuts off the current to the resistor network during reset state (RESET = high)
using the the RESET signal level instead of the VSS level.
Figure 5–5. Example of Controlling Current Path Using RESET Signal
VDD
VDD
VDD (VLC0)
VLC1
VLC2
CPU
VLC3
µPD16434
VLC4
VLC5
Output port
RESET
Remark The power to the CPU and the µ PD16434 must be from the same source.
30
Data Sheet S10299EJ4V0DS00
µ PD16434
6. DISPLAY EXAMPLES
Figure 6–1 shows how the data memory contents and LCD display pattern are corresponded, when displaying
characters "AEZ" in 8-time-division mode.
This example is to display 3 digits of 5×7 (5×8) dot characters, and uses data memory addresses 00H to 0EH
(0 to 14) and column signals C0 to C14.
Figure 6–2 shows the timing waveforms for displaying character "A" in columns C14 to C10 for the display example,
shown in figure 6–1.
Figure 6–3 shows how the data memory contents and display pattern are corresponded, when displaying characters
" ANZ " in 16-time-division mode.
8, 5
This example is to display 5 × 7 (5 × 8) dot characters in two rows, 3 digits in each row, and uses data memory
addresses 00H to 0EH (0 to 14) in data memory banks 0 and 1 and column signals C0 to C14.
A
Figure 6–4 shows the timing waveforms for displaying character " 8 " in columns C14 to C10 for display example,
shown in Figure 6–3.
In Figure 6–2 and Figure 6–4, when the differential waveform levels between the row signal and column signal are
VLCD and –VLCD, the LCD dot corresponding to these signals will be lit.
Figure 6–1. 8-Time-divisions
µPD16434
Note
Timing strobe
1
1
0
0
0
0
0
0
0
0
1
bit 1
0
1
1
0
0
0
0
0
0
0
1
0
bit 2
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
bit 3
1
0
0
0
1
1
0
0
0
0
0
1
0
0
0
bit 4
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
bit 5
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
bit 6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
bit 7
R7/R15
0
0
R6/R14
0
0
R5/R13
0
1
R4/R12
1
R3/R11
bit 0
R2/R10
1
C0
1
C1
1
C2
1
C3
1
C4
0
1
C5
1
1
C6
2
1
C7
3
1
C8
4
1
C9
5
0
C10
6
1
C11
7
1
C12
8
1
C13
9
0
C14
14 13 12 11 10
R1/R9
data memory address
R0/R8
Bank 0/1
Note Display data is read out from either bank 0 or bank 1.
Data Sheet S10299EJ4V0DS00
31
µ PD16434
Figure 6–2. 8-Time-divisions (When Displaying Character A)
1 frame
7
0
1
2
3
VDD
VLC1
ROW 0
VLC2
VLC3
VLC4
VDD
VLC1
ROW 1
VLC2
VLC3
VLC4
VDD
VLC1
ROW 7
VLC2
VLC3
VLC4
VDD
C10, C14
VLC2
VLC4
VDD
C11, C12, C13
VLC2
VLC4
VLCD
1/4 VLCD
ROW 0 to C13
−1/4 VLCD
−VLCD
32
Data Sheet S10299EJ4V0DS00
4
5
6
7
0
1
µ PD16434
Figure 6–3. 16-Time-divisions
µPD16434
Data memory address
14 13 12 11 10 9 8 7 6 5
bit 0
1
0
0
0
1
1
0
0
0
1
0
0
0
0
1
bit 1
1
0
0
0
1
1
1
0
0
1
0
0
0
1
0
bit 2
1
1
1
1
1
1
0
1
0
1
0
0
1
0
0
bit 3
1
0
0
0
1
1
0
0
1
1
0
1
0
0
0
bit 4
1
0
0
0
1
1
0
0
0
1
1
0
0
0
0
bit 5
1
0
0
0
1
1
0
0
0
1
1
1
1
1
1
bit 6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
bit 7
0
1
1
1
0
0
0
0
0
0
1
1
1
1
1
bit 0
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
bit 1
1
0
0
0
1
0
0
0
0
0
1
1
1
1
0
bit 2
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
bit 3
1
0
0
0
1
0
1
1
0
0
0
0
0
0
1
bit 4
1
0
0
0
1
0
0
1
0
0
1
0
0
0
1
bit 5
0
1
1
1
0
0
1
0
0
0
0
1
1
1
0
bit 6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
bit 7
R0/R8
R1/R9
R2/R10
R3/R11
R4/R12
R5/R13
R6/R14
R7/R15
1
C0
1
C1
1
C2
1
C3
1
C4
1
C5
0
C6
0
C7
0
C8
1
C9
0
0
C10
1
1
C11
2
1
C12
3
1
C13
Bank 1
4
0
C14
Bank 0
Timing strobe
To R0/R8 to R7/R15
of slave chip
Data Sheet S10299EJ4V0DS00
33
µ PD16434
Figure 6–4. 16-Time-divisions (When Displaying Characters A and 8)
1 frame
0
ROW 0
VDD
VLC1
VLC2
VLC3
VLC4
VLC5
ROW 1
VDD
VLC1
VLC2
VLC3
VLC4
VLC5
ROW 15
VDD
VLC1
VLC2
VLC3
VLC4
VLC5
1
2
3
4
5
6
7
VDD
C10, C14
VLC2
VLC3
VLC5
VDD
C11, C12, C13
VLC2
VLC3
VLC5
VLCD
1/5 VLCD
ROW 1 to C14
−1/5 VLCD
−VLCD
34
Data Sheet S10299EJ4V0DS00
8
9
10
11
12
13
14
15
0
µ PD16434
7. STANDBY MODE
The µ PD16434 offers the standby mode in order to reduce the power consumption, when displaying operation is
not necessary.
The standby mode is set, by executing the STOP command. The standby mode is actually set, when the /BUSY
signal is set to high after the STOP command is executed. In the standby mode, the µ PD16434 stops supplying the
CLOCK signal to the LCD timing control circuit and the clock control circuit by internally masking the CLOCK signal. In
addition, the µ PD16434 initializes the data processing mode to the auto-increment (I1I0 = 00) write mode. However, no
other modes are affected by RESET operation, so that the interface mode and the display mode will be retained. The
standby mode is cleared when a byte of data (command or data) is input, or when the RESET signal falls. However, the
processing necessary during the standby mode and operation after clearing the standby mode differ, depending on which
method is used.
In addition, the CLOCK signal to the µ PD16434 can be stopped during the standby mode. In this case, the power
consumption can be further reduced, compared to when the CLOCK is only internally masked.
7.1 Clearing Standby Mode
(1) Clearing standby mode by writing a byte of data
If the previous operation modes (except the data processing mode), used before entering the standby mode,
needs to be maintained, the standby mode can be cleared by writing a byte of data (command or data).
In the serial interface mode, the standby mode is cleared, when writing 8 bits of serial data is completed (at the
rising edge of the 8th /SCK). In the parallel interface, the standby mode is cleared, when writing the second 4-bit
data is completed (at the rising edge of the 2nd /STB).
When the chip address selection function is used in the serial interface mode, if /CS is set to high in the standby
mode, the first 8-bit data, after /CS is set to low, is used as the chip address information, when the standby mode
is cleared. Therefore, the standby mode is cleared, when writing the next 8-bit data is completed.
Remark During the standby mode, the clock necessary for driving the LCD by alternating current is stopped.
Therefore, the LCD drive signal level, before entering the standby mode, is maintained in the standby
mode. This means that a DC voltage remains applied to the LCD in the standby mode. To avoid this,
control the VLC5 pin voltage using the CPU output port, as shown in Figure7–1, and output a high
level from the output port, before executing the STOP command, to eliminate voltage differential
between the VDD and VLC5.
Data Sheet S10299EJ4V0DS00
35
µ PD16434
Figure 7–1. Controlling LCD Drive Voltage
VDD
VDD
VDD (VLC0)
VLC1
VLC2
VLC3
CPU
µPD16434
VLC4
VLC5
Output port
Remark The power fed to the CPU and the µ PD16434 must be from the same source.
(2) Clearing standby mode by RESET signal
For a system for which only the contents of the data memory need be held when the standby mode is cleared,
the RESET signal can be used to clear the standby mode.
When using the RESET signal for clearing the standby mode, set the RESET signal to high after the standby
mode is initiated (this can be checked by determining whether the /BUSY is set to high), then set the RESET signal
to low when clearing the standby mode. While the RESET signal is high, the LCD drive voltage becomes the same
as when it is in the reset operation, and no voltage is applied to the LCD. However, unlike normal reset operation,
the contents of the data memory will not become undefined by the RESET signal. The data which existed before
entering the standby mode is retained, and it can be used after clearing the standby mode. In a system which uses
this method, the current path control by the RESET signal shown in Figure5–5 can be used.
7.2 Stopping Clock Supply and Retaining Data at Low Voltage in Standby Mode
In the standby mode, only the data memory contents can be retained at a reduced voltage level. In this case, the
power consumption can be further reduced by stopping the CLOCK supply to the µ PD16434. When stopping the
CLOCK supply to the µ PD16434 in the standby mode, check that the µ PD16434 is in the standby mode (check that
the /BUSY signal is high, after executing the STOP command), set the RESET signal to high, then stop the CLOCK
supply to the µ PD16434 after the specified time period.
36
Data Sheet S10299EJ4V0DS00
µ PD16434
Figure 7–2. CLOCK Supply Stop Timing Waveforms in Standby Mode
Standby mode
STOP
/BUSY
/CS
RESET
CLOCK
tSRC
tHRC
Data can be retained
at a reduced voltage
Data Sheet S10299EJ4V0DS00
37
µ PD16434
8. RESET OPERATION
The µ PD16434 is initialized as follows, when a high level is input to the RESET pin :
• The chip address compare data (compared with CA1, CA0 inputs) is initialized to 00.
In a multi-chip configuration, /BUSY output operation will differ, depending on whether CA1 and CA0 of the chip
are 00 (coinciding address) or not (non-coinciding address) (refer to Figure 8–1).
When CA1, CA0 = 00
: Sets /BUSY output to low, if /CS = 0. If /CS = 1, sets /BUSY output to high
impedance.
Other than 00
: Sets /BUSY output to high impedance, regardless of /CS input.
In a single chip configuration, /BUSY output operation is the same as that when CA1 and CA0 are 00.
• All processing operations (command/data processing, reading timing signal and display data to the row and
column driver) are stopped.
• VLC3 level DC current is output from each LCD drive signal output pin (C0 to C41, R15/C42 to R8/C49, R0/R8
to R7/R15).
• The internal functions are set as follows (to the same conditions as when these commands are executed) :
SWM (I1I0 = 00)
: Auto-increment mode
LDPI (D6 to D0 = 0000000) : Data pointer is cleared to 0
SMM (M2 to M0 = 000)
: 8-time-divisions, R0/R8 to R7/R15 pins serve as R0 to R7 pins, SYNC pin is set in
the input mode, the data memory is set to bank 0.
SFF (F2 to F0 = 000)
14
: Frame frequency is set to fCL/2 .
• The byte transfer end counter is cleared.
• If the µ PD16434 is in the standby mode, the standby mode is maintained.
• The data memory contents become undefined.
When the high level input to the RESET pin is returned to low, the operation becomes possible, according to the
initialized contents. In addition, the next processing will be performed at the falling edge of the RESET signal. The display
output will be the same as when the DISP OFF is executed.
• The interface specification code (serial/parallel specification, chip address selection function provided/
unprovided) is read from the D2(CAE) and D1(P, /S) pins.
• A chip, whose CA1 and CA0 values are 0, becomes selected state.
38
Data Sheet S10299EJ4V0DS00
µ PD16434
• If a RESET is executed during the standby mode, the standby mode is cleared. In this case, the data memory
contents are retained.
Figure 8–1. Example of /BUSY Output Timing Waveforms by RESET Input
(a) when CA1, CA0 ≠ 00
RESET
/CS
Hi-Z
/BUSY
Output from
selected chip
Output from no chip
Output from chip whose
CA1 and CA0 values are 00
(b) when CA1, CA0 = 00 and /CS = 0
RESET
/CS
"L"
/BUSY
Output from
selected chip
Output from chip, whose
CA1 and CA0 values are 00
Data Sheet S10299EJ4V0DS00
39
µ PD16434
9. COMMANDS
The µ PD16434 offers the following 16 different commands, each consisting of 1 byte (8 bits) :
Table 9–1. List of Commands
Mnemonic
Operation
Hexadecimal code
SFF
Set Frame Frequency
10 to 14
SMM
Set Multiplexing Mode
18 to 1F
DISP OFF
Display Off
DISP ON
Display On
LDPI
Load Data Pointer with Immediate
SRM
Set Read Mode
60 to 63
SWM
Set Write Mode
64 to 67
SORM
Set OR Mode
68 to 6B
SANDM
Set AND Mode
6C to 6F
SCML
Set Character Mode with Left entry
71
SCMR
Set Character Mode with Right entry
72
BRESET
Bit Reset
20 to 3F
BSET
Bit set
40 to 5F
CLCURS
Clear Cursor
7C
WRCURS
Write Cursor
7D
STOP
Set Stop Mode
01
08
09
80 to B1, C0 to F1
9.1 LCD Display Mode Setting Commands
The following commands are provided for LCD display mode setting :
SFF (Set Frame Frequency)
SMM (Set Multiplexing Mode)
DISP OFF (Display Off)
DISP ON (Display On)
(1) SFF (Set Frame Frequency)
0
0
0
1
0
F2
F1
F0
This command sets the frame frequency. The frame frequency will be the clock frequency input from the
CLOCK pin divided by the frequency dividing ratio specified by F2 to F0.
40
Data Sheet S10299EJ4V0DS00
µ PD16434
F2
F1
F0
Frame Frequency
0
0
0
fCL/2
0
0
1
fCL/2
0
1
0
fCL/2
0
1
1
fCL/2
1
0
0
fCL/2
1
0
1
14
13
12
11
10
These settings
to
1
are not allowed.
1
1
Remark fCL : Clock frequency
(2) SMM (Set Multiplexing Mode)
0
0
0
1
1
M2
M1
M0
This command specifies the number of time divisions, and the functions of the row driver, and the row/column
driver, input/output for the SYNC pin, and the data memory bank.
M2
M1
M0
0
0
0
Number of
time divisions
R0/R8 to
R7/R15
R15/C42 to
R8/C49
SYNC
pin
Memory
bank
0
Input
0
0
1
1
8
0
1
R0 to R7
0
0
Output
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
C42 to C49
R8 to R15
1
Input
16
0, 1
R0 to R7
Output
R15 to R8
Data Sheet S10299EJ4V0DS00
41
µ PD16434
(3) DISP OFF (Display Off)
0
0
0
0
1
0
0
0
This command sets the relationship of the row signal and column signal to non-select level, regardless of the
display data, and deletes display.
(4) DISP ON (Display On)
0
0
0
0
1
0
0
1
When this command is executed, the display operation will be performed according to the display data.
9.2 Data Pointer Load Command
(1) LDPI (Load Data Pointer with Immediate)
1
D6
D5
D4
D3
D2
D1
D0
Remark D6 to D0 = 00H to 31H, 40H to 71H
This command loads 7-bit immediate data D6 to D0 to the data pointer.
9.3 Data Processing Mode Setting Commands
The following six different commands are available as the data processing mode setting commands.
SRM (Set Read Mode)
SWM (Set Write Mode)
SORM (Set OR Mode)
SANDM (Set AND Mode)
SCML (Set Character Mode with Left Entry)
SCMR (Set Character Mode with Right Entry)
Each of these commands sets the µ PD16434 to the respective mode.
Afterwards, the µ PD16434 processes data in the specified mode until a command to set a different processing
mode is executed.
The lower 2 bits (I1I0) of these data processing mode setting commands specify the data pointer modification
operation for each byte data processing.
The data pointer is modified as follows:
42
Data Sheet S10299EJ4V0DS00
µ PD16434
I1
I0
Data pointer contents of modification
0
0
Automatically incremented (+1) each time a byte of data is processed.
0
1
Automatically decremented (−1) each time a byte of data is processed.
1
0
This setting is not allowed.
1
1
No modification (the same address is maintained)
(1) SRM (Set Read Mode)
0
1
1
0
0
0
I1
I0
The data processing mode is set to the read mode by this command. Afterwards, data processing will be
performed in the read mode.
When this mode is set, the contents of the data memory, addressed by the current contents of the data pointer,
are automatically transferred to the serial/parallel register.
The data pointer is then modified according to I1I0.
When all 8 bits of the serial/parallel register contents are read by the CPU, the contents of the data memory,
addressed by the modified data pointer, are automatically transferred into the serial/parallel register for the next
read operation. Afterwards, the same operation is repeated by the CPU, each time an 8-bit data is read.
(2) SWM (Set Write Mode)
0
1
1
0
0
1
I1
I0
The data processing mode is set to the write mode by this command. Afterwards, data processing will be
performed in the write mode.
When this mode is set, the 8-bit data written into the serial/parallel register by the CPU is stored into the data
memory addressed by the current contents of the data pointer. The data pointer is then modified, according to I1I0.
Afterwards, the same operation is repeated, each time an 8-bit data is written by the CPU.
(3) SORM (Set OR Mode)
0
1
1
0
1
0
I1
I0
The data processing mode is set to the OR mode by this command. Afterwards, data processing will be
performed in the OR mode.
When this mode is set, the 8-bit data, written into the serial/parallel register by the CPU, is ORed with the data
Data Sheet S10299EJ4V0DS00
43
µ PD16434
memory addressed by the current contents of the data pointer, and the result will be stored into the same data
memory address. The data pointer is then modified, according to I1I0. Afterwards, the same operation is repeated,
each time an 8-bit data is written by the CPU.
(4) SANDM (Set AND Mode)
0
1
1
0
1
1
I1
I0
The data processing mode is set to the AND mode by this command. Afterwards, data processing will be
performed in the AND mode.
When this mode is set, the 8-bit data, written into the serial/parallel register by the CPU, is ANDed with the data
memory addressed by the current contents of the data pointer, and the result will be stored into the same data
memory address. The data pointer is then modified, according to I1I0. Afterwards, the same operation is repeated,
each time an 8-bit data is written by the CPU.
(5) SCML (Set Character Mode with Left entry)
0
1
1
1
0
0
0
1
The data processing mode is set to the character mode with left entry by this command. Afterwards, data
processing will be performed in the Character mode with left entry.
When this mode is set, the 8-bit data written into the serial/parallel register by the CPU is treated as ASCII or JIS
code and is decoded to 5 × 7-bit character display data by the character generator. It is written into the lower five
consecutive data memory addresses from the address indicated by the current contents of the data memory. As a
result, the data pointer contents are subtracted by 5 (−5). Afterwards, the same operation is repeated, each time
an 8-bit data is written by the CPU.
(6) SCMR (Set Character Mode with Right entry)
0
1
1
1
0
0
1
0
The data processing mode is set to the character mode with right entry by this command. Afterwards, data
processing will be performed in the character mode with right entry.
When this mode is set, the 8-bit data written into the serial/parallel register by the CPU is treated as ASCII or JIS
code and is decoded to 5 × 7-bit character display data by the character generator, and is written into the
subsequent five data memory addresses from the address indicated by the current contents of the data memory.
As a result, the data pointer contents are added by 5 (+5).
Afterwards, the same operation is repeated, each time an 8-bit data is written by the CPU.
44
Data Sheet S10299EJ4V0DS00
µ PD16434
9.4 Memory Bit Manipulation Commands
The following four different memory bit manipulation commands are available:
BRESET (Bit Reset)
BSET (Bit Set)
CLCURS (Clear Cursor)
WRCURS (Write Cursor)
The BRESET and BSET commands can be executed in any data processing mode. After the bit specified by the
BRESET/BSET command in the data memory addressed by the data pointer is set/reset, the data pointer is modified
according to the lower 2 bits (J1J0) of the command byte.
The CLCURS or WRCURS command is used to clear or set the cursor (bit 7 position) in the character mode. After
these commands are executed, the data pointer contents are added by 5 or subtracted by 5.
Data pointer manipulation by these memory bit manipulation commands is effective, only when these commands
are executed. Afterwards, the data pointer is modified according to the data processing mode that has been set.
However, the data pointer contents are modified by the memory bit manipulation command. Therefore, the
modified value will be used as the initial value for the subsequent modification operation. The figure below shows the
BRESET and BSET command bit specifications and modification contents for the data pointer.
7
0
Data memory
B2 B1 B0
0 0 0
0 0 1
to
1 1 1
J1
J0
Data pointer contents for modification
0
0
+1
0
1
−1
1
0
This setting is not allowed
1
1
No modification (The same address is maintained)
Data Sheet S10299EJ4V0DS00
45
µ PD16434
(1) BRESET (Bit Reset)
0
0
1
B2
B1
B0
J1
J0
This command or these commands resets (to 0) the bit specified by B2 to B0 of the data memory addressed by
the data pointer. Afterwards, the data pointer is modified according to J 1J0.
(2) BSET (Bit Set)
0
1
0
B2
B1
B0
J1
J0
This command or these commands sets (to 1) the bit specified by B2 to B0 of the data memory addressed by
the data pointer.
Afterwards, the data pointer is modified according to J1J0.
(3) CLCURS (Clear Cursor)
0
1
1
1
1
1
0
0
When this command is executed in the character mode, bit 7 of each data memory of the five subsequent
addresses (SCMR mode) or the lower five consecutive addresses (SCML mode) from the address, indicated by
the current contents of the data pointer, is reset (to 0).
This command can be used to clear the cursor displayed for 5 × 7-bit configuration character.
(4) WRCURS (Write Cursor)
0
1
1
1
1
1
0
1
When this command is executed in the character mode, bit 7 of each data memory of the five subsequent
addresses (SCMR mode) or the lower five consecutive addresses (SCML mode) from the address, indicated by
the current contents of the data pointer, is set (to 1).
This command can be used to display the cursor for 5 × 7-bit configuration character.
46
Data Sheet S10299EJ4V0DS00
µ PD16434
9.5 Standby Operation Setting Command
(1) STOP (Set Stop Mode)
0
0
0
0
0
0
0
1
This command sets the STOP mode (standby mode).
The data processing mode is initialized to the auto-increment (I1I0 = 00) write mode.
Other modes are not affected by this command execution.
Data Sheet S10299EJ4V0DS00
47
µ PD16434
10. SYSTEM CONFIGURATION EXAMPLE
Shows a circuit example, when four µ PD16434s are used in a multi-chip system configuration.
Figure 10–1. System Configuration Example (Multi-Chip)
LCD (40 characters x 2 lines)
C49 to C0
(1)
C49 to C0
CA1
(2)
CA0
CA1
C49 to C0 R8 to R15
CA1
(3)
CA0
CA0
D0
to
D3
CLOCK
/CS
RESET
C, /D
/BUSY
/STB
CLOCK
/CS
RESET
C, /D
/BUSY
/STB
SYNC
D0 to D3
R0 to R7 C49 to C0
CA1
(0)
CA0
CPU
48
Data Sheet S10299EJ4V0DS00
µPD16434
x
4
µ PD16434
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 °C)
Parameter
Power Supply Voltage
LCD Drive Voltage
Note
Symbol
Conditions
VDD
VLCD
VDD = 5.0 V
Ratings
Unit
–0.3 to +7.0
V
0 to 12.5
V
Input Voltage
VI
–0.3 to VDD + 0.3
V
Output Voltage
VO
–0.3 to VDD + 0.3
V
Operating Ambient Temperature
TA
–40 to +85
°C
Storage Temperature
Tstg
–65 to +150
°C
Note VLCD = VDD − VLC5
Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the
quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values
exceeding which the product may be physically damaged. Be sure to use the product within the range of
the absolute maximum ratings.
Recommended Operating Range
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Power Supply Voltage
VDD
2.7
5.5
V
LCD Drive Voltage (VDD = 4.5 to 5.5V)
VLCD
4.5
12.0
V
LCD Drive Voltage (VDD = 2.7 to 4.5V)
VLCD
2.5
10.5
V
Logic Input Voltage
VIN
0
VDD
V
Drive Input Voltage
VLC1 to VLC4
VLC5
VDD
V
Data Sheet S10299EJ4V0DS00
49
µ PD16434
DC Characteristics 1 (TA = –40 to + 85 °C, VDD = 5 V ± 10 %, VLC5 = −6.0 V ± 10 %)
Parameter
High Level Input Voltage
Symbol
Conditions
MAX.
Unit
Except for /SCK
0.7 VDD
VDD
V
VIH2
/SCK
0.8 VDD
VDD
V
0
0.3 VDD
V
10
µA
−10
µA
VIL
High Level Input Leakage Current
ILIH
VI = VDD
ILIL
VI = 0 V
High Level Output Voltage
TYP.
VIH1
Low Level Input Voltage
Low Level Input Leakage Current
MIN.
VOH1
/BUSY, D0 to D3,
VDD – 0.5
V
VDD – 0.5
V
IOH = −400 µ A
Low Level Output Voltage
High Level Output Leakage
VOH2
SYNC, IOH = −100 µ A
VOL1
/BUSY, D0 to D3, IOL = 1.7 mA
0.5
V
VOL2
SYNC, IOL = 100 µ A
0.5
V
ILOH
VO = VDD
10
µA
ILOL
VO = 0 V
−10
µA
Current
Low Level Output Leakage Current
Row Output Impedance
RROW
6
16
kΩ
Row/Column Output Impedance
RROW
7.5
20
kΩ
15
30
kΩ
250
600
µA
25
µA
MAX.
Unit
f = 1 MHz
10
pF
Unmeasured pins returned to
25
pF
0 V.
15
pF
/COL
Column Output Impedance
Supply Current
RCOL
IDD1
Operation mode, fC = 400 kHz
IDD2
STOP mode, CLK = 0 V
Capacitance (TA = 25 °C, VDD = 0 V)
Parameter
Input Capacitance
Output Capacitance
I/O Capacitance
50
Symbol
CIN
COUT
CIO
Conditions
Data Sheet S10299EJ4V0DS00
MIN.
TYP.
µ PD16434
AC Characteristics 1 (TA = – 40 °C to + 85 °C, VDD = + 5 V ± 10 %)
Common Operation
Parameter
Clock Operation Frequency
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
1100
kHz
fC
100
Clock High Level pulse Width
tWHC
350
ns
Clock Low Level pulse Width
tWLC
350
ns
RESET High Level Width
tHRS
4
µs
/CS↓ → /BUSY Delay Time
tDCSB
CL = 50 pF
3
µs
/CS↑ → /BUSY Float Delay Time
tDCSBF
CL = 50 pF
5
µs
/CS High Level Width
tWHCS
SYNC Load Capacitance
CLSY
Data Set Time (RESET↓)
tSDR
0
µs
Data Hold Time (RESET↓)
tHRD
5
µs
µs
4
100
pF
Serial Input / Output Operation
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
/SCK Period
tCYK
0.9
µs
/SCK High Level Pulse Width
tWHK
400
ns
/SCK Low Level Pulse Width
tWLK
400
ns
High Level /SCK Hold Time (/BUSY↑)
tHBK
0
ns
SI Set Time (/SCK↑)
tSIK
120
ns
SI Hold Time (/SCK↑)
tHKI
270
ns
/SCK↓ → SO Delay Time
tDKO
CL = 50 pF
350
ns
8th /SCK↑ → /BUSY Delay Time
tDKB
CL = 50 pF
4
µs
/BUSY Low Level Time
tWLB
CL = 50 pF
64
1/fC
C,/D Set Time (1st /SCK↓)
tSDK
0
µs
C,/D Hold Time (8th /SCK↑)
tHKD
3
µs
/CS Hold Time (8th /SCK↑)
tHKCS
5
µs
Data Sheet S10299EJ4V0DS00
18
51
µ PD16434
Parallel Input / Output Operation
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Command Input Set Time (/STB↓)
tA
CL = 80 pF
120
ns
Command Input Hold Time (/STB↓)
tB
CL = 20 pF
110
ns
Data Input Set Time (/STB↑)
tC
CL = 80 pF
250
ns
Data Input Hold Time (/STB↑)
tD
CL = 20 pF
70
ns
Data Output Delay Time
tACC
CL = 80 pF
Data Output Hold Time
tH
CL = 20 pF
/STB Low Level Pulse Width
tSL
700
ns
/STB High Level Time
tSH
1
µs
/STB Hold Time (/BUSY↑)
tHBS
0
2nd /STB↑ → /BUSY Delay Time
tDSB
/BUSY Low Level Time
tWLB
C,/D Set Time (1st /STB↓)
tSDS
0
µs
C,/D Hold Time (2nd /STB↑)
tHSD
3
µs
/CS Hold Time (2nd /STB↑)
tHSCS
3
µs
52
CL = 50 pF
Data Sheet S10299EJ4V0DS00
0
18
750
ns
150
ns
µs
4
µs
64
1/fC
µ PD16434
DC Characteristics 2 (Unless otherwise specified, TA = –40 to + 85 °C, VDD = 3 V ± 10 %, VDD − VLC5 = 9 V ± 10 %)
Parameter
Symbol
High Level Input Voltage
Conditions
MIN.
TYP.
MAX.
Unit
VIH1
Except for /SCK
0.7 VDD
VDD
V
VIH2
/SCK
0.8 VDD
VDD
V
0
0.3 VDD
V
Low Level Input Voltage
VIL
High Level Input Leakage Current
ILIH
VI = VDD
10
µA
Low Level Input Leakage Current
ILIL
VI = 0 V
−10
µA
High Level Output Voltage
Low Level Output Voltage
VOH1
/BUSY, D0 to D3, IOH = −100 µ A
VDD – 0.5
V
VOH2
SYNC, IOH = −100 µ A
VDD – 0.5
V
VOL1
/BUSY, D0 to D3, IOL = 500 µ A
0.5
V
VOL2
SYNC, IOL = 100 µ A
0.5
V
High Level Output Leakage Current
ILOH
VO = VDD
10
µA
Low Level Output Leakage Current
ILOL
VO = 0 V
−10
µA
Row Output Impedance
RROW
8
kΩ
RROW/COL
10
kΩ
Column Output Impedance
RCOL
20
kΩ
Supply Current
IDD1
Operation mode, fC = 400 kHz
IDD2
STOP mode, CLK = 0 V
Row/Column Output Impedance
250
µA
20
µA
MAX.
Unit
f = 1 MHz
10
pF
With pins other than that
25
pF
measured at 0 V.
15
pF
150
Capacitance (TA = 25 °C, VDD = 0 V)
Parameter
Input Capacitance
Output Capacitance
I/O Capacitance
Symbol
CIN
COUT
CIO
Conditions
Data Sheet S10299EJ4V0DS00
MIN.
TYP.
53
µ PD16434
AC Characteristics 2 (Unless Otherwise Specified, TA = – 40 °C to + 85 °C, VDD = + 3 V ± 10 %)
Common Operation
Parameter
Clock Operation Frequency
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
800
kHz
fC
20
Clock High Level pulse Width
tWHC
350
ns
Clock Low Level pulse Width
tWLC
350
ns
RESET High Level Width
tHRS
4
µs
/CS↓ → /BUSY Delay Time
tDCSB
CL = 50 pF
4
µs
/CS↑ → /BUSY Float Delay Time
tDCSFB
CL = 50 pF
6
µs
/CS High Level Width
tWHCS
SYNC Load Capacitance
CLSY
Data Set Time (RESET↓)
tSDR
0
µs
Data Hold Time (RESET↓)
tHRD
10
µs
µs
10
100
pF
Serial Input / Output Operation
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
/SCK Period
tCYK
1
µs
/SCK High Level Pulse Width
tWHK
450
ns
/SCK Low Level Pulse Width
tWLK
450
ns
High Level /SCK Hold Time (/BUSY↑)
tHBK
0
ns
SI Set Time (/SCK↑)
tSIK
200
ns
SI Hold Time (/SCK↑)
tHKI
500
ns
/SCK↓ → SO Delay Time
tDKO
CL = 50 pF
400
ns
8th /SCK↑ → /BUSY Delay Time
tDKB
CL = 50 pF
5
µs
/BUSY Low Level Time
tWLB
CL = 50 pF
64
1/fC
C, /D Set Time (1st /SCK↓)
tSDK
0
µs
C, /D Hold Time (8th /SCK↑)
tHKD
4
µs
/CS Hold Time (8th /SCK↑)
tHKCS
6
µs
54
Data Sheet S10299EJ4V0DS00
18
µ PD16434
Parallel Input / Output Operation
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Command Input Set Time (/STB↓)
tA
CL = 80 pF
200
ns
Command Input Hold Time (/STB↓)
tB
CL = 20 pF
180
ns
Data Input Set Time (/STB↑)
tC
CL = 80 pF
450
ns
Data Input Hold Time (/STB↑)
tD
CL = 20 pF
100
ns
Data Output Delay Time
tACC
CL = 80 pF
Data Output Hold Time
tH
CL = 20 pF
/STB Low Level Pulse Width
tSL
2000
ns
/STB High Level Time
tSH
3
µs
/STB Hold Time (/BUSY↑)
tHBS
0
2nd /STB↑ → /BUSY Delay Time
tDSB
/BUSY Low Level Time
tWLB
C, /D Set Time (1st /STB↓)
tSDS
0
µs
C, /D Hold Time (2nd /STB↑)
tHSD
4
µs
/CS Hold Time (2nd /STB↑)
tHSCS
4
µs
CL = 50 pF
Data Sheet S10299EJ4V0DS00
0
18
2000
ns
900
ns
µs
5
µs
64
1/fC
55
µ PD16434
AC timing measurement voltages (except /STB,/SCK, /BUSY)
0.7 VDD
0.7 VDD
Test points
0.3 VDD
0.3 VDD
Clock timing waveforms
1/fc
tWHC
CL
tWLC
RESET input timing waveforms
tHRS
RESET
Interface specification timing waveforms
RESET
tSDR
tHRD
D1,D2
56
Data Sheet S10299EJ4V0DS00
µ PD16434
Serial input / output timing waveforms
tWHCS
/CS
tHKCS
tDCSB
C, /D
Command/data specification
tHKD
tSDK
tDCSBF
VDD−0.5 V
/BUSY
0.45 V
tCYK
tDKB
tHBK
tWLB
tWHK
/SCK
1st
2nd
8th
tWLK
tSIK
SI
tHKI
Serial
data
(MSB)
Serial
data
(LSB)
tDKO
SO
Data Sheet S10299EJ4V0DS00
57
µ PD16434
Parallel input / output timing waveforms
tWHCS
/CS
tHSCS
tDCSB
C, /D
tSDS
tHSD
/BUSY
tHBS
tSH
/STB
1st
tA
D0 to D3
tB
Control
input
2nd
tC
58
tD
Data
input
tACC
D0 to D3
tDSB
tH
Data
output
Data Sheet S10299EJ4V0DS00
tSL
tWLB
tDCSBF
µ PD16434
Data Memory STOP Mode Low Power Supply Voltage Data Retention Characteristics (TA = −40 to +85 °C)
Parameter
Symbol
Data Retention Power Supply
Conditions
MIN.
VDDDR
TYP.
MAX.
2.0
Unit
V
Voltage
Data Retention Power Supply
IDDDR
20
µA
VDDDR + 0.2
V
VDDDR = 2.0 V
Current
Data Retention High Level RESET
VIHDR
0.9 VDDDR
RESET, CLOCK Setup Time
tSRC
10
µs
RESET, CLOCK Hold Time
tHRC
10
µs
Input Voltage
Data retention timing waveforms
Data retention mode
VDD
1
2
2
3
RESET
4
4
CLOCK
tSRC
1
VDDDR
2
VIH1
3
VIHDR
4
VIL
tHRC
Remark All inputs must be set below VDDDR in the data retention mode.
Data Sheet S10299EJ4V0DS00
59
µ PD16434
12. PACKAGE DRAWINGS
µ PD16434G-xxx-12
80-PIN PLASTIC QFP (14x20)
A
B
41
40
64
65
detail of lead end
S
C D
Q
R
25
24
80
1
F
G
H
I
J
M
K
P
S
N
S
L
M
NOTE
ITEM
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
B
C
24.7±0.4
20.0±0.2
14.0±0.2
D
18.7±0.4
F
1.0
G
H
0.8
0.37±0.08
I
J
K
0.15
0.8 (T.P.)
2.35±0.2
L
1.2±0.2
M
0.17 +0.08
−0.07
N
0.15
P
2.05 +0.2
−0.1
Q
0.1±0.1
R
3°+7°
−3°
S
2.45 MAX.
P80G-80-12-3
60
Data Sheet S10299EJ4V0DS00
µ PD16434
★
★
µ PD16434GF-xxx-3B9
80-PIN PLASTIC QFP (14x20)
A
B
41
40
64
65
detail of lead end
S
C D
R
Q
25
24
80
1
F
G
J
H
I
M
K
P
M
N
S
L
NOTE
S
ITEM
Each lead centerline is located within 0.15 mm of
its true position (T.P.) at maximum material condition.
MILLIMETERS
A
23.2±0.2
B
20.0±0.2
C
14.0±0.2
D
17.2±0.2
F
1.0
G
0.8
H
0.37 +0.08
−0.07
I
J
0.15
0.8 (T.P.)
K
1.6±0.2
L
0.8±0.2
M
0.17 +0.08
−0.07
N
0.10
P
2.7±0.1
Q
0.125±0.075
R
5°±5°
S
3.0 MAX.
S80GF-80-3B9-5
Data Sheet S10299EJ4V0DS00
61
µ PD16434
13. RECOMMENDED SOLDERING CONDITIONS
When mounting the µ PD16434 by soldering should be performed under the following recommended conditions.
Should other than recommended conditions be used, consult with our sales personnel.
Surface Mount Type
µ PD16434G-xxx-12
★
: 80-PIN PLASTIC QFP (14 × 20)
µ PD16434GF-xxx-3B9: 80-PIN PLASTIC QFP (14 × 20)
Soldering Method
Soldering Condition
Symbol of Recommended
Soldering Condition
Infrared reflow
Package peak temperature : 235 °C, Time : 30 seconds MAX. (210 MIN.),
IR35-00-2
Number of times : 2 MAX.
VPS
Package peak temperature : 235 °C, Time : 40 seconds MAX. (200 MIN.),
VP-15-00-2
Number of times : 2 MAX.
Wave soldering
Solder path temperature : 260 °C MAX., Time : 10 seconds MAX.,
WS-60-00-1
Number of times : 1,
Preheating temperature : 120 °C MAX. (Package sutface)
★
Partial heating
Pin temperature: 300 °C MAX., Time: 3 seconds MAX. (per side of device)
−
Caution Do not use two or more soldering methods in combination (except the partial heating method).
62
Data Sheet S10299EJ4V0DS00
µ PD16434
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S10299EJ4V0DS00
63
µ PD16434
Reference Documents
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Semiconductor Device Mounting Technology Manual (C10535E)
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8