SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 10-MHz To 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER FEATURES • • • • 100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 66-MHz System Clock Pin-Compatible Superset of DS92LV1023/DS92LV1224 Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHz Synchronization Mode for Faster Lock • • • • • • Lock Indicator No External Components Required for PLL 28-Pin SSOP and Space Saving 5 × 5 mm QFN Packages Available Industrial Temperature Qualified, TA = –40°C to 85°C Programmable Edge Trigger on Clock Flow-Through Pinout for Easy PCB Layout DESCRIPTION The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput. Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters. The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock. AVCC DVCC DVCC DVCC SYNC1 DVCC SYNC2 DIN1 32 31 30 29 28 27 26 25 1 24 AGND DIN2 2 23 PWRDN DIN3 3 22 AGND 21 DO+ 20 DO− 19 AGND DEN RHB Package SN65LV1023A Serializer (Top View) 7 18 DIN8 8 17 9 10 11 12 13 14 15 16 AGND AVCC DIN7 DGND DIN6 6 DGND 5 DGND DIN5 DGND DIN4 4 TCLK DVCC DVCC AVCC AGND PWRDN AGND DO+ DO− AGND DEN AGND AVCC DGND DGND DIN9 1 28 2 27 3 26 4 25 5 24 6 23 7 DB Package 22 SN65LV1023A 8 21 Serializer 9 20 10 19 11 18 12 17 13 16 14 15 TCLK_R/F SYNC1 SYNC2 DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9 TCLK_R/F TCLK DIN0 The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2006, Texas Instruments Incorporated SN65LV1023A SN65LV1224B www.ti.com ROUT2 ROUT1 ROUT0 AGND AGND AGND REFCLK 32 31 30 29 28 27 26 25 1 24 ROUT3 RI+ 2 23 ROUT4 RI− 3 22 DVCC PWRDN 4 21 DGND 20 DVCC 19 DGND AVCC RHB Package SN65LV1224B Deserializer (Top View) ROUT5 AVCC 8 17 9 10 11 12 13 14 15 16 ROUT6 ROUT7 18 ROUT9 LOCK 7 ROUT8 6 DGND RCLK DGND REN 5 AGND ROUT0 ROUT1 ROUT2 ROUT3 ROUT4 DVCC DGND DVCC DGND ROUT5 ROUT6 ROUT7 ROUT8 ROUT9 AVCC 1 28 2 27 3 26 4 25 5 24 6 23 DB Package 22 7 SN65LV1224B 8 21 Deserializer 9 20 10 19 11 18 12 17 13 16 14 15 AGND AGND RCLK_R/F REFCLK AVCC RI+ RI− PWRDN REN RCLK LOCK AVCC AGND AGND DGND RCLK_R/F SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 BLOCK DIAGRAMS SN65LV1023A SN65LV1224B TCLK (10 MHz to 66 MHz) PLL Timing / Control Y+ A− Y− DEN Clock Recovery SYNC1 SYNC2 2 PLL Submit Documentation Feedback 10 Output Latch A+ Serial-to-Parallel TCLK_R/F Input Latch DIN Parallel-to-Serial LVDS 10 Timing / Control DOUT REFCLK REN LOCK RCLK_R/F RCLK (10 MHz to 66 MHz) SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 FUNCTIONAL DESCRIPTION The SN65LV1023A and SN65LV1224B are a 10-bit serializer/deserializer chipset designed to transmit data over differential backplanes or unshielded twisted pair (UTP) at clock speeds from 10 MHz to 66 MHz. The chipset has five states of operation: initialization mode, synchronization mode, data transmission mode, power-down mode, and high-impedance mode. The following sections describe each state of operation. INITIALIZATION MODE Initialization of both devices must occur before data transmission can commence. Initialization refers to synchronization of the serializer and deserializer PLLs to local clocks. When VCC is applied to the serializer and/or deserializer, the respective outputs enter the high-impedance state, while on-chip power-on circuitry disables internal circuitry. When VCC reaches 2.45 V, the PLL in each device begins locking to a local clock. For the serializer, the local clock is the transmit clock (TCLK) provided by an external source. For the deserializer, a local clock must be applied to the REFCLK pin. The serializer outputs remain in the high-impedance state, while the PLL locks to the TCLK. SYNCHRONIZATION MODE The deserializer PLL must synchronize to the serializer in order to receive valid data. Synchronization can be accomplished in one of two ways: • Rapid Synchronization: The serializer has the capability to send specific SYNC patterns consisting of six ones and six zeros switching at the input clock rate. The transmission of SYNC patterns enables the deserializer to lock to the serializer signal within a deterministic time frame. This transmission of SYNC patterns is selected via the SYNC1 and SYNC2 inputs on the serializer. Upon receiving valid SYNC1 or SYNC2 pulse (wider than 6 clock cycles), 1026 cycles of SYNC pattern are sent. When the deserializer detects edge transitions at the LVDS input, it attempts to lock to the embedded clock information. The deserializer LOCK output remains high while its PLL locks to the incoming data or SYNC patterns present on the serial input. When the deserializer locks to the LVDS data, the LOCK output goes low. When LOCK is low, the deserializer outputs represent incoming LVDS data. One approach is to tie the deserializer LOCK output directly to SYNC1 or SYNC2. • Random-Lock Synchronization: The deserializer can attain lock to a data stream without requiring the serializer to send special SYNC patterns. This allows the SN65LV1224B to operate in open-loop applications. Equally important is the deserializer’s ability to support hot insertion into a running backplane. In the open-loop or hot-insertion case, it is assumed the data stream is essentially random. Therefore, because lock time varies due to data stream characteristics, the exact lock time cannot be predicted. The primary constraint on the random lock time is the initial phase relation between the incoming data and the REFCLK when the deserializer powers up. The data contained in the data stream can also affect lock time. If a specific pattern is repetitive, the deserializer could enter false lock—falsely recognizing the data pattern as the start/stop bits. This is referred to as repetitive multitransition (RMT); see Figure 1 for RMT examples. This occurs when more than one low-high transition takes place per clock cycle over multiple cycles. In the worst case, the deserializer could become locked to the data pattern rather than the clock. Circuitry within the deserializer can detect that the possibility of false lock exists. Upon detection, the circuitry prevents the LOCK output from becoming active until the potential false lock pattern changes. Notice that the RMT pattern only affects the deserializer lock time, and once the deserializer is in lock, the RMT pattern does not affect the deserializer state as long as the same data boundary happens each cycle. The deserializer does not go into lock until it finds a unique four consecutive cycles of data boundary (stop/start bits) at the same position. The deserializer stays in lock until it cannot detect the same data boundary (stop/start bits) for four consecutive cycles. Then the deserializer goes out of lock and hunts for the new data boundary (stop/start bits). In the event of loss of synchronization, the LOCK pin output goes high and the outputs (including RCLK) enter a high-impedance state. The user’s system should monitor the LOCK pin in order to detect a loss of synchronization. Upon detection of loss of lock, sending sync patterns for resynchronization is desirable if reestablishing lock within a specific time is critical. However, the deserializer can lock to random data as previously noted. Submit Documentation Feedback 3 SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 FUNCTIONAL DESCRIPTION (continued) DIN0 Held Low and DIN1 Held High Stop Bit Start Bit DIN0 Stop Bit Start Bit Stop Bit Start Bit Stop Bit Start Bit DIN1 DIN4 Held Low and DIN5 Held High Stop Bit Start Bit DIN4 DIN5 DIN8 Held Low and DIN9 Held High Stop Bit Start Bit DIN8 DIN9 Figure 1. RMT Pattern Examples DATA TRANSMISSION MODE After initialization and synchronization, the serializer accepts parallel data from inputs DIN0–DIN9. The serializer uses the TCLK input to latch the incoming data. The TCLK_R/F pin selects which edge the serializer uses to strobe incoming data. If either of the SYNC inputs is high for six TCLK cycles, the data at DIN0–DIN9 is ignored regardless of the clock edge selected and 1026 cycles of SYNC pattern are sent. After determining which clock edge to use, a start and stop bit, appended internally, frames the data bits in the register. The start bit is always high and the stop bit is always low. The start and stop bits function as the embedded clock bits in the serial stream. The serializer transmits serialized data and appended clock bits (10+2 bits) from the serial data output (DO±) at 12 times the TCLK frequency. For example, if TCLK is 66 MHz, the serial rate is 66 × 12 = 792 Mbps. Because only 10 bits are input data, the useful data rate is 10 times the TCLK frequency. For instance, if TCLK = 66 MHz, the useful data rate is 66 × 10 = 660 Mbps. The data source, which provides TCLK, must be in the range of 10 MHz to 66 MHz. The serializer outputs (DO±) can drive point-to-point connections or limited multipoint or multidrop backplanes. The outputs transmit data when the enable pin (DEN) is high, PWRDN = high, and SYNC1 and SYNC2 are low. When DEN is driven low, the serializer output pins enter the high-impedance state. 4 Submit Documentation Feedback SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 FUNCTIONAL DESCRIPTION (continued) Once the deserializer has synchronized to the serializer, the LOCK pin transitions low. The deserializer locks to the embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low, otherwise ROUT0–ROUT9 is invalid. The ROUT0–ROUT9 data is strobed out by RCLK. The specific RCLK edge polarity to be used is selected by the RCLK_R/F input. The ROUT0–ROUT9, LOCK and RCLK outputs can drive a maximum of three CMOS input gates (15-pF load. total for all three) with a 66-MHz clock. POWER DOWN When no data transfer is required, the power-down mode can be used. The serializer and deserializer use the power-down state, a low-power sleep mode, to reduce power consumption. The deserializer enters power down when you drive PWRDN and REN low. The serializer enters power down when you drive PWRDN low. In power down, the PLL stops and the outputs enter a high-impedance state, which disables load current and reduces supply current to the milliampere range. To exit power down, you must drive the PWRDN pin high. Before valid data exchanges between the serializer and deserializer can resume, you must reinitialize and resynchronize the devices to each other. Initialization of the serializer takes 1026 TCLK cycles. The deserializer initialize and drives LOCK high until lock to the LVDS clock occurs. HIGH-IMPEDANCE MODE The serializer enters the high-impedance mode when the DEN pin is driven low. This puts both driver output pins (DO+ and DO–) into a high-impedance state. When you drive DEN high, the serializer returns to the previous state, as long as all other control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F). When the REN pin is driven low, the deserializer enters high-impedance mode. Consequently, the receiver output pins (ROUT0–ROUT9) and RCLK are placed into the high-impedance state. The LOCK output remains active, reflecting the state of the PLL. Deserializer Truth Table INPUTS (1) (2) (3) OUTPUTS PWRDN REB ROUT(0:9) (1) H H Z H H L X H L LOCK (2) RCLK (3) (1) H Z Active L Active Z Z Z Z Active Z ROUT and RCLK are 3-stated when LOCK is asserted high. LOCK output reflects the state of the deserializer with regard to the selected data stream. RCLK active indicates the RCLK is running if the deserializer is locked. The timing of RCLK with respect to ROUT is determined by RCLK_R/F. FAILSAFE BIASING FOR THE SN65LV1224B The SN65LV1224B has an input threshold sensitivity of ±50 mV. This allows for greater differential noise margin in the SN65LV1224B. However, in cases where the receiver input is not being actively driven, the increased sensitivity of the SN65LV1224B can pickup noise as a signal and cause unintentional locking. This may occur when the input cable is disconnected. The SN65LV1224B has an on-chip fail-safe circuit that drives the serial input and LOCK signal high. The response time of the fail-safe circuit depends on interconnect characteristics. Submit Documentation Feedback 5 SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 TERMINAL FUNCTIONS PIN DB PACKAGE RHB PACKAGE I/O DESCRIPTION SERIALIZER 18, 20, 23, 25 17, 19, 22, 24 AGND Analog circuit ground (PLL and analog circuits) 17, 26 16, 25 AVCC Analog circuit power supply (PLL and analog circuits) 19 18 DEN LVTTL logic input. Low puts the LVDS serial output into the high-impedance state. High enables serial data output. 15, 16 12, 13, 14, 15 DGND 3–12 32, 1–9 DIN0 – DIN9 21 20 DO– Inverting LVDS differential output 22 21 DO+ Noninverting LVDS differential output 27, 28 26, 27, 28, 29 DVCC Digital circuit power supply 24 23 PWRDN LVTTL logic input. Asserting this pin low turns off the PLL and places the outputs into the high-impedance state, putting the device into a low-power mode. LVTTL logic inputs SYNC1 and SYNC2 are ORed together. When at least one of the two pins is asserted high for 6 cycles of TCLK, the serializer initiates transmission of a minimum 1026 SYNC patterns. If after completion of the transmission of 1026 patterns SYNC continues to be asserted, then the transmission continues until SYNC is driven low and if the time SYNC holds > 6 cycles, another 1026 SYNC pattern tranmission initiates. Digital circuit ground Parallel LVTTL data inputs 1, 2 30, 31 SYNC1, SYNC2 13 10 TCLK_R/F 14 11 TCLK LVTTL-level reference clock input. The SN65LV1023A accepts a 10-MHz to 66-MHz clock. TCLK strobes parallel data into the input latch and provides a reference frequency to the PLL. 1, 12, 13 10, 11, 28, 29, 30 AGND Analog circuit ground (PLL and analog circuits) 4, 11 1, 8, 9 AVCC Analog circuit power supply (PLL and analog circuits) 14, 20, 22 12, 13, 19, 21 DGND Digital circuit ground 21, 23 20, 22 DVCC Digital circuit power supply 10 7 LOCK LVTTL level output. LOCK goes low when the deserializer PLL locks onto the embedded clock edge. LVTTL logic input. Low selects a TCLK falling-edge data strobe; high selects a TCLK rising-edge data strobe. DESERIALIZER 6 LVTTL logic input. Asserting this pin low turns off the PLL and places outputs into a high-impedance state, putting the device into a low-power mode. To initiate power down, this pin is held low for a minimum of 16 ns. As long as PWRDN is held low, the device is in the power down state. 7 4 PWRDN 2 31 RCLK_R/F 9 6 RCLK 3 32 REFCLK LVTTL logic input. Use this pin to supply a REFCLK signal for the internal PLL frequency. 8 5 REN LVTTL logic input. Low places ROUT0–ROUT9 and RCLK in the high-impedance state. 5 2 RI+ Serial data input. Noninverting LVDS differential input Serial data input. Inverting LVDS differential input LVTTL logic input. Low selects an RCLK falling-edge data strobe; high selects an RCLK rising-edge data strobe. LVTTL level output recovered clock. Use RCLK to strobe ROUTx. 6 3 RI– 28–24, 19–15 27–23, 18–14 ROUT0–ROUT9 Parallel LVTTL data outputs Submit Documentation Feedback SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VCC to GND –0.3 V to 4 V LVTTL input voltage –0.3 V to (VCC + 0.3 V) LVTTL output voltage –0.3 V to (VCC + 0.3 V) LVDS receiver input voltage –0.3 V to 3.9 V LVDS driver output voltage –0.3 V to 3.9 V LVDS output short circuit duration Electrostatic discharge: 10 ms HBM up to 6 kV MM up to 200 V Junction temperature 150°C Storage temperature –65°C to 150°C Lead temperature (soldering, 4 seconds) 260°C DB package maximum package power dissipation TA = 25°C 1.27 W RHB package maximum package TA = 25°C power dissipation 2.85 W DB package derating 10.3 mW/°C above 25°C RHB package derating 23.6 mW/°C above 25°C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VCC VCM (1) MIN NOM MAX Supply voltage 3 3.3 3.6 V Receiver input voltage range 0 2.4 V ID 2 V Receiver input common mode range V V 2.4 Supply noise voltage TA (1) ID 2 100 Operating free-air temperature –40 25 UNIT mVp-p °C By design, DVCC and AVCC are separated internally and does not matter what the difference is for |DVCC–AVCC|, as long as both are within 3 V to 3.6 V. Submit Documentation Feedback 7 SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 ELECTRICAL CHARACTERISTICS over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC V 0.8 V SERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (1) VIH High-level input voltage VIL Low-level input voltage VCL Input clamp voltage IIN Input current, (2) 2 GND ICL = –18 mA VIN = 0 V or 3.6 V –200 -0.86 –1.5 V ±100 200 µA DESERIALIZER LVCMOS/LVTTL DC SPECIFICATIONS (3) VIH High-level input voltage 2 VCC V VIL Low-level input voltage GND 0.8 V VCL Input clamp voltage ICL = –18 mA IIN Input current (pull-up and pull-down resistors on inputs) VIN = 0 V or 3.6 V VOH High-level output voltage IOH = –5 mA VOL Low-level output voltage IOS Output short-circuit current IOZ High-impedance output current -0.62 –200 –1.5 V 200 µA VCC V 2.2 3 IOL = 5 mA GND 0.25 0.5 V VOUT = 0 V –15 –47 –85 mA PWRDN or REN = 0.8 V, VOUT = 0 V or VCC –10 ±1 10 µA 350 450 SERIALIZER LVDS DC SPECIFICATIONS (Apply to Pins DO+ and DO–) RL = 27 Ω, See Figure 19 VOD Output differential voltage (DO+)–(DO–) ∆VOD Output differential voltage unbalance VOS Offset voltage ∆VOS Offset voltage unbalance IOS Output short circuit current D0 = 0 V, DINx = high, PWRDN and DEN = 2.4 V IOZ High-impedance output current PWRDN or DEN = 0.8 V, DO = 0 V or VCC IOX Power-off output current VCC = 0 V, DO = 0 V or 3.6 V CO Output single-ended capacitance mV 35 1.1 mV 1.2 1.3 V 4.8 35 mV -10 -90 mA –10 ±1 10 µA -20 ±1 25 µA 1±20% pF 50 mV DESERIALIZER LVDS DC SPECIFICATIONS (Apply to Pins RI+ and RI–) VTH Differential threshold high voltage VTL Differential threshold low voltage IIN Input current CI Input single-ended capacitance VCM = 1.1 V –50 mV VIN = 2.4 V, VCC = 3.6 V or 0 V –10 ±1 15 VIN = 0 V, VCC = 3.6 V or 0 V –10 ±0.05 10 0.5±20 % µA pF SERIALIZER SUPPLY CURRENT (Applies to Pins DVCC and AVCC) ICCD Serializer supply current worst case RL = 27 Ω, See Figure 4 ICCXD Serializer supply current PWRDN = 0.8 V f = 10 MHz 20 25 f = 66 MHz 55 70 200 500 f = 10 MHz 15 35 f = 66 MHz 80 95 0.36 1 mA µA DESERIALIZER SUPPLY CURRENT (applies to pins DVCC and AVCC) ICCR Deserializer supply current, worst case ICCXR Deserializer supply current, power down (1) (2) (3) 8 CL = 15 pF, See Figure 4 PWRDN = 0.8 V, REN = 0.8 V Apply to DIN0–DIN9, TCLK, PWRDN, TCLK_R/F, SYNC1, SYNC2, and DEN High IIN values are due to pullup and pulldown resistors on the inputs. Apply to pins PWRDN, RCLK_R/F, REN, and REFCLK = inputs; apply to pins ROUTx, RCLK, and LOCK = outputs Submit Documentation Feedback mA mA SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 SERIALIZER TIMING REQUIREMENTS FOR TCLK over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER MIN TYP MAX UNIT 15.15 T 100 ns Transmit clock high time 0.4T 0.5T 0.6T ns tTCIL Transmit clock low time 0.4T 0.5T 0.6T ns tt(CLK) TCLK input transition time 3 6 tJIT TCLK input jitter tTCP Transmit clock period tTCIH TEST CONDITIONS See Figure 18 Frequency tolerance ns 150 ps (RMS) +100 ppm TYP MAX UNIT 0.2 0.4 ns 0.25 0.4 ns -100 SERIALIZER SWITCHING CHARACTERISTICS over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER tTLH(L) LVDS low-to-high transition time tLTHL(L) LVDS high-to-low transition time tsu(DI) DIN0–DIN9 setup to TCLK tsu(DI) DIN0–DIN9 hold from TCLK td(HZ) DO± high-to-high impedance state delay td(LZ) DO± low-to-high impedance state delay td(ZH) TEST CONDITIONS MIN RL = 27 Ω, CL = 10 pF to GND, See Figure 5 RL = 27 Ω, CL = 10 pF to GND, See Figure 8 0.5 ns 4 RL = 27 Ω, CL = 10 pF to GND, See Figure 9 ns 2.5 5 2.5 5 DO± high-to-high impedance state-tohigh delay 5 10 td(ZL) DO± high-to-high impedance state-to-low delay 6.5 10 tw(SPW) SYNC pulse duration t(PLD) Serializer PLL lock time td(S) Serializer delay RL = 27 Ω, See Figure 12 tDJIT Deterministic jitter RL = 27 Ω, CL = 10 pF to GND RL = 27 Ω, See Figure 11 6×tTCP ns 1026×tTCP tTCP+1 ns tTCP+2 tTCP+3 230 150 tRJIT Random jitter RL = 2.7 Ω, CL = 10 pF to GND ns 10 19 ns ps ps (RMS) DESERIALIZER TIMING REQUIREMENTS FOR REFCLK over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER tRFCP REFCLK period tRFDC REFCLK duty cycle tt(RF) REFCLK transition time TEST CONDITIONS MIN TYP MAX UNIT 15.15 T 100 ns 30% 50% 70% 3 Frequency tolerance -100 Submit Documentation Feedback 6 +100 ns ppm 9 SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 DESERIALIZER SWITCHING CHARACTERISTICS over recommended operating supply and temperature ranges (unless otherwise specified) PARAMETER t(RCP) Receiver out clock period tTLH(C) CMOS/TTL low-to-high transition time tTHL(C) CMOS/TTL high-to-low transition time td(D) (1) Deserializer delay, See Figure 13 t(ROS) TEST CONDITIONS t(RCP) = t(TCP), See Figure 12 CL = 15 pF,CL = 15 pF, See Figure 6 PIN/FREQ RCLK MIN TYP 15.15 ROUT0–ROUT9 , LOCK, RCLK MAX UNIT 100 ns 1.2 2.5 1.1 2.5 Room temperature, 10 MHz 3.3 V 1.75×t(RCP) +4.2 1.75×t(RCP) +12.6 66 MHz 1.75×t(RCP) +7.4 1.75×t(RCP) +9.7 ROUTx data valid before RCLK See Figure 14 ns ns ns RCLK 10 MHz 0.4×t(RCP) 0.5×t(RCP) RCLK 66 MHz 0.4×t(RCP) 0.5×t(RCP) 10 MHz –0.4×t(RCP) –0.5×t(RCP) 66 MHz –0.4×t(RCP) –0.5×t(RCP) 40% 50% 60% ns ns t(ROH) ROUTx data valid after RCLK t(RDC) RCLK duty cycle td(HZ) High-to-high impedance state delay 6.5 8 ns td(LZ) Low-to-high impedance state delay 4.7 8 ns td(HR) High-impedance state to high delay 5.3 8 ns td(ZL) High-impedance state to low delay 4.7 8 ns t(DSR1) Deserializer PLL lock time from PWRDN (with SYNCPAT) t(DSR2) Deserializer PLL lock time from SYNCPAT td(ZHLK) High-impedance state to high delay (power up) tRNM Deserializer noise margin (1) (2) (3) 10 See Figure 15 See Figure 16, Figure 17, and (2) ROUT0–ROUT9 10 MHz 850 x tRFCP 66 MHz 850 x tRFCP 10 MHz 2 66 MHz 0.303 LOCK See Figure 18 and (3) 3 10 MHz 3680 66 MHz 540 µs ns ps The deserializer delay time for all frequencies does not exceed two serial bit times. t(DSR1) represents the time required for the deserializer to register that a lock has occurred upon powerup or when leaving the powerdown mode. t(DSR2) represents the time required to register that a lock has occurred for the powered up and enabled deserializer when the input (RI±) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). In order to specify deserializer PLL performance, tDSR1 and tDSR2 are specified with REFCLK active and stable and specific conditions of SYNCPATs. tRNM represents the phase noise or jitter that the deserializer can withstand in the incoming data stream before bit errors occur. Submit Documentation Feedback SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 TIMING DIAGRAMS AND TEST CIRCUITS TCLK ODD DIN EVEN DIN Figure 2. Worst-Case Serializer ICC Test Pattern SUPPLY CURRENT vs TCLK FREQUENCY 60 66 mA, 48.880 MHz ICC − Supply Current − mA 50 40 ICC 30 20 10 mA, 14.732 MHz 10 0 0 20 40 60 80 TCLK Frequency − MHz Figure 3. Submit Documentation Feedback 11 SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 TIMING DIAGRAMS AND TEST CIRCUITS (continued) RCLK ODD ROUT EVEN ROUT Figure 4. Worst-Case Deserializer ICC Test Pattern 10 pF tTLH(L) DO+ tTHL(L) RL 80% Vdiff 80% 20% 20% DO− 10 pF Vdiff = (DO+) − (DO−) Figure 5. Serializer LVDS Output Load and Transition Times CMOS/TTL Output Deserializer tTHL(C) tTLH(C) 80% 15 pF 80% 20% 20% Figure 6. Deserializer CMOS/TTL Output Load and Transition Times tt(CLK) TCLK tt(CLK) 90% 10% 90% 10% 3V 0V Figure 7. Serializer Input Clock Transition Time 12 Submit Documentation Feedback SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 TIMING DIAGRAMS AND TEST CIRCUITS (continued) tTCP 1.5 V TCLK 1.5 V For TCLK_R/F = Low 1.5 V th(DI) tsu(DI) DIN [9:0] 1.5 V Setup Hold 1.5 V Figure 8. Serializer Setup/Hold Times Parasitic Package and Trace Capacitance 3V DEN 1.5 V 1.5 V 0V td(ZH) td(HZ) VOH 13.5 Ω DO+ 50% 1.1 V DO− DO± 50% 1.1 V td(ZL) td(LZ) 13.5 Ω DEN 1.1 V 50% 50% VOL Figure 9. Serializer High-Impedance State Test Circuit and Timing PWRDN 2V 0.8 V 1026 Cycles td(HZ) or td(LZ) TCLK td(ZH) or td(ZL) tPLD DO± 3-State Output Active 3-State Figure 10. Serializer PLL Lock Time and PWRDN High-Impedance State Delays Submit Documentation Feedback 13 SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 TIMING DIAGRAMS AND TEST CIRCUITS (continued) REN PWRDN TCLK tw(SP) SYNC1 or SYNC2 DO± DATA SYNC Pattern TCLK SYNC1 or SYNC2 tw(SP) Min. Timing Met DO± SYNC Pattern DATA Figure 11. SYNC Timing Delays DIN DIN0 − DIN9 SYMBOL N DIN0 − DIN9 SYMBOL N+1 td(S) TCLK Timing for TCLK_R/F = High Start D00 − D09 SYMBOL N−1 Bit Stop Start Bit Bit DO Figure 12. Serializer Delay 14 Submit Documentation Feedback D00 − D09 SYMBOL N Stop Bit SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 TIMING DIAGRAMS AND TEST CIRCUITS (continued) Start Bit D00 − D09 SYMBOL N Stop Start Bit Bit D00 − D09 SYMBOL N+1 Stop Start Bit Bit D00 − D09 SYMBOL N+2 Stop Bit RI 1.2 V 1V tDD RCLK Timing for TCLK_R/F = High ROUT ROUT0 − ROUT9 SYMBOL N−1 ROUT0 − ROUT9 SYMBOL N ROUT0 − ROUT9 SYMBOL N+1 Figure 13. Deserializer Delay tLow tHigh RCLK RCLK_R/F = Low tHigh tLow RCLK RCLK_R/F = High tROH tROS ROUT [9:0] 1.5 V Data Valid Before RCLK Data Valid After RCLK 1.5 V Figure 14. Deserializer Data Valid Out Times 7 V x (LZ/ZL), Open (HZ/ZH) VOH REN 500 Ω 450 Ω 1.5 V 1.5 V VOL Scope td(LZ) VOL + 0.5 V 50 Ω td(ZL) VOL + 0.5 V VOL ROUT[9:0] td(HZ) td(ZH) VOH VOH − 0.5 V VOH − 0.5 V Figure 15. Deserializer High-Impedance State Test Circuit and Timing Submit Documentation Feedback 15 SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 TIMING DIAGRAMS AND TEST CIRCUITS (continued) PWRDN 2V 0.8 V REFCLK 1.5 V t(DSR1) DATA RI± Not Important td(ZHL) LOCK SYNC Patterns 3-State 3-State td(HZ) or td(LZ) td(ZH) or td(ZL) ROUT[9:0] 3-State 3-State SYNC Symbol or DIN[9:0] RCLK 3-State 3-State RCLK_R/F = Low REN Figure 16. Deserializer PLL Lock Times and PWRDN 3-State Delays 16 Submit Documentation Feedback SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 TIMING DIAGRAMS AND TEST CIRCUITS (continued) 3.6 V 3V VCC 0V PWRDN 0.8 V REFCLK t(DSR2) DATA 1.2 V RI± Not Important 1V SYNC Patterns LOCK 3-State td(ZH) or td(ZL) ROUT[9:0] td(HZ) or td(LZ) 3-State 3-State SYNC Symbol or DIN[9:0] RCLK 3-State 3-State REN Figure 17. Deserializer PLL Lock Time From SyncPAT 1.2 V VTH RI± VTL 1V tDJIT tDJIT tRNM tRNM tSW Ideal Sampling Position tSW: Setup and Hold Time (Internal Data Sampling Window) tDJIT: Serializer Output Bit Position Jitter That Results From Jitter on TCLK tRNM: Receiver Noise Margin Time Figure 18. Receiver LVDS Input Skew Margin Submit Documentation Feedback 17 SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 TIMING DIAGRAMS AND TEST CIRCUITS (continued) DO+ RL 10 DIN Parallel-to-Serial DO− > TCLK VOD = (DO+) − (DO−) Differential Output Signal Is Shown as (DO+) − (DO−) Figure 19. VOD Diagram DEVICE STARTUP PROCEDURE It is recommended that the PWRDNB pin on both the SN65LV1023A and the SN65LV1224B device be held to a logic LOW level until after the power supplies have powered up to at least 3 V as shown in Figure 20. 3.0 V VDD PWRDNB Figure 20. Device Startup 18 Submit Documentation Feedback SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 APPLICATION INFORMATION DIFFERENTIAL TRACES AND TERMINATION The performance of the SN65LV1023A/SN65LV1224B is affected by the characteristics of the transmission medium. Use controlled-impedance media and termination at the receiving end of the transmission line with the media’s characteristics impedance. Use balanced cables such as twisted pair or differential traces that are ran close together. A balanced cable picks up noise together and appears to the receiver as common mode. Differential receivers reject common-mode noise. Keep cables or traces matched in length to help reduce skew. Running the differential traces close together helps cancel the external magnetic field, as well as maintain a constant impedance. Avoiding sharp turns and reducing the number of vias also helps. TOPOLOGIES There are several topologies that the serializers can operate. Three common examples are shown below. Figure 21 shows an example of a single-terminated point-to-point connection. Here a single termination resistor is located at the deserializer end. The resistor value should match that of the characteristic impedance of the cable or PC board traces. The total load seen by the serializer is 100 Ω. Double termination can be used and typically reduces reflections compared with single termination. However, it also reduces the differential output voltage swing. AC-coupling is only recommended if the parallel TX data stream is encoded to achieve a dc-balanced data stream. Otherwise the ac-capicitors can induce common mode voltage drift due to the dc-unbalanced data stream. Serialized Data 100 Ω Parallel Data In Parallel Data Out Figure 21. Single-Terminated Point-to-Point Connection Figure 22 shows an example of a multidrop configuration. Here there is one transmitter broadcasting data to multiple receivers. A 50-kΩ resistor at the far end terminates the bus. ASIC ASIC ASIC ASIC 50 Ω Figure 22. Multidrop Configuration Figure 23 shows an example of multiple serializers and deserializers on the same differential bus, such as in a backplane. This is a multipoint configuration. In this situation, the characteristic impedance of the bus can be significantly less due to loading. Termination resistors that match the loaded characteristic impedance are required at each end of the bus. The total load seen by the serializer in this example is 27 Ω. Submit Documentation Feedback 19 SN65LV1023A SN65LV1224B www.ti.com SLLS621C – SEPTEMBER 2004 – REVISED FEBRUARY 2006 APPLICATION INFORMATION (continued) ASIC ASIC ASIC 54 Ω ASIC 54 Ω Figure 23. Multiple Serializers and Deserializers on the Same Differential Bus 20 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65LV1023ADB ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LV1023ADBG4 ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LV1023ADBR ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LV1023ADBRG4 ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LV1023ARHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LV1023ARHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LV1023ARHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LV1224BDB ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LV1224BDBG4 ACTIVE SSOP DB 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LV1224BDBR ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LV1224BDBRG4 ACTIVE SSOP DB 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65LV1224BRHBR ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LV1224BRHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LV1224BRHBT ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN65LV1224BRHBTG4 ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SNLV1023ARHBTG4 ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LV1023ADBR DB 28 SITE 60 330 16 8.1 10.4 2.5 12 16 Q1 SN65LV1023ARHBR RHB 32 SITE 60 330 12 5.3 5.3 1.5 8 12 Q2 SN65LV1023ARHBT RHB 32 SITE 60 330 12 5.3 5.3 1.5 8 12 Q2 SN65LV1224BDBR DB 28 SITE 60 330 16 8.1 10.4 2.5 12 16 Q1 SN65LV1224BRHBR RHB 32 SITE 60 330 12 5.3 5.3 1.5 8 12 Q2 SN65LV1224BRHBT RHB 32 SITE 60 330 12 5.3 5.3 1.5 8 12 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 4-Oct-2007 Package Pins Site Length (mm) Width (mm) Height (mm) SN65LV1023ADBR DB 28 SITE 60 346.0 346.0 33.0 SN65LV1023ARHBR RHB 32 SITE 60 342.9 336.6 20.64 SN65LV1023ARHBT RHB 32 SITE 60 342.9 336.6 20.64 SN65LV1224BDBR DB 28 SITE 60 346.0 346.0 33.0 SN65LV1224BRHBR RHB 32 SITE 60 342.9 336.6 20.64 SN65LV1224BRHBT RHB 32 SITE 60 342.9 336.6 20.64 Pack Materials-Page 2 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. 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