PD - 94591
AUTOMOTIVE MOSFET
HEXFET® Power MOSFET
Benefits
●
●
●
●
●
●
IRF1302
Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
D
VDSS = 20V
RDS(on) = 4.0mΩ
G
S
ID = 180A
Description
Specifically designed for Automotive applications, this Stripe Planar
design of HEXFET® Power MOSFET utilizes the lastest processing
techniques to achieve extremely low on-resistance per silicon area.
Additional features of this design are a 175°C junction operating
temperature, fast switching speed and improved repetitive avalanche
rating. These benefits combine to make this design an extremely efficient
and reliable device for use in Automotive applications and a wide variety
of other applications.
TO-220AB
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
Units
180
130
700
230
1.5
± 20
350
See Fig.12a, 12b, 15, 16
TBD
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
Thermal Resistance
Parameter
RθJC
RθCS
RθJA
www.irf.com
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient (PCB mount)
Typ.
Max.
Units
–––
0.50
–––
0.65
–––
62
°C/W
1
10/31/02
IRF1302
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
20
–––
–––
2.0
59
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.021
3.3
–––
–––
–––
–––
–––
–––
79
18
31
28
130
47
16
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
4.5
LS
Internal Source Inductance
–––
7.5
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
–––
–––
–––
–––
3600
2370
520
5710
2370
3540
V(BR)DSS
∆V(BR)DSS/∆TJ
IGSS
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
4.0
mΩ VGS = 10V, ID = 104A
4.0
V
VDS = 10V, ID = 250µA
–––
S
VDS = 15V, ID = 104A
20
VDS = 20V, VGS = 0V
µA
250
VDS = 16V, VGS = 0V, TJ = 150°C
200
VGS = 20V
nA
-200
VGS = -20V
120
ID = 104A
27
nC
VDS = 16V
46
VGS = 10V
–––
VDD = 11V
–––
ID = 104A
ns
–––
RG = 4.5Ω
–––
VGS = 10V
D
Between lead,
–––
6mm (0.25in.)
nH
G
from package
–––
and center of die contact
S
–––
VGS = 0V
–––
pF
VDS = 25V
–––
ƒ = 1.0MHz, See Fig. 5
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 16V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 16V
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
2
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 180
showing the
A
G
integral reverse
––– ––– 700
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 104A, VGS = 0V
––– 66 100
ns
TJ = 25°C, IF = 104A
––– 130 200
nC
di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
www.irf.com
IRF1302
10000
10000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
1000
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
100
10
4.5V
1000
100
4.5V
10
20µs PULSE WIDTH
Tj = 175°C
20µs PULSE WIDTH
Tj = 25°C
1
1
0.1
1
10
0.1
100
1
Fig 1. Typical Output Characteristics
T J = 175°C
100.00
T J = 25°C
VDS = 15V
20µs PULSE WIDTH
5.0
6.0
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
www.irf.com
7.0
I D = 174A
1.5
(Normalized)
RDS(on) , Drain-to-Source On Resistance
ID, Drain-to-Source Current (Α )
2.0
4.0
100
Fig 2. Typical Output Characteristics
1000.00
10.00
10
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
80
TJ , Junction Temperature
100 120 140 160 180
( ° C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF1302
12
100000
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
VGS , Gate-to-Source Voltage (V)
C, Capacitance(pF)
Ciss
Coss
1000
Crss
VDS = 16V
10
Coss = Cds + Cgd
10000
I D = 104A
7
5
2
100
0
1
10
0
100
20
40
60
80
100
QG, Total Gate Charge (nC)
VDS, Drain-to-Source Voltage (V)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
10000
1000
TJ = 175 ° C
100
I SD , Reverse Drain Current (A)
ID , Drain-to-Source Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100µsec
100
10
TJ = 25 ° C
1
V GS = 0 V
0.1
0.2
0.7
1.2
1.7
V SD,Source-to-Drain Voltage (V)
2.2
1msec
10
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
1
1
10
100
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
Fig 8. Maximum Safe Operating Area
www.irf.com
IRF1302
200
RD
VDS
LIMITED BY PACKAGE
VGS
D.U.T.
RG
150
+
I D , Drain Current (A)
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
100
Fig 10a. Switching Time Test Circuit
50
VDS
90%
0
25
50
75
100
125
150
175
TC, Case Temperature (°C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
(Z thJC)
1
D = 0.50
Thermal Response
0.20
0.1
0.10
P DM
0.05
0.02
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
0.01
Notes:
1. Duty factor D =
2. Peak T
0.01
0.00001
0.0001
0.001
0.01
t1 / t 2
J = P DM x Z thJC
+T C
0.1
1
t1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
www.irf.com
5
IRF1302
700
15V
ID
43A
74A
TOP
+
V
- DD
IAS
20V
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
A
EAS , Single Pulse Avalanche Energy (mJ)
D.U.T
RG
560
DRIVER
L
VDS
BOTTOM
104A
420
280
140
0
25
50
75
100
125
Starting Tj, Junction Temperature
150
175
( ° C)
I AS
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
10 V
QGD
4.0
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
VGS(th) Gate threshold Voltage (V)
QGS
3.0
ID = 250µA
2.0
1.0
-75 -50 -25
VGS
0
25
50
75
100 125 150 175
T J , Temperature ( °C )
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage Vs. Temperature
www.irf.com
IRF1302
1000
Duty Cycle = Single Pulse
Avalanche Current (A)
0.01
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses
100
0.05
0.10
10
1
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
410
TOP
Single Pulse
BOTTOM 10% Duty Cycle
ID = 104A
EAR , Avalanche Energy (mJ)
360
310
260
210
160
110
60
10
25
50
75
100
125
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
Vs. Temperature
www.irf.com
150
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
t av = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = ∆T/ ZthJC
∆T/ [1.3·BV·Zth]
Iav = 2∆
EAS (AR) = PD (ave)·tav
7
IRF1302
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T*
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
RG
VGS
*
+
+
-
VDD
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
[ ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 17. For N-channel HEXFET® power MOSFETs
8
www.irf.com
IRF1302
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
10.29 (.405)
2.87 (.113)
2.62 (.103)
-B-
3.78 (.149)
3.54 (.139)
4.69 (.185)
4.20 (.165)
-A-
1.32 (.052)
1.22 (.048)
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
1.15 (.045)
MIN
1
2
14.09 (.555)
13.47 (.530)
4.06 (.160)
3.55 (.140)
3X
3X
LEAD ASSIGNMENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
3
1.40 (.055)
1.15 (.045)
0.93 (.037)
0.69 (.027)
0.36 (.014)
3X
M
B A M
0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
EXAMPLE: THIS IS AN IRF1010
LOT CODE 1789
ASSEMBLED ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
INTERNATIONAL
RECTIFIER
LOGO
ASSEMBLY
LOT CODE
PART NUMBER
DATE CODE
YEAR 7 = 1997
WEEK 19
LINE C
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Starting TJ = 25°C, L = 0.063mH
R G = 25Ω, IAS = 104A. (See Figure 12).
ISD ≤ 104A, di/dt ≤ 100A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the same charging
time as Coss while VDS is rising from 0 to 80% VDSS .
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 75A.
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This is applied to D2Pak, when mounted on 1" square PCB ( FR4 or G-10 Material ). For recommended footprint and soldering
techniques refer to application note #AN-994.
TO-220 package is not recommended for Surface Mount Application.
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.10/02
www.irf.com
9