PD - 94972
IRF3808PbF
AUTOMOTIVE MOSFET
HEXFET® Power MOSFET
Typical Applications
●
●
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Integrated Starter Alternator
42 Volts Automotive Electrical Systems
Lead-Free
D
Benefits
●
●
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Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Repetitive Avalanche Allowed up to Tjmax
VDSS = 75V
RDS(on) = 0.007Ω
G
ID = 140A
S
Description
Designed specifically for Automotive applications, this Advanced
Planar Stripe HEXFET ® Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon
area. Additional features of this HEXFET power MOSFET are a 175°C
junction operating temperature, low RθJC, fast switching speed and
improved repetitive avalanche rating. This combination makes the
design an extremely efficient and reliable choice for use in higher
power Automotive electronic systems and a wide variety of other
applications.
TO-220AB
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting Torque, 6-32 or M3 screw
Max.
Units
140
97
550
330
2.2
± 20
430
82
See Fig.12a, 12b, 15, 16
5.5
-55 to + 175
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
RθJC
RθCS
RθJA
Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Junction-to-Ambient
Typ.
Max.
Units
–––
0.50
–––
0.45
–––
62
°C/W
HEXFET(R) is a registered trademark of International Rectifier.
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1
02/02/04
IRF3808PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
75
–––
–––
2.0
100
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.086
5.9
–––
–––
–––
–––
–––
–––
150
31
50
16
140
68
120
IDSS
Drain-to-Source Leakage Current
LD
Internal Drain Inductance
–––
4.5
LS
Internal Source Inductance
–––
7.5
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
–––
–––
–––
–––
5310
890
130
6010
570
1140
V(BR)DSS
∆V(BR)DSS/∆TJ
IGSS
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
7.0
mΩ VGS = 10V, ID = 82A
4.0
V
VDS = 10V, ID = 250µA
–––
S
VDS = 25V, ID = 82A
20
VDS = 75V, VGS = 0V
µA
250
VDS = 60V, VGS = 0V, TJ = 150°C
200
VGS = 20V
nA
-200
VGS = -20V
220
ID = 82A
47
nC
VDS = 60V
76
VGS = 10V
–––
VDD = 38V
–––
ID = 82A
ns
–––
RG = 2.5Ω
–––
VGS = 10V
D
Between lead,
–––
6mm (0.25in.)
nH
G
from package
–––
and center of die contact
S
–––
VGS = 0V
–––
pF
VDS = 25V
–––
ƒ = 1.0MHz, See Fig. 5
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 60V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 60V
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 140
showing the
A
G
integral reverse
––– ––– 550
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 82A, VGS = 0V
––– 93 140
ns
TJ = 25°C, IF = 82A
––– 340 510
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Starting TJ = 25°C, L = 0.130mH
RG = 25Ω, IAS = 82A. (See Figure 12).
ISD ≤ 82A, di/dt ≤ 310A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Pulse width ≤ 400µs; duty cycle ≤ 2%.
2
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 75A.
Limited by T Jmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
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IRF3808PbF
I D, Drain-to-Source Current (A)
TOP
BOTTOM
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
I D, Drain-to-Source Current (A)
1000
100
4.5V
10
20µs PULSE WIDTH
T J= 25 ° C
1
0.1
1
10
BOTTOM
100
4.5V
10
20µs PULSE WIDTH
T J= 175 ° C
1
100
0.1
1
V DS, Drain-to-Source Voltage (V)
10
100
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.00
3.0
I D = 137A
RDS(on) , Drain-to-Source On Resistance
100.00
T J = 25°C
VDS = 15V
20µs PULSE WIDTH
10.00
1.0
3.0
5.0
7.0
9.0
11.0
13.0
15.0
2.0
(Normalized)
ID, Drain-to-Source Current (Α)
2.5
TJ = 175°C
1.5
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
80
TJ , Junction Temperature
100 120 140 160 180
( °C)
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF3808PbF
100000
12
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
ID = 82A
VDS = 60V
VDS = 37V
VDS = 15V
10
VGS , Gate-to-Source Voltage (V)
C, Capacitance(pF)
Coss = Cds + Cgd
10000
Ciss
Coss
1000
8
6
4
2
Crss
100
0
1
10
0
100
40
VDS , Drain-to-Source Voltage (V)
1000.00
160
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
120
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
T J = 175°C
100.00
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
10.00
100
T J = 25°C
1.00
100µsec
1msec
10
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
10msec
1
0.10
0.0
0.5
1.0
1.5
VSD, Source-toDrain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
80
QG, Total Gate Charge (nC)
2.0
1
10
100
1000
VDS , Drain-toSource Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF3808PbF
140
120
VGS
D.U.T.
RG
100
ID , Drain Current (A)
RD
VDS
LIMITED BY PACKAGE
80
+
-VDD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
60
Fig 10a. Switching Time Test Circuit
40
VDS
20
90%
0
25
50
75
100
125
TC , Case Temperature
150
175
( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
(Z thJC)
1
D = 0.50
0.1
0.20
Thermal Response
0.10
0.05
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
P DM
0.01
t1
t2
Notes:
1. Duty factor D =
2. Peak T
0.001
0.00001
0.0001
0.001
0.01
t1/ t 2
J = P DM x Z thJC
+T C
0.1
1
t1, Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF3808PbF
800
15V
TOP
+
V
- DD
IAS
20V
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
A
EAS , Single Pulse Avalanche Energy (mJ)
D.U.T
RG
640
DRIVER
L
VDS
BOTTOM
480
320
160
0
25
50
75
100
Starting Tj, Junction Temperature
I AS
ID
34A
58A
82A
125
150
( ° C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
QGS
QGD
3.5
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
VGS(th) Gate threshold Voltage (V)
10 V
3.0
ID = 250µA
2.5
2.0
1.5
1.0
-75 -50 -25
VGS
0
25
50
75 100 125 150 175 200
T J , Temperature ( °C )
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
Fig 14. Threshold Voltage Vs. Temperature
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IRF3808PbF
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆ Tj = 25°C due to
avalanche losses
0.01
100
0.05
0.10
10
1
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
EAR , Avalanche Energy (mJ)
500
TOP
Single Pulse
BOTTOM 10% Duty Cycle
ID = 140A
400
300
200
100
0
25
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 16. Maximum Avalanche Energy
Vs. Temperature
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Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
175
D = Duty cycle in avalanche = t av ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
7
IRF3808PbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T*
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
RG
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
V GS
*
+
-
V DD
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
[ISD]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
8
Fig 17. For N-channel HEXFET® power MOSFETs
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IRF3808PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
10.54 (.415)
10.29 (.405)
2.87 (.113)
2.62 (.103)
-B-
3.78 (.149)
3.54 (.139)
4.69 (.185)
4.20 (.165)
-A-
1.32 (.052)
1.22 (.048)
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
LEAD ASSIGNMENTS
1.15 (.045)
MIN
1
2
3
4- DRAIN
14.09 (.555)
13.47 (.530)
4- COLLECTOR
4.06 (.160)
3.55 (.140)
3X
3X
LEAD ASSIGNMENTS
IGBTs, CoPACK
1 - GATE
2 - DRAIN
1- GATE
1- GATE
3 - SOURCE 2- COLLECTOR
2- DRAIN
3- EMITTER
3- SOURCE
4 - DRAIN
HEXFET
1.40 (.055)
1.15 (.045)
0.93 (.037)
0.69 (.027)
0.36 (.014)
3X
M
B A M
0.55 (.022)
0.46 (.018)
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
2 CONTROLLING DIMENSION : INCH
3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
E XAMPL E : T HIS IS AN IR F 1010
LOT CODE 1789
AS S E MB L E D ON WW 19, 1997
IN T H E AS S E MB L Y LINE "C"
Note: "P" in assembly line
position indicates "Lead-Free"
INT E R NAT IONAL
R E CT IF IE R
L OGO
AS S E MB L Y
L OT CODE
PAR T NU MB E R
DAT E CODE
YE AR 7 = 1997
WE E K 19
L INE C
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive (Q101) market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.02/04
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9