CXD2458AR Timing Generator for Color LCD Panels For the availability of this product, please contact the sales office. Description The CXD2458AR is a timing signal generator for the color LCD panel LCX005BK/BKB, LCX009AK/ AKB, LCX024AK and LCX027AK drivers. Features • Generates the color LCD panel LCX005BK/BKB, LCX009AK/AKB, LCX024AK and LCX027AK drive pulse • Supports NTSC/PAL • Supports 16:9 (WIDE) display (NTSC/PAL) • Supports composite SYNC and separate SYNC (XHD, XVD) input • Standby function (low power consumption function) • Supports right/left inverse display • AC drive of LCD panels during no signal • Generates timing signal of external sample-andhold circuit • Generates line inversion and field inversion signals • AFC circuit supporting static and dynamic fluctuations 48 pin LQFP (Plastic) Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD VSS – 0.3 to +6.0 V • Input voltage VI VSS – 0.3 to VDD + 0.3 V • Output voltage VO VSS – 0.3 to VDD + 0.3 V • Operating temperature Topr –20 to +85 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDD 2.7 to 3.3 • Operating temperature Topr –20 to +85 V °C Applications Color LCD viewfinders, compact LCD projectors, etc. Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98218-PS CXD2458AR Block Diagram 19 VDD CKO 41 43 VDD master ck 6 VSS 31 VSS CKI 42 40 VSS STBY 15 SLCK 1 PLNT 2 XCLR 3 XHD 27 PLL PHASE COMPARATOR H-SYNC DETECTOR H-SKEW DETECTOR HALF-H KILLER PLL-COUNTER 39 RPD 35 XCLP 36 HD XVD 45 TST0 7 V-SYNC SEPERATOR (NOISE SHAPE) 46 HP1 TST1 8 47 HP2 TST2 9 48 HP3 TST3 37 38 HP4 TST4 44 10 H-TIMING PULSE GENERATOR BLK 12 RGT 22 HST1 14 HST2 24 HCK1 23 HCK2 EN 17 32 SH1 VD 25 33 SH2 VST 18 V-TIMING PULSE GENERATOR 34 SH3 VCK1 21 VCK2 20 FLDO 29 SBLK 30 SH4 16 CLR PAL PULSE ELIMINATOR 5 SLTM 11 FIELD & LINE CONTROLLER SLNP 26 13 SLFR 28 FRP WIDE 4 –2– CXD2458AR Pin Description Pin Symbol No. I/O Description Input pin for open status 1 SLCK I Switches between LCX005, LCX024 (H) and LCX009, LCX027 (L) L 2 PLNT I Switches between PAL (H) and NTSC (L) L 3 XCLR I Cleared at 0V H 4 WIDE I Switches between 16:9 display (H) and 4:3 display (L) L 5 SBLK O SBLK pulse output (during WIDE MODE) (positive polarity) — 6 VSS — GND — 7 TST0 I Test (Leave open.) L 8 TST1 I Test (Leave open.) L 9 TST2 I Test (Leave open.) L 10 RGT I Switches between Normal scan (H) and Reverse scan (L) H 11 SLTM I Switches between LCX027 (H) and LCX009 (L) L 12 BLK O BLK pulse output (during WIDE MODE) (positive polarity) — 13 SLFR I Switches between field inversion (H) and line inversion (L) L 14 HST2 O H start pulse 2 (positive polarity) — 15 STBY I Standby input (H: Operating mode, L: Standby mode) H 16 CLR O CLR pulse output — 17 EN O EN pulse output — 18 VST O V start pulse output — 19 VDD — Power supply — 20 VCK2 O V clock pulse 2 — 21 VCK1 O V clock pulse 1 — 22 HST1 O H start pulse 1 (positive polarity) — 23 HCK2 O H clock pulse 2 — 24 HCK1 O H clock pulse 1 — 25 VD O VD pulse output (positive polarity) — 26 SLNP I Switches between LCX024 (H) and LCX005 (L) L 27 XHD I XHD (negative polarity)/Composite SYNC (positive polarity) input — 28 FRP O AC drive timing pulse — 29 FLDO O Field identification signal — 30 SH4 O Sample-and-hold pulse (positive polarity) — 31 VSS — GND — 32 SH1 O Sample-and-hold pulse (positive polarity) — 33 SH2 O Sample-and-hold pulse (positive polarity) — 34 SH3 O Sample-and-hold pulse (positive polarity) — –3– CXD2458AR Pin Symbol No. I/O 35 XCLP O Burst position clamp pulse (negative polarity) — 36 HD O HD pulse (positive polarity) — 37 TST3 I Test (Leave open.) H 38 HP4 I Switches the horizontal display position H 39 RPD O Phase comparator output — 40 VSS — GND — 41 CKO O Oscillation cell (output) — 42 CKI I Oscillation cell (input) — 43 VDD — Power supply — 44 TST4 I Test (Leave open.) H 45 XVD I XVD (negative polarity) input L 46 HP1 I Switches the horizontal display position L 47 HP2 I Switches the horizontal display position L 48 HP3 I Switches the horizontal display position L Description Input pin for open status (H: Pull up, L: Pull down) Note) The CXD2458AR processes the composite SYNC and separate SYNC inputs with the same pins. Therefore, care should be given to the following points when using the CXD2458AR. 1) During composite SYNC input, the XVD input pin should be set to L or left open. 2) During separate SYNC (XHD, XVD) input, the XVD width specification is from 2H to 10H. –4– CXD2458AR Electrical Characteristics DC Characteristics Item (VDD = 3.0V ± 10%, Topr = –20 to +85°C) Symbol Measurement conditions H level input voltage VIH L level input voltage VIL H level input current IIH1 L level input current Min. Typ. Max. 0.7VDD Unit Remarks V 0.3VDD V VI = VDD 1.0 µA IIL1 VI = 0V –1.0 µA H level input current IIH2 VI = VDD 180 µA L level input current IIL2 VI = 0V –3.0 µA H level input current IIH3 VI = VDD 3.0 µA L level input current IIL3 VI = 0V –180 µA L level output voltage VOL1 IOL = 1mA 0.2 V H level output voltage VOH1 IOH = –250µA L level output voltage VOL2 IOL = 500µA H level output voltage VOH2 IOH = –125µA L level output voltage VOL3 IOL = 500µA H level output voltage VOH3 IOH = –250µA 2.6 Output leak current IOZ At high impedance state –1.0 Current consumption IDD ∗1 ∗2 ∗3 ∗4 ∗5 ∗6 ∗7 ∗8 10 –10 2.6 V 0.2 2.6 V V 0.2 V V 1.0 µA VDD = 3.0V, STBY = H 12 mA VDD = 3.0V, STBY = L 3 mA ∗1 ∗2 ∗3 ∗4 ∗5 ∗6 ∗7 ∗8 All input pins. Input pins XHD and CKI. Input pins SLNP and XVD. Input pins XCLR, RGT, STBY, HP4, TST3 and TST4. Output pins HCK1 and HCK2. All output pins other than those listed in ∗5, ∗7 and ∗8. Output pin CKO. However, set the input level of input pin CKI to 0V or VDD during measurement. Output pin RPD. AC Characteristics (VDD = 3.0V ± 10%, Topr = –20 to +85°C) Item Clock input cycle Applicable pins tck CKI HCK1, HCK2 Cross-point time difference ∆t VCK1, VCK2 VCKn, HCKn Output rise delay time Other than HCKn and VCKn VCKn, HCKn Output fall delay time Symbol Conditions Other than HCKn and VCKn tpr tpf Min. Typ. Max. 60 Unit ns CL = 30pF 1 15 ns CL = 30pF 3 20 ns CL = 30pF 84 ns CL = 30pF 76 ns CL = 30pF 71 ns CL = 30pF 62 ns HCK1, SH1 delay time difference HCK1, SH1 dt1 CL = 30pF 1 5 ns HCK2, SH1 delay time difference HCK2, SH1 dt2 CL = 30pF 1 5 ns HCK Duty dtyH CL = 30pF 48 53 % HCK1, HCK2 –5– CXD2458AR Timing Definition AC Characteristics CKI VDD 100% 0V tpr VDD Output 0V VDD Output 0V tpf HCK1/VCK1 50% VDD 50% 0V VDD 50% HCK2/VCK2 50% ∆t 0V ∆t tck CKI HCK1/HCK2 50% 50% tH SH1 50% tL 50% 50% dt1 dt2 –6– LCX005BK/BKB, LCX024AK Pixel Arrangement Hout1 dummy1 dummy1 dummy2 G B Vout1 Vout2 B R G B Vout3 B R –7– B G R G B G B R G B B R G B R R G B R G G B R G B B R G B R R G B R G G B R G B B R G B R B R G B R G G B R G B G R B R B G B B R G B R B R G B R G B R G B R G B R R G B R G B R B G B G R G R B B G R R G R B G R B G R R G B R R G G B R G B B R G B R R G B R G G B R G B B R G B R B G B G R G R B R G R B G B G B R G R R G B R B dummy3 G B R G B R G B R G B R G B R G B R G B R G B R G B R Photo-shielding area B R G B R G B R G B R G B R G B R G B R G B R G B R G dummy4 3 G B R G B R G B R G B R 521 B R G B R G B R G B R G 2 13 CXD2458AR 537 G 222 R Vout218 R 2 G R B R B G R B R B G B G R B G G B G R B R G R B G B R B G R G 218 R B R B G G dummy2 to 5 Hout175 R B G R B G R B G B G R B G B G R G R B G R R G B R G B R Drive display area G R B G R G R B G R B G R B R B G R G R B G B G R B G B G R G R B G R G R B R B G R B R B G B G R B G B G R G R B G R G R B Hout174 R B G R B R B G B G R B G B G R G R B G R G R B Hout3 R B G R B R B G B G R B G B G R G R B G Vout217 G R B R B G Hout2 LCX009AK/AKB, LCX027AK Pixel Arrangement dummy1 to 4 dummy1 dummy2 B R G B R Vout3 G –8– R R G B Hout3 R B R R G R G R B Hout267 R G R G R B B R G R R B G B R B R G B dummy5 to 8 Hout268 R G B R G B R G R G B R G B R B R G R B R G B R G B G B R B G R G B R G R B R G B R G B G B R B G R G B R R R B G R G B R G R G B G R B G B G R B R G R B G B G R G B R B R G B R G B R G B R G B R G Drive display area R G B R G B R G B R G B R G B R R B G R B G R R B R G R B R G R B B R B G B 800 R G B R R G 1 13 CXD2458AR 827 228 R B R G B R G B R G B R G B R G B R G B R G B R G B R Photo-shielding area R G B R G B R G B R G B R G B R G B R G B R G B R G 14 225 G B G R G R G R B G B G B G R G R B R B G B G B G R G R B R B G B G B G R G R B R B G B G B G R G B R B G R B G R B G B G R G B G B G R G R B B G R R G R B G R B G B G G R B B R B G R B G R G B B G R G R B G R B B G R R G R B G R B G B G G R B B R B G R B G B G B R R B G G B G R B G G R B R B G R B R B G B G R B G B G R B dummy3 R G R B G R R B R B Vout225 B G R B R B G R Vout224 G Hout2 2 R Vout1 Vout2 Hout1 CXD2458AR Description of Mode Selection Switch (SLCK, SLTM, SLNP, PLNT, WIDE) SLCK SLTM SLNP PLNT WIDE MODE H X L L L LCX005BK/BKB, NTSC, NORMAL H X L L H LCX005BK/BKB, NTSC, WIDE H X L H L LCX005BK/BKB, PAL, NORMAL H X L H H LCX005BK/BKB, PAL, WIDE H X H L L LCX024AK, NTSC, NORMAL H X H L H LCX024AK, NTSC, WIDE H X H H L LCX024AK, PAL, NORMAL H X H H H LCX024AK, PAL, WIDE L L X L L LCX009AK/AKB, NTSC, NORMAL L L X L H LCX009AK/AKB, NTSC, WIDE L L X H L LCX009AK/AKB, PAL, NORMAL L L X H H LCX009AK/AKB, PAL, WIDE L H X L L LCX027AK, NTSC, NORMAL L H X L H LCX027AK, NTSC, WIDE L H X H L LCX027AK, PAL, NORMAL L H X H H LCX027AK, PAL, WIDE ∗ NORMAL (4:3 display), WIDE (16:9 display) ∗ X: Don't Care SLFR SLFR is the selector switch for the AC drive timing pulse (FRP). This switch selects field inversion when H and line inversion when L. Normally, line inversion (L) is used. The transition point is one clock cycle after the transition point of the VCK1 and VCK2 pulses. FRP 1H inversion (2H cycle) 1F inversion (2F cycle) 1H 1H 1H 1Field 1H 1Field ∗ FRP polarity is not specified. –9– CXD2458AR AFC Circuit (PLL Method) The CXD2458AR employs the PLL method in order to achieve phase synchronization with the input sync signal. The PLL circuit phase comparator and frequency division counter are built in, and a fully synchronized AFC circuit is comprised by connecting an external VCO circuit and LPF. PLL errors are detected at the following timing. The phase comparison output of the entire bottom of XHD or the horizontal sync signal of composite SYNC and the internal H counter becomes RPD. RPD output is converted to DC error with the lag-lead filter (LPF), and then it changes the varicap capacitance to stabilize the oscillating frequency at 702fh in the LCX005BK/BKB and LCX024AK, and 1050fh in the LCX009AK/AKB and LCX027AK. This PLL circuit is adjusted by setting the RPD transition point so that it sets in the center of the window (XHD or horizontal sync signal of composite SYNC) as shown in the figure below. 4.7µs XHD or horizontal sync signal of composite SYNC RPD WL = WH WL WH AC Driving for No Signal HST1/2, HCK1/2, FRP, VCK1/2, XCLP, VST, HD, VD, SH1/2/3/4 and EN are made to run freely so that the LCD panel is AC driven even when there are no input sync signals (XHD/XVD and composite SYNC). During this time, the horizontal sync separation circuit stops and the PLL internal frequency division counter is made to run freely. At the same time, the auxiliary V counter is used to create the reference pulse for generating the free running VD and VST because the vertical sync separation circuit is also stopped. The cycle of this V counter is set to 269H for NTSC and 321H for PAL. However, when there is no XVD (VSYNC) input for 301H (NTSC) and 360H (PAL), the no signal state is assumed and the free running VD and VST pulses are generated from the next field. RPD is kept at high impedance when there is no signal in order to prevent the AFC circuit from causing phase errors due to phase comparison. System Clear (XCLR) The entire logic is initialized by setting XCLR = L. Be sure to perform this operation during power-on and after changing the STBY pin from L to H. When this function is activated the outputs (XCLP, HD, FRP, VST, VD, CLR, EN, HST1/2, HCK1/2, SH1/2/3/4, VCK1/2, FLDO, SBLK and BLK) go to L. – 10 – CXD2458AR Right/Left Inverse Display The CXD2458AR outputs a right/left inversion timing pulse that supports the right/left inverse display function of the LCX005BK/BKB, LCX024AK, LCX009AK/AKB and LCX027AK. The LCD panel is arranged in a delta pattern, where the same signal line is 1.5-dot offset at adjoining vertical lines. For this reason, a 1.5-dot offset is attached to the horizontal start pulse (HST) of the LCD between odd lines and even lines in order to correct this difference. Other H system output pulses are also 1.5-dot offset. When the panel is driven with left scan (Reverse scan), this offset relationship becomes inverted for even and odd lines, and the asymmetrical dot arrangement produces an offset. Therefore, the CXD2458AR internally controls the right/left and interline offset to allow right scan or left scan display by setting RGT = H or L for right/left inversion. Right scan (Normal scan) Left scan (Reverse scan) V SCANNER H SCANNER Display area SH Pulse and HCK Phase Relationship The phase relationship between the SH pulse and HCK changes according to switching between right scan (Normal scan) and left scan (Reverse scan). SH3 is the re-sampling pulse. RGT = H (Normal scan) RGT = L (Reverse scan) HCK1/2 SH1 SH2 SH3 SH4 – 11 – CXD2458AR 16:9 (WIDE) Display Mode Setting the WIDE pin to H shifts the unit to WIDE display mode. In this mode, the aspect ratio is converted through pulse eliminator processing, allowing 16:9 quasi-WIDE display. Vertical pulse eliminator scanning of 1/4 (NTSC) and 2/6 (PAL) for the LCX005BK/BKB and LCX009AK/AKB, and 1/4 (NTSC) and 10/28 (PAL) for the LCX024AK and LCX027AK is performed, and the video signal is compressed in the display area compared to 4:3 display to achieve 16:9 (WIDE) display. In addition, in areas outside the display area, vertical high-speed scanning is performed and black signals are written to the black display area in the upper 28 lines and the lower 27 or 28 lines. During this period, the FRP and HST output cycles are also changed, and EN and CLR are not output. In addition, the SBLK output, which is the black signal generation timing pulse, and the LCX024AK/LCX027AK black display area control signal BLK are both H. (For example, black display in the panel is permitted by connecting the SBLK output to the external RGB input pin of the CXA1785AR.) See the Timing Charts for details. AAAA AAAA AAA AAA AAAA AAAA Vertical high speed scanning 218 LINES (225 LINES) AAA AAA Display area 4:3 display Vertical pulse eliminator scanning Black display area 28 LINES (28 LINES) Display area 163 LINES (169 LINES) Black display area 27 LINES (28 LINES) 16:9 display ∗ Numbers in parentheses are for the LCX009AK/AKB and LCX027AK. Note) When the no signal status occurs during 16:9 (WIDE) display mode, 4:3 display mode results. – 12 – CXD2458AR HP1, 2, 3, 4 These are selector switches for the horizontal display position. The HST timing can be set at 2fh intervals in 16 different ways by using the four HP1, 2, 3 and 4 bits. The picture center is set at internal preset value: HP1/2/3/4: LLLH. However, because there is actually a difference between the RGB signal and the drive pulse delays, the picture center may not match the design center. In this case, adjust with these switches. The HST timing (from SYNC termination to the rising edge of HST) for even lines is shown below. LCX005BK/BKB, LCX024AK (NTSC/PAL) HP4 HP3 HP2 HP1 0 0 0 0 72fh (6.51/6.56µs) 74.5fh (6.74/6.79µs) 0 0 0 1 70fh 72.5fh 0 0 1 0 68fh 70.5fh 0 0 1 1 66fh 68.5fh 0 1 0 0 64fh 66.5fh 0 1 0 1 62fh 64.5fh 0 1 1 0 60fh 62.5fh 0 1 1 1 58fh 60.5fh 1 0 0 0 56fh (5.06/5.11µs) 58.5fh (5.29/5.33µs) 1 0 0 1 54fh 56.5fh 1 0 1 0 52fh 54.5fh 1 0 1 1 50fh 52.5fh 1 1 0 0 48fh 50.5fh 1 1 0 1 46fh 48.5fh 1 1 1 0 44fh 46.5fh 1 1 1 1 42fh (3.80/3.83µs) 44.5fh (4.02/4.06µs) HST1 (NTSC/PAL) HST2 (NTSC/PAL) ∗ The HST1 and 2 timing for odd lines is 1.5fh delayed and 1.5fh advanced respectively from the above timings. (See the Timing Charts for details.) – 13 – CXD2458AR LCX009AK/AKB, LCX027AK (NTSC/PAL) HST1 (NTSC/PAL) HST2 (NTSC/PAL) HP4 HP3 HP2 HP1 0 0 0 0 91fh (5.51/5.55µs) 93.5fh (5.66/5.70µs) 0 0 0 1 89fh 91.5fh 0 0 1 0 87fh 89.5fh 0 0 1 1 85fh 87.5fh 0 1 0 0 83fh 85.5fh 0 1 0 1 81fh 83.5fh 0 1 1 0 79fh 81.5fh 0 1 1 1 77fh 79.5fh 1 0 0 0 75fh (4.54/4.57µs) 77.5fh (4.69/4.72µs) 1 0 0 1 73fh 75.5fh 1 0 1 0 71fh 73.5fh 1 0 1 1 69fh 71.5fh 1 1 0 0 67fh 69.5fh 1 1 0 1 65fh 67.5fh 1 1 1 0 63fh 65.5fh 1 1 1 1 61fh (3.69/3.72µs) 63.5fh (3.84/3.87µs) ∗ The HST1 and 2 timing for odd lines is 1.5fh delayed and 1.5fh advanced respectively from the above timings. (See the Timing Charts for details.) – 14 – LCX005BK/BKB, LCX024AK Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: H (Normal scan) MCK 4.7µs (52fh) XHD 4.7µs (52fh) (BLK) HD 2.1µs (23fh) 4.4µs (49fh) XCLP 2.0µs (22fh) 4.5fh 0.5fh 1.3µs (14fh) HST1 13fh 13fh HST2 HCK1 – 15 – HCK2 SH1 SH2 SH3 SH4 FRP ODD FIELD EVEN FIELD 18.5fh VCK1 VCK2 CLR 0.5µs (6fh) 3.0µs (33fh) EN ODD LINE CXD2458AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB, LCX024AK Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: H (Normal scan) MCK 4.7µs (52fh) XHD 4.7µs (52fh) (BLK) 2.1µs (23fh) HD 4.4µs (49fh) XCLP 3.0fh 2.0µs (22fh) 2.5fh 1.3µs (14fh) HST1 13fh HST2 13fh HCK1 – 16 – HCK2 SH1 SH2 SH3 SH4 FRP ODD FIELD EVEN FIELD 18.0fh VCK1 VCK2 0.5µs (6fh) CLR 3.0µs (33fh) EN EVEN LINE CXD2458AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB, LCX024AK Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: L (Reverse scan) MCK 4.7µs (52fh) XHD 4.7µs (52fh) (BLK) 2.1µs (23fh) HD XCLP 4.4µs (49fh) 4.0fh 2.0µs (22fh) 2.5fh 13fh HST1 HST2 13fh HCK1 – 17 – HCK2 SH1 SH2 SH3 SH4 FRP ODD FIELD EVEN FIELD 18.0fh VCK1 VCK2 0.5µs (5fh) CLR 3.0µs (34fh) EN ODD LINE CXD2458AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB, LCX024AK Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: L (Reverse scan) MCK 4.7µs (52fh) XHD 4.7µs (52fh) (BLK) 2.0µs (22fh) HD 4.5µs (50fh) XCLP 5.5fh 2.0µs (22fh) 0.5fh 1.4µs (15fh) HST1 13fh HST2 13fh HCK1 – 18 – HCK2 SH1 SH2 SH3 SH4 FRP ODD FIELD EVEN FIELD VCK1 18.5fh VCK2 0.5µs (5fh) CLR 3.0µs (34fh) EN EVEN LINE CXD2458AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB, LCX027AK Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: H (Normal scan) MCK XHD 4.7µs (78fh) 4.7µs (78fh) (BLK) 2.0µs (34fh) HD 4.4µs (72fh) XCLP 2.0µs (33fh) 1.3µs (22fh) HST1 2.5fh 0.5fh 12fh 12fh HST2 HCK1 HCK2 – 19 – SH1 SH2 SH3 SH4 FRP ODD FIELD EVEN FIELD VCK1 43.5fh VCK2 0.5µs (8fh) CLR 3.0µs (50fh) EN ODD LINE CXD2458AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB, LCX027AK Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: H (Normal scan) MCK 4.7µs (78fh) XHD 4.7µs (78fh) (BLK) 4.4µs (72fh) 2.0µs (34fh) HD 2.0µs (33fh) XCLP 1.3µs (22fh) HST1 4.0fh 2.5fh 12fh HST2 12fh HCK1 – 20 – HCK2 SH1 SH2 SH3 SH4 FRP ODD FIELD EVEN FIELD 43.0fh VCK1 VCK2 0.5µs (8fh) CLR 3.0µs (50fh) EN EVEN LINE CXD2458AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB, LCX027AK Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: L (Reverse scan) MCK 4.7µs (78fh) XHD 4.7µs (78fh) (BLK) 2.0µs (34fh) HD 4.4µs (72fh) XCLP 3.0fh 2.0µs (33fh) 2.5fh 1.3µs (22fh) HST1 12fh HST2 12fh HCK1 HCK2 – 21 – SH1 SH2 SH3 SH4 FRP ODD FIELD EVEN FIELD 43.0fh VCK1 VCK2 0.5µs (7fh) CLR 3.0µs (51fh) EN ODD LINE CXD2458AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB, LCX027AK Horizontal Direction Timing Chart NTSC/PAL HP1/2/3/4: LLLH RGT: L (Reverse scan) MCK 4.7µs (78fh) XHD 4.7µs (78fh) (BLK) 4.4µs (72fh) 2.0µs (34fh) HD XCLP 1.5fh 2.0µs (33fh) 0.5fh 1.3µs (22fh) HST1 12fh HST2 12fh HCK1 HCK2 – 22 – SH1 SH2 SH3 SH4 FRP ODD FIELD EVEN FIELD 43.5fh VCK1 VCK2 0.5µs (7fh) CLR 3.0µs (51fh) EN EVEN LINE CXD2458AR Note) The third row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart NTSC : 1st display line XVD XHD CSYNC 204 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 – 23 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart NTSC : 1st display line XVD XHD CSYNC 203 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 FRP (1H inversion) – 24 – HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2458AR LCX005BK/BKB Vertical Direction Timing Chart PAL : 1st display line XVD XHD CSYNC 248 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 – 25 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart PAL : 1st display line XVD XHD CSYNC 249 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 – 26 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart NTSC WIDE 163-line display area, 1/4 pulse elimination, : 1st display line XVD XHD CSYNC 204 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 – 27 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart NTSC WIDE 163-line display area, 1/4 pulse elimination, : 1st display line XVD XHD CSYNC 203 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 – 28 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart PAL WIDE 163-line display area, 2/6 pulse elimination, : 1st display line XVD XHD CSYNC 248 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 – 29 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX005BK/BKB Vertical Direction Timing Chart PAL WIDE 163-line display area, 2/6 pulse elimination, : 1st display line XVD XHD CSYNC 249 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 – 30 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX024AK Vertical Direction Timing Chart NTSC : 1st display line XVD XHD CSYNC 204 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 – 31 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX024AK Vertical Direction Timing Chart NTSC : 1st display line XVD XHD CSYNC 203 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 – 32 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX024AK Vertical Direction Timing Chart PAL : 1st display line XVD XHD CSYNC 248 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 – 33 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX024AK Vertical Direction Timing Chart PAL : 1st display line XVD XHD CSYNC 249 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 – 34 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX024AK Vertical Direction Timing Chart NTSC WIDE 163-line display area, 1/4 pulse elimination, : 1st display line XVD XHD CSYNC 204 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 – 35 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX024AK Vertical Direction Timing Chart NTSC WIDE 163-line display area, 1/4 pulse elimination, : 1st display line XVD XHD CSYNC 203 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 – 36 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX024AK Vertical Direction Timing Chart PAL WIDE 163-line display area, 10/28 pulse elimination, : 1st display line XVD XHD CSYNC 248 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 FRP (1H inversion) – 37 – HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX024AK Vertical Direction Timing Chart PAL WIDE 163-line display area, 10/28 pulse elimination, : 1st display line XVD XHD CSYNC 249 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 – 38 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart NTSC : 1st display line XVD XHD CSYNC 204 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 – 39 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart NTSC : 1st display line XVD XHD CSYNC 203 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 – 40 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart PAL : 1st display line XVD XHD CSYNC 248 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 – 41 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart PAL : 1st display line XVD XHD CSYNC 249 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 – 42 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart NTSC WIDE 169-line display area, 1/4 pulse elimination, : 1st display line XVD XHD CSYNC 204 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 – 43 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart NTSC WIDE 169-line display area, 1/4 pulse elimination, : 1st display line XVD XHD CSYNC 203 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 – 44 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart PAL WIDE 169-line display area, 2/6 pulse elimination, : 1st display line XVD XHD CSYNC 248 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 FRP (1H inversion) – 45 – HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX009AK/AKB Vertical Direction Timing Chart PAL WIDE 169-line display area, 2/6 pulse elimination, : 1st display line XVD XHD CSYNC 249 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 – 46 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX027AK Vertical Direction Timing Chart NTSC : 1st display line XVD XHD CSYNC 204 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 – 47 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX027AK Vertical Direction Timing Chart NTSC : 1st display line XVD XHD CSYNC 203 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 – 48 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX027AK Vertical Direction Timing Chart PAL : 1st display line XVD XHD CSYNC 248 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 – 49 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX027AK Vertical Direction Timing Chart PAL : 1st display line XVD XHD CSYNC 249 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 – 50 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX027AK Vertical Direction Timing Chart NTSC WIDE 169-line display area, 1/4 pulse elimination, : 1st display line XVD XHD CSYNC 204 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 – 51 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX027AK Vertical Direction Timing Chart NTSC WIDE 169-line display area, 1/4 pulse elimination, : 1st display line XVD XHD CSYNC 203 210 220 230 240 243 1 10 20 30 40 50 60 (BLK) VST VCK1 VCK2 – 52 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX027AK Vertical Direction Timing Chart PAL WIDE 169-line display area, 10/28 pulse elimination, : 1st display line XVD XHD CSYNC 248 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 – 53 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK ODD FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. LCX027AK Vertical Direction Timing Chart PAL WIDE 169-line display area, 10/28 pulse elimination, : 1st display line XVD XHD CSYNC 249 260 270 280 288 1 10 20 30 40 50 55 (BLK) VST VCK1 VCK2 – 54 – FRP (1H inversion) HST EN CLR FRP (1F inversion) FLD VD SBLK BLK EVEN FIELD CXD2458AR Note) The fourth row of the timing chart "BLK" is a pulse indicated as a reference and is not a pulse output from pins. FRP polarity is not specified for each line and field. CXD2458AR AC conversion circuit (RGB driver) RGB decoder Sample-and-hold circuit (RGB driver) Sample-and-hold circuit (RGB driver) RGB driver Backlight driver circuit Application Circuit +3V LCX024AK LCX005BK/BKB 1k 10k 3300p 0.01µ 33k 10k 1000p 39 RPD HST1 22 40 VSS VCK1 21 41 CKO VCK2 20 42 CKI VDD 19 43 VDD VST 18 EN 17 VSS TST0 TST1 TST2 3 4 5 6 7 8 9 10 11 12 2 RGT SBLK 1 SLTM WIDE +12V SLFR 13 XCLR 47 HP2 48 HP3 SLCK PLNT 46 HP1 RGB decoder LCD panel CLR 16 STBY 15 +3V HST2 14 45 XVD 20p HCK1 24 HCK2 23 44 TST4 L 100k VD SLNP FRP XHD SH4 FLDO VSS SH1 SH2 38 HP4 BLK 3.3µ 37 TST3 SH3 +3V XCLP HD 36 35 34 33 32 31 30 29 28 27 26 25 LCD panel LCD panel +3V RGB external input (RGB driver) 16:9 LCX005BK/BKB, LCK024AK PAL LCX009AK/AKB, LCK027AK NTSC N R 4:3 LCX027AK LCX009AK/AKB Reference examples of L value: when using LCX009AK/AKB, LCX027AK 4.7µH when using LCX005BK/BKB, LCX024AK 10µH Recommended varicap: 1T369 (SONY) The constants noted above are reference values, so care should be taken as they may change according to the wiring capacitance on the board, etc. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 55 – CXD2458AR Package Outline Unit: mm 48PIN LQFP (PLASTIC) 9.0 ± 0.3 7.0 ± 0.2 0.15 ± 25 36 24 8.0 ± 0.2 37 0.05 A 13 48 12 1 0.5 0.2 ± 0.06 0.08 M 0.5 1.45 ± 0.2 0.1 0.65 ± 0.2 0.1 ± 0.1 0° to 10° DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-48P-L111 LEAD TREATMENT SOLDER PLATING EIAJ CODE LQFP048-P-0707-AP LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 0.2g JEDEC CODE – 56 –