TPS75003 www.ti.com SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 Triple-Supply Power Management IC for Powering FPGAs and DSPs • • • • • • • DESCRIPTION Two Buck Controllers Providing up to 3A and One 300mA LDO for Powering 3 Supplies Tested and Endorsed by Xilinx for Powering the Spartan™-3 and Spartan-3L FPGAs Adjustable (1.2V to 6.5V for Bucks, 0.9V to 6.5V for LDO) Output Voltages on All Channels Independent Soft-Start for Each Supply Independent Enable for Each Supply LDO Stable with Small 2.2µF Ceramic Output Cap Input Voltage Range: 2.2V to 6.5V Small, Low-Profile 4.5mm x 3.5mm x 0.9mm QFN Package The TPS75003 is fully specified from -40°C to +85°C and is offered in a QFN package, yielding a highly compact total solution size with high power dissipation capability. APPLICATIONS • • • The TPS75003 is a complete power management solution for FPGA, DSP and other multi-supply applications. The device has been tested with and meets all of the Xilinx Spartan-3 and Spartan-3L start-up profile requirements, including monotonic voltage ramp and minimum voltage rail rise time. Independent Enables for each output allow sequencing to minimize demand on the power supply at start-up. Soft-start on each supply limits inrush current during start-up. Two integrated buck controllers allow efficient, cost-effective voltage conversion for both low and high current supplies such as core and I/O. A 300mA LDO is integrated to provide an auxiliary rail such as VCCAUX on the Xilinx Spartan-3 FPGA. All three supply voltages are offered in user-programmable options for maximum flexibility. FPGA Supplies DSP/ASIC Supplies Split Supply Applications TPS75003 IN3 SS3 AGND EN1 SS1 DGND SW1 IN1 IS1 19 18 17 16 15 14 13 12 IN1 20 EN1 SS1 11 FB1 IN2 EN2 DGND OUT3 SS2 1 10 IS1 3A BUCK1 IS2 3A BUCK2 IS2 IN2 SW2 DGND SS2 EN2 EN3 SW2 FB2 OUT3 9 8 7 6 5 4 3 IN3 2 FB1 FB2 EN3 FB3 SW1 SS3 DGND 300mA LDO FB3 AGND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Spartan is a trademark of Xilinx, Inc. All other trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2004, Texas Instruments Incorporated PRODUCT PREVIEW FEATURES • TPS75003 www.ti.com SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION PRODUCT VOUT PACKAGE-LEAD DESIGNATOR SPECIFIED TEMPERATURE RANGE, TA ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TPS75003 Buck1: Adjustable Buck2: Adjustable LDO: Adjustable 4.5x3.5 QFN-20 (RHL) -40°C to +85°C TPS75003RHLR Tape and Reel, 3000 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) PRODUCT PREVIEW VINX range (IN1, IN2, IN3) TPS75003 UNIT -0.3 to +7.0 V VENX range (EN1, EN2, EN3) -0.3 to VINX +0.3 V VSWX range (SW1, SW2, SW3) -0.3 to VINX +0.3 V VISX range (IS1, IS2, IS3) -0.3 to VINX +0.3 V -0.3 to +7.0 V -0.3 to VINX +0.3 V VOUT3 range VSSX range (SS1, SS2, SS3) VFBX range (FB1, FB2, FB3) Peak LDO output current (IOUT3) Continuous total power dissipation -0.3 to +3.3 V Internally limited — See Dissipation Ratings Table — Junction temperature range, TJ -55 to +150 °C Storage temperature range -65 to +150 °C ESD rating, HBM 2 kV ESD rating, CDM 500 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristics is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. DISSIPATION RATINGS BOARD RΘJC RΘJA DERATING FACTOR ABOVE TA = 25°C TA ≤ 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C POWER RATING Reference Layout (1) — — — — — — (1) 2 Refer to PCB Layout section. Internal power dissipation limits are determined by LDO operation: PDISS = (VIN3– VOUT3) x IOUT3. TPS75003 www.ti.com SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS VEN1 = VIN1, VEN2 = VIN2, VEN3 = VIN3, VIN1 = VIN2 = VIN3 = 3.0V, VOUT1 = VOUT2 = VOUT3 = 2.5V, COUT1 = COUT2 = 47µF, COUT3 = 2.2µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. PARAMETER CONDITIONS MIN TYP MAX UNIT Supply and Logic VINX Input Voltage Range (IN1, IN2, IN3) (1) IQ Quiescent Current, IQ = IDGND + IAGND IOUT1 = IOUT2 = 0mA, IOUT3 = 1mA ISHDN Shutdown Supply Current VEN1 = VEN2 = VEN3 = 0V VIHX Enable High, enabled (EN1, EN2, EN3) VILX Enable Low, shutdown (EN1, EN2, EN3) IENX Enable pin current (EN1, EN2, EN3) 2.2 6.5 V 100 150 µA 0.3 3.0 µA 1.3 VINX V 0 0.3 V 0.5 µA VINX V 0.01 Buck Controllers 1 and 2 Adjustable Output Voltage Range (2) VFB1,2 Feedback Voltage (FB1, FB2) Feedback Voltage Accuracy (1) (FB1, FB2) VFBX 1.2 2.8V ≤ V IN1,2 ≤ 6.5V -4 V +4 % 0.01 0.5 µA 105 120 mV 0.01 0.5 µA IFB1,2 Current into FB1, FB2 pins VIS1,2 Reference Voltage for Current Sense IIS1,2 Current into IS1, IS2 Pins ∆VOUT%/∆VIN Line Regulation (1) Measured with the circuit in Figure 1, VOUT + 0.5V ≤ VIN ≤ 6.5V 0.6 %/V ∆VOUT%/∆IOUT Load Regulation Measured with the circuit in Figure 1, 1mA ≤ I OUT ≤ 2A 0.6 %/A n 1,2 Efficiency (3) Measured with the circuit in Figure 1, IOUT = 1A 94 % tSTR1,2 Startup Time (3) Measured with the circuit in Figure 1, RL = 6Ω, COUT = 100µF, CSS = 2.2nF 5 ms RDS,ON1,2 Gate Driver P-Channel MOSFET On-Resistance VIN1,2 > 2.5V 4 VIN1,2 = 2.2V 6 RDS,ON1,2 Gate Driver N-Channel MOSFET On-Resistance VIN1,2 > 2.5V 4 VIN1,2 = 2.2V 6 ISW1,2 Minimum Gate Drive Current tON Minimum On Time 1.36 1.6 1.84 µs tOFF Minimum Off Time 0.44 0.55 0.86 µs 6.5 - VDO V 90 PRODUCT PREVIEW VOUT1,2 Ω Ω TBD mA LDO VOUT3 Output Voltage Range VFB3 Feedback Pin Voltage 1.0 0.507 V Feedback Pin Voltage Accuracy (1) 2.85V ≤ VIN3 ≤ 6.5V 1mA ≤ IOUT3 ≤ 300mA ∆VOUT%/∆VIN Line Regulation (1) VOUT3 + 0.5V ≤ VIN3 ≤ 6.5V 0.75 %/V ∆VOUT%/∆IOUT Load Regulation 10mA ≤ IOUT3 ≤ 300mA 0.01 % / mA (1) (2) (3) -4.0 +4.0 % To be in regulation, minimum VIN1 (or VIN2) must be greater than VOUT1,NOM (or VOUT2,NOM) by an amount determined by external components. Minimum VIN3 = VOUT3 + VDO or 2.2V, whichever is greater. Maximum VOUT is dependent on external components and will be less than VIN. Depends on external components. 3 TPS75003 www.ti.com SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 ELECTRICAL CHARACTERISTICS (continued) VEN1 = VIN1, VEN2 = VIN2, VEN3 = VIN3, VIN1 = VIN2 = VIN3 = 3.0V, VOUT1 = VOUT2 = VOUT3 = 2.5V, COUT1 = COUT2 = 47µF, COUT3 = 2.2µF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C. PARAMETER CONDITIONS MIN TYP MAX UNIT 175 300 mV 625 1000 mA 0.01 0.1 µA LDO, continued VDO Dropout Voltage (VIN = VOUT(NOM) - 0.1) (4) IOUT3 = 300mA, 2.2V ≤ VIN3 < 6.5 ICL3 Current Limit VOUT = 0.9 x VOUT(NOM) IFB3 Current into FB3 pin Vn Output Noise PSRR Power-Supply Rejection Ratio tSD Thermal Shutdown Temperature for LDO (4) PRODUCT PREVIEW 4 VDO does not apply when VOUT + VDO < 2.2V. BW = 100Hz - 100kHz, IOUT3 = 300mA 375 400 f = 1kHz TBD f = 10kHz TBD Shutdown, Temp Increasing 175 Reset, Temp Decreasing 160 µVRMS dB °C TPS75003 www.ti.com SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 DEVICE INFORMATION Functional Block Diagram TPS75003 IN1 ≤ 3A Buck Controller IS1 VIS 1 Switch Control Soft Start Control SS1 EN1 VR E F1 FB1 DGND IN2 ≤ 3A Buck Controller Switch Control PRODUCT PREVIEW IS2 VIS2 SS2 SW1 SW2 Soft Start Control EN2 VR E F2 FB2 DGND 300mA LDO IN3 OUT3 Thermal/ Current Limit EN3 FB3 VREF 3 SS3 AGND 5 TPS75003 www.ti.com SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 TERMINAL FUNCTIONS TERMINAL PRODUCT PREVIEW 6 DESCRIPTION NAME RHL DGND 6, 15, PAD AGND 18 Ground connection for LDO. IN1 13 Input supply to BUCK1. IN2 8 Input supply to BUCK2. IN3 20 Input supply to LDO. EN1 17 Driving the enable pin (ENx) high turns on BUCK1 regulator. Driving this pin low puts it into shutdown mode, reducing operating current. The enable pin does not trigger on fast negative going transients. EN2 4 Same as EN1 but for BUCK2 controller. EN3 3 Same as EN1 but for LDO. SS1 16 Connecting a capacitor between this pin and ground increases start-up time of the BUCK1 regulator by slowing the ramp-up of current limit. This high-impedance pin is noise-sensitive; careful layout is important. See Applications and PCB Layout sections for details. SS2 5 Same as SS1 but for BUCK2 regulator. SS3 19 Connecting a capacitor from this pin to ground slows the start-up time of the LDO reference, therby slowing output voltage ramp-up. See Applications section for details. IS1 12 Current sense input for BUCK1 regulator. The voltage difference between this pin and IN1 is compared to an internal reference to set current limit. For a robust output start-up ramp, careful layout and bypassing are required. See Applications section for details. IS2 9 Same as IS1 but compared to IN2 and used for BUCK2 controller. SW1 14 Gate drive pin for external BUCK1 P-channel MOSFET. SW2 7 Same as SW1 but for BUCK2 controller. FB1 11 Feedback pin. Used to set the output voltage of BUCK1 regulator. FB2 10 Same as FB1 but for BUCK2 controller. FB3 2 Same as FB1 but for LDO. OUT3 1 Regulated LDO output. A small ceramic capacitor (≥ 2.2µF) is needed from this pin to ground to ensure stability. Ground connection for BUCK1 and BUCK2 converters. Pins 6 and 15 should be connected to the back side exposed pad by a short metal trace as shown in the PCB Layout section of this data sheet. TPS75003 www.ti.com SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 Typical Application Circuit for Powering the Xilinx Spartan-3 FPGA L1 15µH Sumida CDRH8D43−150 Q1 EN1 Siliconix Si2323DS 0.01µF 1.5nF VCCINT 1.2V, 3A Vishay SS32 100µF Tantalum R1 33mΩ IN3 VIN 100µF 0.1µF 12 IS1 IN1 13 SW1 14 DGND 15 SS1 16 EN1 17 AGND 18 19 SS3 VIN 20 11 FB1 1µF DGND EN3 EN2 IS2 9 8 IN2 7 SW2 6 DGND 5 SS2 4 EN2 3 FB2 PRODUCT PREVIEW R4 154k EN3 R3 619k 10 FB3 10µF 1 2 OUT3 VCCAUX 2.5V, 300mA VIN R2 33mΩ 1.5nF Siliconix Si2323DS ON Semiconductor MBRM120 R6 365k 0.1µF 10pF L2 5µH Sumida CDRH6D38−5R0 R5 619k VCCIO 3.3V, 3A 100µF Tantalum Figure 1. 7 TPS75003 www.ti.com SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS Measured using circuit in Figure 1 Buck Converter BUCK LOAD REGULATION BUCK LOAD REGULATION 5 5 4 VIN = 3.3V VOUT = 1.2V TA = −40C 3 3 2 2 TA = +85 C 1 TA = +25 C 0 −1 ∆ VOUT (%) ∆ VOUT (%) VIN = 5V VOUT = 3.3V 4 0 TA = −40 C −1 −2 −2 −3 −3 −4 −4 −5 −5 0 0.5 1.0 1.5 2.0 IOUT (A) 2.5 3.0 0 3.5 0.5 1.0 1.5 2.0 I OUT (A) PRODUCT PREVIEW Figure 2. BUCK LINE REGULATION 3.5 BUCK LINE REGULATION 3 TA = +25 C 1 TA = +85 C −1 TA = +25C 2 ∆ VOUT (%) 2 0 VOUT = 3.3V IOUT = 2A 4 TA = −40C 3 ∆ VOUT (%) 3.0 5 4 TA = −40 C 1 0 −1 TA = +85C −2 −2 −3 −3 VOUT = 1.2V IOUT = 2A −4 −5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 −4 −5 7.0 3.0 3.5 4.0 4.5 VIN (V) 5.0 5.5 6.0 6.5 7.0 VIN (V) Figure 4. Figure 5. BUCK SWITCHING FREQUENCY vs IOUT, TA 500 BUCK SWITCHING FREQUENCY vs IOUT 600 VOUT = 1.2V 400 VIN = 3.3V 300 200 VIN = 5.0V −40C 100 +25C Switching Frequency (kHz) Switching Frequency (kHz) 2.5 Figure 3. 5 500 VIN = 5.0V VOUT = 3.3V VIN = 2.2V VOUT = 1.2V 400 VIN = 3.3V VOUT = 1.2V 300 200 100 VIN = 5.0V VOUT = 1.2V +85C 0 0 0 0.5 1.0 1.5 IOUT (A) Figure 6. 8 TA = +85 C TA = +25 C 1 2.0 2.5 3.0 0.01 0.1 1.0 IOUT (A) Figure 7. 10 TPS75003 www.ti.com SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) Measured using circuit in Figure 1 BUCK OUTPUT VOLTAGE RIPPLE EFFICIENCY vs IOUT 100 VIN = 5.0V VOUT = 3.3V IOUT = 2A VIN = 5.0V VOUT = 3.3V 90 20mV/div Efficiency (%) 80 70 VIN = 5.0V VOUT = 1.2V 60 50 40 VIN = 3.3V 30 VOUT = 1.2V 20 10 0 1µs/div 0.0001 0.001 0.01 0.1 1 10 Figure 8. Figure 9. BUCK START-UP vs VIN and IOUT BUCK START-UP vs VIN and COUT EN EN VOUT (500mV/div) VIN = 3.3V, IOUT = 1.0A VIN = 5V, I OUT = 2.0A VIN = 5V, COUT = 330µF VOUT (500mV/div) VIN = 5V, IOUT = 0.5A VIN = 5V, I OUT = 1.0A VIN = 5V, COUT = 100µF VIN = 3.3V, COUT = 680µF VIN = 3.3V, COUT = 100µF VIN = 3.3V, I OUT = 2.0A CSS = 0.01µF VOUT = 1.2V CSS = 0.01µF VOUT = 1.2V 20ms/div 20ms/div Figure 10. Figure 11. BUCK START-UP vs VIN and CSS BUCK START-UP vs IOUT and CSS VIN = 3.3V, C SS = 0.001µF VIN = 5V VOUT = 3.3V VIN = 5V, CSS = 0.001µF IOUT = 2A, CSS = 560pF VIN = 3.3V, C SS = 0.01µF IOUT = 1A VOUT = 1.2V 20ms/div Figure 12. VOUT (2V/div) VOUT (500mV/div) EN VIN = 5V, CSS = 0.01µF PRODUCT PREVIEW IOUT (A) EN I OUT = 0.5A, CSS = 560pF IOUT = 0.5A, CSS = 1500pF I OUT = 2A, CSS = 1500pF 5ms/div Figure 13. 9 TPS75003 www.ti.com SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) Measured using circuit in Figure 1 BUCK START-UP vs VIN and RSENSE VOUT = 1.2V, CSS = 0.01µF EN VOUT (1V/div) VIN = 3.3V, IOUT = 1A, RS = 0.020 VIN = 5V, IOUT = 1A, RS = 0.020 VIN = 3.3V, IOUT = 1A, RS = 0.033 VIN =5V, IOUT = 1A, RS = 0.033 20ms/div Figure 14. LDO LOAD REGULATION LDO LINE REGULATION 5 5 VIN = 3.3V VOUT = 2.5V 4 3 3 2 ∆VOUT (%) ∆VOUT (%) VOUT = 2.5V IOUT = 1mA 4 2 TA = −40 C 1 0 −1 TA = +25C −2 TA = +25C 1 0 −1 TA = +85C −2 TA = +85C −3 TA = −40C −3 −4 −4 −5 −5 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 3.0 3.5 4.0 4.5 5.0 5.5 IOUT (A) VIN (V) Figure 15. Figure 16. LDO DROPOUT vs IOUT 6.0 6.5 7.0 LDO DROPOUT vs TA 450 500 VIN = 3.3V VOUT = 2.5V TA = +25C VOUT = 2.5V IOUT = 300mA 400 400 350 TA = +85C 300 VDO (mV) VDO (mV) PRODUCT PREVIEW LDO Converter 300 200 TA = −40 C 250 200 150 100 100 50 0 0 0 50 100 150 200 250 I OUT (mA) Figure 17. 10 300 350 400 450 −40 −25 −10 5 20 35 Ambient Temperature (C) Figure 18. 50 65 80 85 TPS75003 www.ti.com SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 TYPICAL CHARACTERISTICS (continued) Measured using circuit in Figure 1 RDS,ON PMOSvs VIN RDS,ON NMOSvs VIN 12 12 10 10 TA = −40 C TA = +25 C 4 TA = +25 C 8 RDS, ON ( Ω ) 6 TA = +85 C 6 4 TA = +85 C 2 2 0 0 TA = −40C 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 2.0 2.5 3.0 3.5 VIN (V) 4.0 4.5 5.0 5.5 6.0 6.5 7.0 VIN (V) Figure 19. Figure 20. PRODUCT PREVIEW 2.0 LDO VOUT vs TA 2.525 2.520 VIN = 3.3V 2.515 2.510 VOUT (V) RDS,ON ( Ω) 8 2.505 2.500 2.495 2.490 2.485 2.480 2.475 −40 −15 10 35 60 85 Ambient Temperature (C) Figure 21. 11 TPS75003 www.ti.com SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 APPLICATION INFORMATION The TPS75003 is an integrated power management IC designed specifically to power DSPs and FPGAs such as the Xilinx Spartan-3 and Spartan-3L. Two non-synchronous buck controllers can be configured to supply up to 3A for both CORE and I/O rails. A low dropout linear regulator powers auxiliary rails up to 300mA. All channels have independent enable and soft-start, allowing control of inrush current and output voltage ramp time as required by the application. Figure 1 shows a typical application circuit for powering the Xilinx Spartan-3 FPGA. Table 1 shows component values that have been tested for use with 2A and 3A load currents. Other similar external components can be substituted as desired; however, in all cases the circuits that are used should be tested for compliance to application requirements. Table 1. Components Tested for 1A and 3A Load Circuits DATA FORTHCOMING FORTHCOMING DATA DATA FORTHCOMING OPERATION (BUCK CONTROLLERS) PRODUCT PREVIEW Channels 1 and 2 contain two identical non-synchronous buck controllers that use minimum on-time/minimum off-time hysteretic control. (Refer to Figure 1.) For clarity, BUCK1 is used throughout the discussion of device operation. When VOUT1 is below its target, an external PMOS (Q1) is turned on for at least the minimum on-time, increasing current through the inductor (L1) until VOUT1 reaches its target value or the current limit (set by R1) is reached. Once either of these conditions is met, the PMOS is switched off for at least the minimum off-time of the device. After the minimum off-time has passed, the output voltage is monitored and the switch is turned on again when necessary. When output current is low, the buck controllers operate in discontinuous mode. In this mode, each switching cycle begins at zero inductor current, rises to a maximum value, then falls back to zero current. When current reaches zero on the falling edge, ringing occurs at the resonant frequency of the inductor and stray switch node capacitance. This is normal operation; it does not affect circuit performance, and can be minimized if desired by using an RC snubber and/or a resistor in series with the gate of the PMOS, as shown in Figure 22. Q L R D 0.1µF f = measured resonant frequency at switch node R = 2πfL Figure 22. RC Snubber and Series Gate Resistor Used to Minimize Ringing At higher output currents, the TPS75003 operates in continuous mode. In continuous mode, there is no ringing at the switch node and VOUT is equal to VIN times the duty cycle of the switching waveform. When VIN approaches or falls below VOUT, the buck controllers operate in 100% duty cycle mode, fully turning on the external PMOS to allow regulation at lower dropout than would otherwise be possible. Enable (Buck Controllers) The enable pins (EN1 and EN2) for the buck controllers are active high. When the enable pin is driven low and input voltage is present at IN1 or IN2, an on-chip FET is turned on to discharge the soft-start pin SS1 or SS2, respectively. If the soft-start feature is being used, enable should be driven high at least 10µs after VIN is applied to ensure this discharge cycle occurs. 12 TPS75003 www.ti.com SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 UVLO (Buck Controllers) An under-voltage lockout circuit is present to prevent turning on the external PMOS (Q1 or Q2) until a reliable operating voltage is reached on the appropriate regulator (IN1 or IN2). This prevents the buck controllers from mis-operation at low input voltages. Current Limit (Buck Controllers) An external resistor (R1 or R2) is used to set the current limit for the external PMOS transistor (Q1 or Q2). These resistors are connected between IN1 and IS1 (or IN2 and IS2) to provide a reference voltage across these pins that is proportional to the current flowing through the PMOS transistor. This reference voltage is compared to an internal reference to determine if an over-current condition exists. When current limit is exceeded, the external PMOS is turned off for the minimum off-time. Current limit detection is disabled for 10ns any time the PMOS is turned on to avoid triggering on switching noise. In 100% duty cycle mode, current limit is always enabled. Current limit is calculated using the VIS1 or VIS2 specification in the Electrical Characteristics section, shown in Equation 1: VIS1,2 I LIMIT R1,2 (1) I RMS I OUT D I OUT VOUT V IN 2 P DISS I RMS R (2) For low-cost applications the IS1,2 pin can be connected to the drain of the PMOS, using RDS,ON instead of R1 or R2 to set current limit. Variations in the PMOS RDS,ON must be taken into account to ensure that current limit will protect external components such as the inductor, the diode, and the switch itself from damage as a result of over-current. Short-Circuit Protection (Buck Controllers) In an overload condition, the current rating of the external components (PMOS, diode, and inductor) can be exceeded. To help guard against this, the TPS75003 increases its minimum off-time when the voltage at the feedback pin is lower than the reference voltage. When the output is shorted (VFB is zero), minimum off-time is increased to approximately 4µs. The increase in off-time is proportional to the difference between the voltage at the feedback pin and the internal reference. Soft-Start (Buck Controllers) The buck controllers each have independent soft-start capability to limit inrush during start-up and to meet timing requirements of the Xilinx Spartan-3 FPGA. Limiting inrush current by using soft-start, or by staggering the turn-on of power rails, also guards against voltage drops at the input source due to its output impedance. Refer to the soft-start circuitry shown in Figure 23 and the soft-start timing diagram shown in Figure 24. BUCK 1 will be discussed in this section; it is identical to BUCK2. Note that pins SS1 and SS2 are very high-impedance and cannot be probed using a typical oscilloscope setup. When input voltage is applied at IN1 and EN1 is driven low, any charge on the SS pin is discharged by an on-chip pull-down transistor. When EN1 is driven high, an on-chip current source starts charging the external soft-start capacitor CSS1. The voltage on the capacitor is compared to the voltage across the current sense resistor R1 to determine if an over-current condition exists. If the voltage drop across the sense resistor goes above the reference voltage, then the external PMOS is shut off for the minimum off-time. This implementation provides a cycle-by-cycle current limit and allows the user to program the soft-start time over a wide range for most applications. For detailed information on choosing CSS1 and CSS2, see the section, Selecting the Soft-Start Cap. 13 PRODUCT PREVIEW The current limit resistor must be appropriately rated for the dissipated power determined by its RMS current calculated by Equation 2: TPS75003 www.ti.com SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 IN1 IS1 V IS1 Switch Control SW1 Soft Start Control SS1 EN1 Figure 23. Soft-Start Circuitry PRODUCT PREVIEW VIN Current Limit VSS1 VEN1 Time Figure 24. Soft-Start Timing Diagram Input Capacitor CIN1, CIN2 Selection (Buck Controllers) It is good analog design practice to place input capacitors near the inputs of the device in order to ensure a low impedance input supply. 10µF to 22µF of capacitance for each buck converter is adequate for most applications, and should be placed within 100mils (0.001in) of the IN1 and IN2 pins to minimize the effects of pulsed current switching noise on the soft-start circuitry during the first ~1V of output voltage ramp. Low ESR capacitors also help to minimize noise on the supply line. The minimum value of capacitance can be estimated using Equation 3: (12)L 0.3 I OUT (12)L (I L) C IN, MIN V(RIPPLE) V IN V (RIPPLE) V IN 2 14 2 (3) TPS75003 www.ti.com SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 Note that the capacitors must be able to handle the RMS current in continuous conduction mode, which can be calculated using Equation 4: I C,IN(RMS) I OUT VOUT V IN, MIN (4) Inductor Value Selection (Buck Controllers) The inductor is chosen based on inductance value and maximum current rating. Larger inductors reduce current ripple (and therefore, output voltage ripple) but are physically larger and more expensive. Inductors with lower DC resistance typically improve efficiency, but also have higher cost and larger physical size. The buck converters work well with inductor values between 4.7µF and 47µF in most applications. When selecting an inductor, the current rating should exceed the current limit set by RIS or RDS,ON (see Current Limit section). To determine the minimum inductor size, first determine if the device will operate in minimum on-time or minimum off-time mode. The device will operate in minimum on-time mode if Equation 5 is satisfied: t (OFF,min) VOUTV SCHOTTKYR L I OUT V INVOUTI OUT r DS(on)R L I OUT t ON, MIN (5) Minimum inductor size needed when operating in minimum on-time mode is given by Equation 6: VINV OUTI OUT r DS(on)RL IOUT tON, MIN L MIN I (6) Minimum inductor size needed when operating in minimum off-time mode is given by Equation 7: VOUTV SCHOTTKYR L I OUT t OFF, MIN L MIN I (7) External PMOS Transistor Selection (Buck Controllers) The external PMOS transistor is selected based on threshold voltage (VT), on-resistance (RDS,ON), gate capacitance (CG) and voltage rating. The PMOS VT magnitude must be much lower than the lowest voltage at IN1 or IN2 that will be used. A VT magnitude that is 0.5V less than the lowest input voltage is normally sufficient. The PMOS gate will see voltages from 0V to the maximum input voltage, so gate-to-source breakdown should be a few volts higher than the maximum input supply. The drain-to-source of the device will also see this full voltage swing, and should therefore be a few volts higher than the maximum input supply. The RMS current in the PMOS can be estimated by using Equation 8: I PMOS(RMS) I OUT D I OUT VOUT V IN (8) The power dissipated in the PMOS is comprised of both conduction and switching losses. Switching losses are typically insignificant. The conduction losses are a function of the RMS current and the RDS,ON of the PMOS, and are calculated by Equation 9: P (cond) I OUT D 2 r DS(on) 1TC T J25C I OUT D rDS(on) (9) 15 PRODUCT PREVIEW where RL = the inductor's DC resistance. TPS75003 SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 www.ti.com Diode Selection (Buck Controllers) The diode is off when the PMOS is on, and on when the PMOS is off. Since it will be turned on and off at a relatively high frequency, a Schottky diode is recommended for good performance. The peak current rating of the diode should exceed the peak current limit set by the sense resistor RIS1,2. A diode with low reverse leakage current and low forward voltage at operating current will optimize efficiency. Equation 10 calculates the estimated average power dissipation: I (diode)(RMS) I OUT1D I OUT 1 V OUT V IN (10) Output Capacitor Selection (Buck Controllers) The output capacitor is selected based on output voltage ripple and transient response requirements. As a result of the nature of the hysteretic control loop, a minimum ESR of a few tens of mΩ should be maintained for good operation unless a feed-forward resistor is used. Low ESR bulk tantalum or PosCap capacitors work best in most applications. A 1.0µF ceramic capacitor can be used in parallel with this capacitor to filter higher frequency spikes. The output voltage ripple can be estimated by Equation 11: V PP I ESR 8 C1 OUT f 1.1I ESR (11) PRODUCT PREVIEW To calculate the capacitance needed to achieve a given voltage ripple as a result of a load transient from zero output to full current, use Equation 12: C OUT L I OUT 2 VINV OUT V (12) If only ceramic or other very low ESR output capacitor configurations are desired, additional voltage ripple must be passed to the feedback pin. This can be accomplished by using the application circuit in Figure 1. Resistor R1B adds additional control signal to the feedback loop. This circuit works best with R1B = 2 to 4 x R1A. If R1B is too low, the output shows worse load regulation. R1A and R1B can be calculated using Equation 13: R1 1 1 1 and R1B 1 1 1 R1 R1 R1 R1 A B A Use Equation 14 to calculate R1A if R1B = (4)(R1A): R1 A 5 R1 4 (13) (14) Output Voltage Ripple Effect on VOUT (Buck Controllers) Output voltage ripple causes VOUT to be higher or lower than the target value by half of the peak-to-peak voltage ripple. For minimum on-time, the ripple adds to the voltage; for minimum off-time, it subtracts from the voltage. Soft-Start Capacitor Selection (Buck Controllers) BUCK1 is discussed in this section; it is identical to BUCK2. Soft-start is implemented on the buck controllers by ramping current limit from 0 to its target value (set by R1) over a user-defined time. This time is set by the external soft-start cap connected to pin SS1. If SS1 is left open, a small on-chip capacitor will provide a current limit ramp time of approximately 250µs. Figure 25 shows the effects of R1 and SS1 on the current limit start-up ramp. 16 TPS75003 www.ti.com SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 2.0A R1 = 33mΩ CSS1 = 0.01µF CSS1 = 0.01µF Current Limit R1 = 12mΩ 0.7A C SS1 = 0.01µF CSS1 = 0.01µF Time This soft-start current limit ramo can be used to provide inrush current control or output voltage ramp control. While the current limit ramp can be easily understood by looking at Figure 25, the output voltage ramp is a complex function of many variables. The dominant variables in this process are VOUT1, CSS1, IOUT1, and R1. Less important variables are VIN1 and L1. The best way to set a target start-up time is through bench measurement under target conditions, adjusting CSS1 to get the desired startup profile. To stay above a minimum start-up time, set the nominal start-up time to approximately five times the minimum. To stay below a maximum time, set the nominal start-up time at one-fifth of the maximum. Fastest start-up times occur at maximum VIN1, with minimum VOUT1, L1, COUT1, CSS1, and IOUT1. Slowest start-up times occur under opposite conditions. Refer to Figure 10 to Figure 14 for characterization curves showing how the start-up profile is affected by these critical parameters. Output Voltage Setting Selection (Buck Controllers) Output voltage is set using two resistors as shown for Buck2 in Figure 1. Output voltage is then calculated using Equation 15: V OUT VFB RR 1 5 6 (15) where VFB = 1.24V. LDO OPERATION The TPS75003 LDO uses a PMOS pass element and is offered in an adjustable version for ease of programming to any output voltage. When used to power VCC,AUX it is set to 2.5V; it can optionally be set to other output voltages to power other circuitry. The LDO has integrated soft-start, independent enable, and short-circuit and thermal protection. The LDO can be used to power VCC,AUX on the Xilinx Spartan-3 FPGA when 3.3V JTAG signals are used as described in Application Note SLVA159 (available for download from www.ti.com). Input Capacitor Selection (LDO) Although an input capacitor is not required, it is good analog design practice to connect a 0.1µF to 10µF low ESR capacitor across the input supply near the regulator. This capacitor counteracts reactive input sources and improves transient response, stability, and ripple rejection. A higher value capacitor may be needed if large, fast rise-time load transients are anticipated, or if the device is located far from its power source. 17 PRODUCT PREVIEW Figure 25. Effects of CSS1 and R1 on Current Ramp Limit TPS75003 SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 www.ti.com Output Capacitor Selection (LDO) A 2.2µF or greater capacitor is required near the output of the device to ensure stability. The LDO is stable with any capacitor type, including ceramic. If improved transient response or ripple rejection is required, larger and/or lower ESR output capacitors can be used. Soft-Start (LDO) The LDO uses an external soft-start capacitor, CSS3, to provide an RC-ramped reference voltage to the control loop. (See the Functional Block Diagram.) This is a voltage-controlled soft-start, as compared to the current-controlled soft-start used by the buck controllers. Setting Output Voltage (LDO) Output voltage is set using two resistors as shown in Figure 1. Output voltage is then calculated using Equation 16: V OUT VFB RR 1 3 4 (16) where VFB = 0.507V. Internal Current Limit (LDO) PRODUCT PREVIEW The internal current limit of the LDO helps protect the regulator during fault conditions. When an over-current condition is detected, the output voltage will be reduced until the current falls to a level that will not damage the device. For good device reliability, the LDO should not operate at current limit. Enable Pin (LDO) The active high enable pin (EN3) can be used to put the device into shutdown mode. If shutdown and soft-start capability are not required, EN3 can be tied to IN3. Dropout Voltage (LDO) The LDO uses a PMOS transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the pass device is in its linear region of operation, and the input-output resistance is the RDS,ON of the pass transistor. In this region, the regulator is said to be out of regulation; ripple rejection, line regulation, and load regulation degrade as (VIN – VOUT) falls much below 0.5V. Transient Response (LDO) The LDO does not have an on-chip pull-down circuit for output is over-voltage conditions. This feature permits applications that connect higher voltage sources such as an alternate power supply to the output. This design also results in an output overshoot of several percent if the load current quickly drops to zero. The amplitude of overshoot can be reduced by increasing COUT; the duration of overshoot can be reduced by adding a load resistor. Thermal Protection (LDO) Thermal protection disables the output when the junction temperature, TJ, reaches unsafe levels. When the junction cools, the output is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage. For good long term reliability, the device should not be continuously operated at or near thermal shutdown. 18 TPS75003 www.ti.com SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 Power Dissipation (LDO) The TPS75003 comes in a QFN-style package with an exposed lead frame on the package underside. The exposed lead frame is the primary path for removing heat and should be soldered to a PC board that is configured to remove the amount of power dissipated by the LDO, as calculated by Equation 17: P D VIN3V OUT3 I OUT3 (17) Power dissipation can be minimized by using the lowest possible input voltage necessary to assure the required output voltage. The two buck converters do not contribute a significant amount of dissipated power. Using heavier copper will increase the overall effectiveness of removing heat from the device. The addition of plated through-holes to heat-dissipating layers will also improve the heatsink effectiveness. PCB Layout Considerations As with any switching regulators, careful attention must be paid to board layout. A typical application circuit and corresponding recommended printed circuit board (PCB) layout with emphasis on the most sensitive areas are shown in Figure 26 through Figure 28. L2 VOUT1 EN1 Q2 C13, C15 D2 C3, C17 R5 PRODUCT PREVIEW C7 C1 C9 IS1 IN1 12 13 SW1 14 DGND 15 SS1 16 EN1 17 18 SS3 19 IN3 VIN AGND VIN 20 11 FB1 C6 DGND R9 9 8 7 6 5 4 3 FB2 R8 IS2 IN2 SW2 DGND SS2 EN3 C10 EN2 R6 10 FB3 C14 1 2 OUT3 VOUT3 VIN R7 EN3 EN2 C5, C18 R4 C8 Q1 VOUT2 L1 D1 C12, C16 Figure 26. Typical Application Circuit 19 TPS75003 SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 PRODUCT PREVIEW Figure 27. Recommended PCB Layout, Component Side, Top View 20 www.ti.com TPS75003 SBVS052A – OCTOBER 2004 – REVISED DECEMBER 2004 PRODUCT PREVIEW www.ti.com Figure 28. Recommended PCB Layout, Bottom Side, Top View 21 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2005, Texas Instruments Incorporated