TI TPS74201RGWT

TPS74201
TP
S7
420
1
TP
S7
42
01
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SBVS064F – DECEMBER 2005 – REVISED OCTOBER 2007
1.5A Ultra-LDO with Programmable Soft-Start
FEATURES
1
• Soft-Start (SS) Pin Provides a Linear Startup
with Ramp Time Set by External Capacitor
• 1% Accuracy Over Line, Load, and
Temperature
• Supports Input Voltages as Low as 0.9V with
External Bias Supply
• Adjustable Output (0.8V to 3.6V)
• Ultra-Low Dropout: 55mV at 1.5A (typ)
• Stable with Any or No Output Capacitor
• Excellent Transient Response
• Available in 5mm × 5mm × 1mm QFN and
DDPAK-7 Packages
• Open-Drain Power-Good (5 × 5 QFN)
• Active High Enable
2
APPLICATIONS
•
•
•
•
FPGA Applications
DSP Core and I/O Voltages
Post-Regulation Applications
Applications with Special Start-Up Time or
Sequencing Requirements
Hot-Swap and Inrush Controls
•
DESCRIPTION
The TPS74201 low-dropout (LDO) linear regulator
provides an easy-to-use robust power management
solution for a wide variety of applications.
User-programmable soft-start minimizes stress on the
input power source by reducing capacitive inrush
current on start-up. The soft-start is monotonic and
well suited for powering many different types of
processors and ASICs. The enable input and
power-good output allow easy sequencing with
external regulators. This complete flexibility permits
the user to configure a solution that will meet the
sequencing requirements of FPGAs, DSPs, and other
applications with special start-up requirements.
A precision reference and error amplifier deliver 1%
accuracy over load, line, temperature, and process.
Each LDO is stable with low-cost ceramic output
capacitors and the device is fully specified from
–40°C to +125°C. The TPS74201 is offered in a small
(5mm × 5mm) QFN package, yielding a highly
compact total solution size. For applications that
require additional power dissipation, the DDPAK
(KTW) package is also available.
CSS = 0mF
VIN
IN
CIN
1mF
R3
BIAS
EN
VBIAS
TPS74201
R1
GND
CSS
VOUT
OUT
SS
CBIAS
1mF
CSS = 0.001mF
PG
FB
VOUT
CSS = 0.0047mF
1V/div
COUT
R2
1.2V
Optional
1V/div
VEN
0V
Figure 1. Typical Application Circuit for the
TPS74201 (Adjustable)
Time (1ms/div)
Figure 2. Turn-On Response
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2007, Texas Instruments Incorporated
TPS74201
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SBVS064F – DECEMBER 2005 – REVISED OCTOBER 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
VOUT (2)
PRODUCT
TPS742xxyyyz
(1)
(2)
(3)
XX is nominal output voltage (for example, 12 = 1.2V, 15 = 1.5V, 01 = Adjustable). (3)
YYY is package designator.
Z is package quantity.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Output voltages from 0.9V to 1.5V in 50mV increments and 1.5V to 3.3V in 100mV increments are available through the use of
innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability.
For fixed 0.8V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS (1)
At TJ = –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND.
TPS74201
UNIT
–0.3 to +6
V
VEN Enable voltage range
–0.3 to +6
V
VPG Power-good voltage range
–0.3 to +6
V
0 to +1.5
mA
VSS SS pin voltage range
–0.3 to +6
V
VFB Feedback pin voltage range
–0.3 to +6
V
–0.3 to VIN + 0.3
V
VIN, VBIAS Input voltage range
IPG PG sink current
VOUT Output voltage range
IOUT Maximum output current
Internally limited
Output short circuit duration
Indefinite
PDISS Continuous total power dissipation
See Dissipation Ratings Table
TJ Operating junction temperature range
TSTG Storage junction temperature range
(1)
–40 to +125
°C
–55 to +150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
DISSIPATION RATINGS
(1)
(2)
2
PACKAGE
θJA
θJC
TA < +25°C
POWER RATING
DERATING FACTOR
ABOVE TA = +25°C
RGW (QFN) (1)
36.5°C/W
4.05°C/W
2.74W
27.4mW/°C
KTW (DDPAK) (2)
18.8°C/W
2.32°C/W
5.32W
53.2mW/°C
See Figure 31 for PCB layout description.
See Figure 34 for PCB layout description.
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ELECTRICAL CHARACTERISTICS
At VEN = 1.1V, VIN = VOUT + 0.3V, CIN = CBIAS = 0.1μF, COUT = 10μF, IOUT = 50mA, VBIAS = 5.0V, and TJ = –40°C to +125°C,
unless otherwise noted. Typical values are at TJ = +25°C.
TPS74201
PARAMETER
MAX
UNIT
VIN Input voltage range
VOUT + VDO
5.5
V
VBIAS Bias pin voltage range
2.375
5.25
V
0.804
V
VREF Internal reference (Adj.)
VOUT
TJ = +25°C
0.796
VIN = 5V, IOUT = 1.5A, VBIAS = 5V
VREF
Accuracy (1)
2.375V ≤ VBIAS ≤ 5.25V, 50mA ≤ IOUT ≤ 1.5A
VOUT/IOUT Load regulation
VIN dropout voltage (2)
VBIAS dropout voltage (2)
ICL Current limit
IBIAS Bias pin current
ISHDN
Shutdown supply current
(VIN)
IFB Feedback pin current (3)
V
±0.2
1
%
VOUT
(NOM)
+ 0.3 ≤ VIN ≤ 5.5V, QFN
0.0005
0.05
VOUT
(NOM)
+ 0.3 ≤ VIN ≤ 5.5V, DDPAK
0.0005
0.06
0mA ≤ IOUT ≤ 50mA
0.013
50mA ≤ IOUT ≤ 1.5A
0.04
%/V
%/mA
%/A
IOUT = 1.5A, VBIAS – VOUT (NOM) ≥ 1.62V, QFN
55
100
mV
IOUT = 1.5A, VBIAS – VOUT (NOM) ≥ 1.62V, DDPAK
60
120
mV
1.4
V
IOUT = 1.5A, VIN = VBIAS
VOUT = 80% × VOUT (NOM)
4
A
IOUT = 0mA to 1.5A
2
4
mA
VEN ≤ 0.4V
1
100
μA
68
250
nA
IOUT = 50mA to 1.5A
1.8
–250
300kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V
42
Power-supply rejection
(VBIAS to VOUT)
1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V
62
300kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V
50
100Hz to 100kHz, IOUT = 1.5A, CSS = 0.001μF
16 × VOUT
μVRMS
IOUT = 50mA to 1.5A at 1A/μs, COUT = none
3.5
%VOUT
IOUT = 1.5A, CSS = open
100
μs
%VOUT droop during load
transient
ISS Soft-start charging current VSS = 0.4V
VEN, LO Enable input low level
1
μA
V
0
0.4
VEN = 5V
VIT PG trip threshold
VOUT decreasing
86.5
VHYS PG trip hysteresis
IPG = 1mA (sinking), VOUT < VIT
IPG, LKG PG leakage current
VPG = 5.25V, VOUT > VIT
Thermal shutdown
temperature
μs
0.1
1
μA
90
93.5
%VOUT
3
VPG, LO PG output low voltage
V
mV
20
IEN Enable pin current
TSD
0.73
50
VEN, DG Enable pin deglitch time
Operating junction
temperature
dB
5.5
Enable pin hysteresis
TJ
dB
1.1
0.5
VEN, HI Enable input high level
(1)
(2)
(3)
3.6
Power-supply rejection
(VIN to VOUT)
tSTR Minimum startup time
HYS
0.8
73
Noise Output noise voltage
VEN,
–1
TYP
1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V
PSRR
VTRAN
MIN
Output voltage range
VOUT/VIN Line regulation
VDO
TEST CONDITIONS
0.03
–40
Shutdown, temperature increasing
+155
Reset, temperature decreasing
+140
%VOUT
0.3
V
1
μA
+125
°C
°C
Adjustable devices tested at 0.8V; resistor tolerance is not taken into account.
Dropout is defined as the voltage from the input to VOUT when VOUT is 2% below nominal.
IFB current flow is out of the device.
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SBVS064F – DECEMBER 2005 – REVISED OCTOBER 2007
BLOCK DIAGRAM
IN
Current
Limit
BIAS
UVLO
OUT
VOUT
Thermal
Limit
0.73mA
R1
SS
CSS
Soft-Start
Discharge
VOUT = 0.8 x (1 +
0.8V
Reference
R1
)
R2
FB
PG
Hysteresis
and De-Glitch
EN
R2
0.9 ´ VREF
GND
Table 1. Standard 1% Resistor Values for Programming the Output Voltage (1)
(1)
R1 (kΩ)
R2 (kΩ)
VOUT (V)
Short
Open
0.8
0.619
4.99
0.9
1.13
4.53
1.0
1.37
4.42
1.05
1.87
4.99
1.1
2.49
4.99
1.2
4.12
4.75
1.5
3.57
2.87
1.8
3.57
1.69
2.5
3.57
1.15
3.3
VOUT = 0.8 × (1 + R1/R2)
Table 2. Standard Capacitor Values for Programming the Soft-Start Time (1)
(1)
4
CSS
SOFT-START TIME
Open
0.1ms
470pF
0.5ms
1000pF
1ms
4700pF
5ms
0.01μF
10ms
0.015μF
16ms
tSS(s) = 0.8 × CSS(F)/7.3 × 10–7
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SBVS064F – DECEMBER 2005 – REVISED OCTOBER 2007
7-Lead
DDPAK (KTW)
Surface-Mount
IN
NC
NC
NC
OUT
5
4
3
2
1
5 ´ 5 QFN (RGW)
Package ¾ Top View
IN
6
20
OUT
IN
7
19
OUT
IN
8
18
OUT
PG
9
17
NC
BIAS
10
16
FB
11
12
13
14
15
EN
GND
NC
NC
SS
TPS74201
1 2 3 4 5 6 7
SS
OUT IN EN
FB GND BIAS
PIN DESCRIPTIONS
NAME
KTW (DDPAK)
RGW (QFN)
DESCRIPTION
IN
5
5–8
Unregulated input to the device.
EN
7
11
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts
the regulator into shutdown mode. This pin must not be left floating.
SS
1
15
Soft-Start pin. A capacitor connected on this pin to ground sets the start-up
time. If this pin is left floating, the regulator output soft-start ramp time is
typically 100μs.
BIAS
6
10
Bias input voltage for error amplifier, reference, and internal control circuits.
PG
N/A
9
Power-Good (PG) is an open-drain, active-high output that indicates the status
of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a
high-impedance state. When VOUT is below this threshold the pin is driven to a
low-impedance state. A pull-up resistor from 10kΩ to 1MΩ should be connected
from this pin to a supply up to 5.5V. The supply can be higher than the input
voltage. Alternatively, the PG pin can be left floating if output monitoring is not
necessary.
FB
2
16
This pin is the feedback connection to the center tap of an external resistor
divider network that sets the output voltage. This pin must not be left floating.
OUT
3
1, 18–20
NC
N/A
2–4, 13, 14, 17
GND
4
12
PAD/TAB
Regulated output voltage. No capacitor is required on this pin for stability.
No connection. This pin can be left floating or connected to GND to allow better
thermal contact to the top-side plane.
Ground
Should be soldered to the ground plane for increased thermal performance.
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TYPICAL CHARACTERISTICS
At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1μF, CBIAS = 4.7μF, CSS =
0.01μF, and COUT = 10μF, unless otherwise noted.
LOAD REGULATION
1.0
LOAD REGULATION
0.050
Referred to IOUT = 50mA
0.9
Referred to IOUT = 50mA
0.025
0.7
0.6
-40°C
0.5
0.4
+25°C
0.3
0.2
0.1
0
Change in VOUT (%)
Change in VOUT (%)
0.8
-0.050
-40°C
-0.075
+125°C
-0.100
+125°C
0
+25°C
-0.025
-0.125
-0.150
-0.1
0
10
20
30
40
50
50
500
1000
1500
IOUT (mA)
IOUT (mA)
Figure 3.
Figure 4.
LINE REGULATION
VIN DROPOUT VOLTAGE vs
IOUT AND TEMPERATURE (TJ)
0.05
100
0.04
0.02
Dropout Voltage (mV)
Change in VOUT (%)
0.03
TJ = -40°C
0.01
0
-0.01
TJ = +25°C
TJ = +125°C
-0.02
75
+125°C
50
+25°C
25
-40°C
-0.03
-0.04
0
-0.05
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
0.5
VIN - VOUT (V)
IOUT (A)
Figure 6.
VIN DROPOUT VOLTAGE vs
VBIAS – VOUT AND TEMPERATURE (TJ)
VIN DROPOUT VOLTAGE vs
VBIAS – VOUT AND TEMPERATURE (TJ)
60
IOUT = 1.5A
180
IOUT = 500mA
50
Dropout Voltage (mV)
160
Dropout Voltage (mV)
1.5
Figure 5.
200
140
120
+125°C
100
+25°C
80
60
40
40
+125°C
30
+25°C
20
10
-40°C
20
-40°C
0
0
0.9
1.4
1.9
2.4
2.9
3.4
3.9
0.9
VBIAS - VOUT (V)
1.4
1.9
2.4
2.9
3.4
3.9
VBIAS - VOUT (V)
Figure 7.
6
1.0
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1μF, CBIAS = 4.7μF, CSS =
0.01μF, and COUT = 10μF, unless otherwise noted.
VBIAS DROPOUT VOLTAGE vs
IOUT AND TEMPERATURE
VBIAS PSRR vs FREQUENCY
1400
Power-Supply Rejection Ratio (dB)
80
Dropout Voltage (mV)
1300
1200
+25°C
+125°C
1100
1000
-40°C
900
800
700
600
70
60
50
40
30
20
VIN = 1.8, VOUT = 1.5V
VBIAS = 3.3V, IOUT = 1.5A
10
0
500
0
0.5
1.0
1.5
10
100
1k
IOUT (A)
10k
Figure 9.
VIN PSRR vs FREQUENCY
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
90
COUT = 10mF
60
50
40
30
20
COUT = 0mF
10
VIN = 1.8, VOUT = 1.5V, IOUT = 100mA
0
10
100
1k
10k
VIN = 1.8, VOUT = 1.5V, IOUT = 1.5A
90
80
70
COUT = 100mF
60
COUT = 10mF
50
40
30
20
10
COUT = 0mF
0
100k
1M
10
10M
100
Figure 11.
Figure 12.
700kHz
60
50
300kHz
100kHz
20
10
IOUT = 1.5A
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
Output Spectral Noise Density (mV/ÖHz)
Power-Supply Rejection Ratio (dB)
1kHz
40
100k
1M
10M
NOISE SPECTRAL DENSITY
80
0
10k
Frequency (Hz)
VIN PSRR vs VIN – VOUT
30
1k
Frequency (Hz)
90
70
10M
VIN PSRR vs FREQUENCY
100
COUT = 100mF
70
1M
Figure 10.
100
80
100k
Frequency (Hz)
1
IOUT = 100mA
VOUT = 1.1V
CSS = 1nF
CSS = 0nF
0.1
CSS = 10nF
0.01
100
VIN - VOUT (V)
1k
10k
100k
Frequency (Hz)
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1μF, CBIAS = 4.7μF, CSS =
0.01μF, and COUT = 10μF, unless otherwise noted.
VBIAS LINE TRANSIENT (1.5A)
VIN LINE TRANSIENT
COUT = 1000mF
10mV/div
10mV/div
10mV/div
COUT = 100mF
COUT = 2 x 470mF (OSCON)
COUT = 100mF (Cer.)
10mV/div
COUT = 10mF
COUT = 10mF (Cer.)
10mV/div
10mV/div
COUT = 0mF
COUT = 0mF
10mV/div
10mV/div
1V/ms
1V/div
500mV/div
1V/ms
Time (50ms/div)
Time (50ms/div)
Figure 15.
Figure 16.
OUTPUT LOAD TRANSIENT RESPONSE
TURN-ON RESPONSE
COUT = 2 x 470mF (OSCON)
CSS = 0mF
50mV/div
50mV/div
CSS = 0.0047mF
1V/div
50mV/div
VOUT
CSS = 0.001mF
COUT = 100mF (Cer.)
COUT = 10mF (Cer.)
50mV/div
COUT = 0mF
1.5A
1A/div
1.2V
1V/div
VEN
0V
1A/ms
50mA
Time (1ms/div)
Time (50ms/div)
Figure 17.
Figure 18.
POWER-UP/POWER-DOWN
IBIAS vs IOUT AND TEMPERATURE
2.85
1V/div
VIN = VBIAS = VEN
VPG (500mV/div)
VOUT
Bias Current (mA)
2.65
+125°C
2.45
2.25
2.05
+25°C
1.85
1.65
-40°C
1.45
1.25
Time (20ms/div)
0
0.5
1.0
1.5
IOUT (A)
Figure 19.
8
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, EN = VIN, CIN = 1μF, CBIAS = 4.7μF, CSS =
0.01μF, and COUT = 10μF, unless otherwise noted.
IBIAS vs VBIAS AND VOUT
IBIAS SHUTDOWN vs TEMPERATURE
3.0
0.45
2.8
2.4
2.2
+25°C
2.0
1.8
1.6
-40°C
1.4
VBIAS = 2.375V
0.35
Bias Current (mA)
Bias Current (mA)
0.40
+125°C
2.6
0.30
VBIAS = 5.5V
0.25
0.20
0.15
0.10
0.05
1.2
1.0
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-40
0
-20
VBIAS (V)
20
Figure 21.
60
80
100
120
Figure 22.
SOFT-START CHARGING CURRENT (ISS) vs
TEMPERATURE
LOW-LEVEL PG VOLTAGE vs PG CURRENT
1.0
VOL Low-Level PG Voltage (V)
765
750
735
ISS (nA)
40
Junction Temperature (°C)
720
705
690
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
675
-40
-20
0
20
40
60
80
100
120
0
2
Junction Temperature (°C)
6
4
8
10
12
PG Current (mA)
Figure 23.
Figure 24.
OUTPUT SHORT-CIRCUIT RECOVERY
IOUT
500mA/div
VOUT
50mV/div
Output Shorted
Output Open
Time (20ms/div)
Figure 25.
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APPLICATION INFORMATION
The TPS74201 belongs to a family of new generation
ultra-low dropout regulators that feature soft-start and
tracking capabilities. These regulators use a low
current bias input to power all internal control
circuitry, allowing the NMOS pass transistor to
regulate very low input and output voltages.
The use of an NMOS-pass FET offers several critical
advantages for many applications. Unlike a PMOS
topology device, the output capacitor has little effect
on loop stability. This architecture allows the
TPS74201 to be stable with any or even no output
capacitor. Transient response is also superior to
PMOS topologies, particularly for low VIN
applications.
The
TPS74201
features
a
programmable
voltage-controlled soft-start circuit that provides a
smooth, monotonic start-up and limits startup inrush
currents that may be caused by large capacitive
loads. A power-good (PG) output is available to allow
supply monitoring and sequencing of other supplies.
An enable (EN) pin with hysteresis and deglitch
allows slow-ramping signals to be used for
sequencing the device. The low VIN and VOUT
capability allows for inexpensive, easy-to-design, and
efficient linear regulation between the multiple supply
voltages often present in processor intensive
systems.
Figure 26 is a typical application circuit for the
TPS74201 adjustable output device.
R1 and R2 can be calculated for any output voltage
using the formula shown in Figure 26. Refer to
Table 1 for sample resistor values of common output
voltages. In order to achieve the maximum accuracy
specifications, R2 should be ≤ 4.99kΩ.
VIN
IN
CIN
1m F
PG
R3
BIAS
EN
VBIAS
TPS74201
R1
SS
CBIAS
1m F
VOUT
OUT
FB
GND
CSS
COUT
Optional
R2
VOUT = 0.8 ´
(
1+
R1
R2
INPUT, OUTPUT, AND BIAS CAPACITOR
REQUIREMENTS
The device does not require any output capacitor for
stability. If an output capacitor is needed, the device
is designed to be stable for all available types and
values of output capacitance. The device is also
stable with multiple capacitors in parallel, which can
be of any type or value.
The capacitance required on the IN and BIAS pins is
strongly dependent on the input supply source
impedance. To counteract any inductance in the
input, the minimum recommended capacitor for VIN
and VBIAS is 1μF. If VIN and VBIAS are connected to
the same supply, the recommended minimum
capacitor for VBIAS is 4.7μF. Good quality, low ESR
capacitors should be used on the input; ceramic X5R
and X7R capacitors are preferred. These capacitors
should be placed as close the pins as possible for
optimum performance.
TRANSIENT RESPONSE
The TPS74201 was designed to have transient
response within 5% for most applications without any
output capacitor. In some cases, the transient
response may be limited by the transient response of
the input supply. This limitation is especially true in
applications where the difference between the input
and output is less than 300mV. In this case, adding
additional input capacitance improves the transient
response much more than just adding additional
output capacitance would do. With a solid input
supply, adding additional output capacitance reduces
undershoot and overshoot during a transient at the
expense of a slightly longer VOUT recovery time. Refer
to Figure 17 in the Typical Characteristics section.
Since the TPS74201 is stable without an output
capacitor, many applications may allow for little or no
capacitance at the LDO output. For these
applications, local bypass capacitance for the device
under power may be sufficient to meet the transient
requirements of the application. This design reduces
the total solution cost by avoiding the need to use
expensive high-value capacitors at the LDO output.
)
Figure 26. Typical Application Circuit for the
TPS74201 (Adjustable)
10
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DROPOUT VOLTAGE
VIN
The TPS74201 offers industry-leading dropout
performance, making it well-suited for high-current
low VIN/low VOUT applications. The extremely low
dropout of the TPS74201 allows the device to be
used in place of a DC/DC converter and still achieve
good efficiencies. This efficiency allows the user to
rethink the power architecture for their applications to
achieve the smallest, simplest, and lowest cost
solution.
There are two different specifications for dropout
voltage with the TPS74201. The first specification
(see Figure 27) is referred to as VIN Dropout and is
for users who wish to apply an external bias voltage
to achieve low dropout. This specification assumes
that VBIAS is at least 1.62V above VOUT, which is the
case for VBIAS when powered by a 3.3V rail with 5%
tolerance and with VOUT = 1.5V. If VBIAS is higher than
3.3V × 0.95 or VOUT is less than 1.5V, VIN dropout is
less than specified.
BIAS
Reference
IN
VBIAS = 5V ± 5%
VIN = 1.8V
VOUT = 1.5V
IOUT = 1.5A
Efficiency = 83%
OUT
VOUT
FB
Simplified Block Diagram
Figure 27. Typical Application of the TPS74201
Using an Auxiliary Bias Rail
The second specification (see Figure 28) is referred
to as VBIAS Dropout and is for users who wish to tie
IN and BIAS together. This option allows the device
to be used in applications where an auxiliary bias
voltage is not available or low dropout is not required.
Dropout is limited by BIAS in these applications
because VBIAS provides the gate drive to the pass
FET and therefore must be 1.4V above VOUT.
Because of this usage, IN and BIAS tied together
easily consume huge power. Pay attention not to
exceed the power rating of the IC package.
BIAS
Reference
IN
VBIAS = 3.3V ± 5%
VIN = 3.3V ± 5V
VOUT = 1.5V
IOUT = 1.5A
Efficiency = 45%
OUT
VOUT
FB
Simplified Block Diagram
Figure 28. Typical Application of the TPS74201
Without an Auxiliary Bias
PROGRAMMABLE SOFT-START
The TPS74201 features a programmable, monotonic,
voltage-controlled soft-start that is set with an
external capacitor (CSS). This feature is important for
many applications because it eliminates power-up
initialization problems when powering FPGAs, DSPs,
or other processors. The controlled voltage ramp of
the output also reduces peak inrush current during
start-up, minimizing start-up transients to the input
power bus.
To achieve a linear and monotonic soft-start, the
TPS74201 error amplifier tracks the voltage ramp of
the external soft-start capacitor until the voltage
exceeds the internal reference. The soft-start ramp
time depends on the soft-start charging current (ISS),
soft-start capacitance (CSS), and the internal
reference voltage (VREF), and can be calculated using
Equation 1:
ǒVREF CSSǓ
t SS +
I SS
(1)
If large output capacitors are used, the device current
limit (ICL) and the output capacitor may set the
start-up time. In this case, the start-up time is given
by Equation 2:
t SSCL +
ǒVOUT(NOM)
COUTǓ
I CL(MIN)
(2)
VOUT(NOM) is the nominal set output voltage as set by
the user, COUT is the output capacitance, and ICL(MIN)
is the minimum current limit for the device. In
applications where monotonic startup is required, the
soft-start time given by Equation 1 should be set to
be greater than Equation 2.
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The maximum recommended soft-start capacitor is
0.015μF. Larger soft-start capacitors can be used and
will not damage the device; however, the soft-start
capacitor discharge circuit may not be able to fully
discharge the soft-start capacitor when enabled.
Soft-start capacitors larger than 0.015μF could be a
problem in applications where the user needs to
rapidly pulse the enable pin and still requires the
device to soft-start from ground. CSS must be
low-leakage; X7R, X5R, or C0G dielectric materials
are preferred. Refer to Table 2 for suggested
soft-start capacitor values.
SEQUENCING REQUIREMENTS
The device can have VIN, VBIAS, and VEN sequenced
in any order without causing damage to the device.
However, for the soft-start function to work as
intended, certain sequencing rules must be applied.
Enabling the device after VIN and VBIAS are present is
preferred, and can be accomplished using a digital
output from a processor or supply supervisor. An
analog signal from an external RC circuit, as shown
in Figure 29, can also be used as long as the delay
time is long enough for VIN and VBIAS to be present.
VIN
IN
VOUT
OUT
CIN
1 mF
R1
BIAS TPS74201
FB
EN
SS
R2
R
VBIAS
CBIAS
1 mF
GND
C
CSS
Figure 29. Soft-Start Delay Using an RC Circuit on
Enable
If a signal is not available to enable the device after
IN and BIAS, simply connecting EN to IN is
acceptable for most applications as long as VIN is
greater than 1.1V and the ramp rate of VIN and VBIAS
is faster the set soft-start ramp rate. If the ramp rate
of the input sources is slower than the set soft-start
time, the output will track the slower supply minus the
dropout voltage until it reaches the set output voltage.
If EN is connected to BIAS, the device will soft-start
as programmed provided that VIN is present before
VBIAS. If VBIAS and VEN are present before VIN is
applied and the set soft-start time has expired then
VOUT will track VIN.
NOTE: When VBIAS and VEN are present and VIN is
not supplied, this device outputs approximately 50μA
of current from OUT. Although this condition will not
cause any damage to the device, the output current
may charge up the OUT node if total resistance
between OUT and GND (including external feedback
resistors) is less than 10kΩ.
12
OUTPUT NOISE
The TPS74201 provides low output noise when a
soft-start capacitor is used. When the device reaches
the end of the soft-start cycle, the soft-start capacitor
serves as a filter for the internal reference. By using a
0.001μF soft-start capacitor, the output noise is
reduced by half and is typically 30μVRMS for a 1.2V
output (10Hz to 100kHz). Because most of the output
noise is generated by the internal reference, the
noise is a function of the set output voltage. The RMS
noise with a 0.001μF soft-start capacitor is given in
Equation 3.
ǒmVV Ǔ
V NǒmVRMSǓ + 25
RMS
V OUT(V)
(3)
The low output noise of the TPS74201 makes it a
good choice for powering transceivers, PLLs, or other
noise-sensitive circuitry.
ENABLE/SHUTDOWN
The enable (EN) pin is active high and is compatible
with standard digital signaling levels. VEN below 0.4V
turns the regulator off, while VEN above 1.1V turns the
regulator on. Unlike many regulators, the enable
circuitry has hysteresis and deglitching for use with
relatively slow-ramping analog signals. This
configuration allows the TPS74201 to be enabled by
connecting the output of another supply to the EN
pin. The enable circuitry typically has 50mV of
hysteresis and a deglitch circuit to help avoid on-off
cycling because of small glitches in the VEN signal.
The enable threshold is typically 0.8V and varies with
temperature and process variations. Temperature
variation is approximately –1mV/°C; therefore,
process variation accounts for most of the variation in
the enable threshold. If precise turn-on timing is
required, a fast rise-time signal should be used to
enable the TPS74201.
If not used, EN can be connected to either IN or
BIAS. If EN is connected to IN, it should be
connected as close as possible to the largest
capacitance on the input to prevent voltage droops on
that line from triggering the enable circuit.
POWER-GOOD (QFN Package Only)
The power-good (PG) pin is an open-drain output and
can be connected to any 5.5V or lower rail through an
external pull-up resistor. This pin requires at least
1.1V on VBIAS in order to have a valid output. The PG
output is high-impedance when VOUT is greater than
VIT + VHYS. If VOUT drops below VIT or if VBIAS drops
below 1.9V, the open-drain output turns on and pulls
the PG output low. The PG pin also asserts when the
device is disabled. The recommended operating
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condition of PG pin sink current is up to 1mA, so the
pull-up resistor for PG should be in the range of 10kΩ
to 1MΩ. PG is only provided on the QFN package. If
output voltage monitoring is not needed, the PG pin
can be left floating.
The internal protection circuitry of the TPS74201 is
designed to protect against overload conditions. It is
not intended to replace proper heatsinking.
Continuously running the TPS74201 into thermal
shutdown degrades device reliability.
INTERNAL CURRENT LIMIT
LAYOUT RECOMMENDATIONS AND POWER
DISSIPATION
The TPS74201 features a factory-trimmed, accurate
current limit that is flat over temperature and supply
voltage. The current limit allows the device to supply
surges of up to 1.8A and maintain regulation. The
current limit responds in about 10μs to reduce the
current during a short-circuit fault. Recovery from a
short-circuit condition is well-controlled and results in
very little output overshoot when the load is removed.
See Figure 25 in the Typical Characteristics section
for a graph of IOUT versus VOUT performance.
The internal current limit protection circuitry of the
TPS74201 is designed to protect against overload
conditions. It is not intended to allow operation above
the rated current of the device. Continuously running
the TPS74201 above the rated current degrades
device reliability.
THERMAL PROTECTION
Thermal protection disables the output when the
junction temperature rises to approximately +160°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C, the
output circuitry is enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage as a result of
overheating.
Activation of the thermal protection circuit indicates
excessive
power
dissipation
or
inadequate
heatsinking.
For
reliable
operation,
junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete design
(including
heatsink),
increase
the
ambient
temperature until thermal protection is triggered; use
worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+40°C above the maximum expected ambient
condition of the application. This condition produces a
worst-case junction temperature of +125°C at the
highest
expected
ambient
temperature
and
worst-case load.
An optimal layout can greatly improve transient
performance, PSRR, and noise. To minimize the
voltage droop on the input of the device during load
transients, the capacitance on IN and BIAS should be
connected as close as possible to the device. This
capacitance also minimizes the effects of parasitic
inductance and resistance of the input source and
can therefore improve stability. To achieve optimal
transient performance and accuracy, the top side of
R1 in Figure 26 should be connected as close as
possible to the load. If BIAS is connected to IN it is
recommended to connect BIAS as close to the sense
point of the input supply as possible. This connection
minimizes the voltage droop on BIAS during transient
conditions and can improve the turn-on response.
Knowing the device power dissipation and proper
sizing of the thermal plane that is connected to the
tab or pad is critical to avoiding thermal shutdown
and ensuring reliable operation. Power dissipation of
the device depends on input voltage and load
conditions and can be calculated using Equation 4:
P D + ǒVIN * VOUTǓ
I OUT
(4)
Power dissipation can be minimized and greater
efficiency can be achieved by using the lowest
possible input voltage necessary to achieve the
required output voltage regulation.
On both the QFN (RGW) and DDPAK (KTW)
packages, the primary conduction path for heat is
through the exposed pad or tab to the printed circuit
board (PCB). The pad or tab can be connected to
ground or be left floating; however, it should be
attached to an appropriate amount of copper PCB
area to ensure the device will not overheat. The
maximum junction-to-ambient thermal resistance
depends on the maximum ambient temperature,
maximum device junction temperature, and power
dissipation of the device and can be calculated using
Equation 5:
()125OC * T A)
R qJA +
PD
(5)
Knowing the maximum RθJA and system air flow, the
minimum amount of PCB copper area needed for
appropriate heatsinking can be calculated using
Figure 30 through Figure 34.
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PCB Top View
PCB Cross Section
TJ
RqJC
TC
RqCS
0.062in.
TS
RqSA
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
0.5in
TA
1.0in
RqJA = RqJC + RqCS + RqSA
2.0in
2
2
2
55
50
0 LFM
qJA (°C/W)
45
40
150 LFM
35
250 LFM
30
25
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
2
Area (in )
Figure 30. PCB Layout and Corresponding RθJA Data, Buried Thermal Plane, No Vias Under Thermal Pad
14
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PCB Top View
PCB Cross Section
TJ
RqJC
TC
RqCS
0.062in.
TS
0.5in
RqSA
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
1.0in
TA
2.0in
2
2
2
RqJA = RqJC + RqCS + RqSA
50
45
0 LFM
qJA (°C/W)
40
150 LFM
35
30
250 LFM
25
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2
Area (in )
Figure 31. PCB Layout and Corresponding RθJA Data, Buried Thermal Plane, Vias Under Thermal Pad
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SBVS064F – DECEMBER 2005 – REVISED OCTOBER 2007
PCB Top View
PCB Cross Section
TJ
RqJC
TC
RqCS
0.062in.
TS
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
RqSA
0.5in
TA
1.0in
2.0in
2
2
2
RqJA = RqJC + RqCS + RqSA
90
80
qJA (°C/W)
70
0 LFM
60
150 LFM
50
40
250 LFM
30
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2
Area (in )
Figure 32. PCB Layout and Corresponding RθJA Data, Top Layer Thermal Plane
16
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PCB Top View
PCB Cross Section
2.0in
2
TJ
RqJC
1.0in
2
TC
0.5in
RqCS
0.062in.
2
TS
RqSA
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
TA
RqJA = RqJC + RqCS + RqSA
35
0 LFM
qJA (°C/W)
30
25
20
15
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2
Area (in )
Figure 33. PCB Layout and Corresponding RθJA, Buried Thermal Plane
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SBVS064F – DECEMBER 2005 – REVISED OCTOBER 2007
PCB Top View
PCB Cross Section
2.0in
2
TJ
1.0in
RqJC
TC
2
0.5in
2
RqCS
0.062in.
TS
RqSA
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
TA
RqJA = RqJC + RqCS + RqSA
55
50
45
qJA (°C/W)
40
35
30
0 LFM
25
20
15
10
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
2
Area (in )
Figure 34. PCB Layout and Corresponding RθJA, Top Layer Thermal Plane
18
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PACKAGE OPTION ADDENDUM
www.ti.com
20-Sep-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS74201KTWR
ACTIVE
DDPAK
KTW
7
500
Green (RoHS &
no Sb/Br)
CU SN
Level-3-245C-168 HR
TPS74201KTWRG3
ACTIVE
DDPAK
KTW
7
500
Green (RoHS &
no Sb/Br)
CU SN
Level-3-245C-168 HR
TPS74201KTWT
ACTIVE
DDPAK
KTW
7
50
Green (RoHS &
no Sb/Br)
CU SN
Level-3-245C-168 HR
TPS74201KTWTG3
ACTIVE
DDPAK
KTW
7
50
Green (RoHS &
no Sb/Br)
CU SN
Level-3-245C-168 HR
TPS74201RGWR
ACTIVE
QFN
RGW
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS74201RGWRG4
ACTIVE
QFN
RGW
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS74201RGWT
ACTIVE
QFN
RGW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS74201RGWTG4
ACTIVE
QFN
RGW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TPS74201KTWR
KTW
7
SITE 41
330
24
10.6
15.6
4.9
16
24
Q2
TPS74201KTWT
KTW
7
SITE 41
330
24
10.6
15.6
4.9
16
24
Q2
TPS74201RGWR
RGW
20
SITE 41
330
12
5.3
5.3
1.5
8
12
Q2
TPS74201RGWT
RGW
20
SITE 41
180
12
5.3
5.3
1.5
8
12
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Oct-2007
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
TPS74201KTWR
KTW
7
SITE 41
346.0
346.0
41.0
TPS74201KTWT
KTW
7
SITE 41
346.0
346.0
41.0
TPS74201RGWR
RGW
20
SITE 41
346.0
346.0
29.0
TPS74201RGWT
RGW
20
SITE 41
190.0
212.7
31.75
Pack Materials-Page 2
MECHANICAL DATA
MPSF015 – AUGUST 2001
KTW (R-PSFM-G7)
PLASTIC FLANGE-MOUNT
0.410 (10,41)
0.385 (9,78)
0.304 (7,72)
–A–
0.006
–B–
0.303 (7,70)
0.297 (7,54)
0.0625 (1,587) H
0.055 (1,40)
0.0585 (1,485)
0.300 (7,62)
0.064 (1,63)
0.045 (1,14)
0.252 (6,40)
0.056 (1,42)
0.187 (4,75)
0.370 (9,40)
0.179 (4,55)
0.330 (8,38)
H
0.296 (7,52)
A
0.605 (15,37)
0.595 (15,11)
0.012 (0,305)
C
0.000 (0,00)
0.019 (0,48)
0.104 (2,64)
0.096 (2,44)
H
0.017 (0,43)
0.050 (1,27)
C
C
F
0.034 (0,86)
0.022 (0,57)
0.010 (0,25) M
B
0.026 (0,66)
0.014 (0,36)
0°~3°
AM C M
0.183 (4,65)
0.170 (4,32)
4201284/A 08/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Lead width and height dimensions apply to the
plated lead.
D. Leads are not allowed above the Datum B.
E. Stand–off height is measured from lead tip
with reference to Datum B.
F. Lead width dimension does not include dambar
protrusion. Allowable dambar protrusion shall not
cause the lead width to exceed the maximum
dimension by more than 0.003”.
G. Cross–hatch indicates exposed metal surface.
H. Falls within JEDEC MO–169 with the exception
of the dimensions indicated.
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