TI TPS74401RGWR

TP
S
744
01
TPS74401
TP
S7
44
01
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SBVS066D – DECEMBER 2005 – REVISED AUGUST 2006
3.0A Ultra-Low Dropout Linear Regulator
FEATURES
•
Soft-Start (SS) Pin Provides a Linear Startup
with Ramp Time Set by External Capacitor
1% Accuracy Over Line, Load, and
Temperature
Supports Input Voltages as Low as 0.9V with
External Bias Supply
Adjustable Output (0.8V to 3.6V)
Ultra-Low Dropout: 115mV at 3.0A (typ)
Stable with Any or No Output Capacitor
Excellent Transient Response
Available in 5mm × 5mm × 1mm QFN and
DDPAK-7 Packages
Open-Drain Power-Good (QFN only)
Active High Enable
•
•
•
•
•
•
•
•
•
APPLICATIONS
•
•
•
•
FPGA Applications
DSP Core and I/O Voltages
Post-Regulation Applications
Applications with Special Start-Up Time or
Sequencing Requirements
Hot-Swap and Inrush Controls
•
DESCRIPTION
The TPS74401 low-dropout (LDO) linear regulator
provides an easy-to-use robust power management
solution for a wide variety of applications.
User-programmable soft-start minimizes stress on
the input power source by reducing capacitive inrush
current on start-up. The soft-start is monotonic and
well-suited for powering many different types of
processors and ASICs. The enable input and
power-good output allow easy sequencing with
external regulators. This complete flexibility permits
the user to configure a solution that will meet the
sequencing requirements of FPGAs, DSPs, and
other applications with specific start-up requirements.
A precision reference and error amplifier deliver 1%
accuracy over load, line, temperature, and process.
Each LDO is stable with low-cost ceramic output
capacitors and the device is fully specified from
–40°C to +125°C. The TPS74401 is offered in a
small (5mm × 5mm) QFN package, yielding a highly
compact total solution size. For applications that
require additional power dissipation, the DDPAK
(KTW) package is also available.
CSS = 0mF
CSS = 0.001mF
VIN
IN
CIN
1mF
BIAS TPS74401
R1
GND
CSS
VOUT
OUT
SS
CBIAS
1mF
CSS = 0.0047mF
500mV/div
R3
EN
VBIAS
VPG
PG
VOUT
FB
COUT
1.1V
R2
1V/div
VEN
0V
Optional
Figure 1. Typical Application Circuit
Time (1ms/div)
Figure 2. Turn-On Response
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
TPS74401
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SBVS066D – DECEMBER 2005 – REVISED AUGUST 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION (1)
VOUT (2)
PRODUCT
TPS744xxyyyz
(1)
(2)
(3)
XX is nominal output voltage (for example, 12 = 1.2V, 15 = 1.5V, 01 = Adjustable). (3)
YYY is package designator.
Z is package quantity.
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Output voltages from 0.9V to 1.5V in 50mV increments and 1.5V to 3.6V in 100mV increments are available through the use of
innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability.
For fixed 0.8V operation, tie FB to OUT.
ABSOLUTE MAXIMUM RATINGS (1)
At TJ = –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND.
TPS74401
UNIT
VIN, VBIAS input voltage range
–0.3 to +6
V
VEN enable voltage range
–0.3 to +6
V
VPG power-good voltage range
–0.3 to +6
V
VSS SS pin voltage range
–0.3 to +6
V
VFB feedback pin voltage range
–0.3 to +6
V
–0.3 to VIN + 0.3
V
VOUT output voltage range
IOUT maximum output current
Internally limited
Output short circuit duration
Indefinite
PDISS continuous total power dissipation
See Dissipation Ratings Table
TJ operating junction temperature range
–40 to +125
°C
TSTG storage junction temperature range
–55 to +150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
DISSIPATION RATINGS
(1)
(2)
2
PACKAGE
θJA
θJC
TA < +25°C
POWER RATING
DERATING FACTOR
ABOVE TA = +25°C
RGW (QFN) (1)
36.5°C/W
4.05°C/W
2.74W
27.4mW/°C
KTW (DDPAK) (2)
18.8°C/W
2.32°C/W
5.32W
53.2mW/°C
See Figure 32 for PCB layout description.
See Figure 35 for PCB layout description.
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SBVS066D – DECEMBER 2005 – REVISED AUGUST 2006
ELECTRICAL CHARACTERISTICS
At VEN = 1.1V, VIN = VOUT + 0.3V, CIN = CBIAS = 0.1µF, COUT = 10µF, IOUT = 50mA, VBIAS = 5.0V, and TJ = –40°C to +125°C,
unless otherwise noted. Typical values are at TJ = +25°C.
TPS74401
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VOUT + VDO
5.5
V
2.375
5.25
V
0.804
V
VIN
Input voltage range
VBIAS
Bias pin voltage range
VREF
Internal reference (Adj.)
TJ = +25°C
0.796
Output voltage range
VIN = 5V, IOUT = 1.5A, VBIAS = 5V
VREF
Accuracy (1)
2.97V ≤ VBIAS ≤ 5.25V, 50mA ≤ IOUT ≤ 3.0A
VOUT
VOUT/VIN
VOUT/IOUT
VDO
Line regulation
–1
TYP
0.8
3.6
V
±0.2
+1
%
VOUT
(NOM)
+ 0.3 ≤ VIN ≤ 5.5V, QFN
0.0005
0.05
VOUT
(NOM)
+ 0.3 ≤ VIN ≤ 5.5V, DDPAK
0.0005
0.06
0mA ≤ IOUT ≤ 50mA
0.013
50mA ≤ IOUT ≤ 3.0A
0.03
IOUT = 3.0A, VBIAS – VOUT (NOM) ≥ 1.62V, QFN
115
195
VIN dropout voltage (2)
IOUT = 3.0A, VBIAS – VOUT (NOM) ≥ 1.62V,
DDPAK
120
240
VBIAS dropout voltage (2)
IOUT = 3.0A, VIN = VBIAS
Load regulation
%/V
%/mA
%/A
1.62
VOUT = 80% × VOUT (NOM), QFN
3.8
6.0
VOUT = 80% × VOUT (NOM), DDPAK
3.5
6.0
mV
V
ICL
Current limit
IBIAS
Bias pin current
IOUT = 0mA to 3.0A
2
4
mA
ISHDN
Shutdown supply current
(VIN)
VEN ≤ 0.4V
1
100
µA
IFB
Feedback pin current (3)
IOUT = 50mA to 3.0A
95
250
nA
Power-supply rejection
(VIN to VOUT)
PSRR
Power-supply rejection
(VBIAS to VOUT)
–250
1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V
73
800kHz, IOUT = 1.5A, VIN = 1.8V,
VOUT = 1.5V
42
1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V
62
800kHz, IOUT = 1.5A, VIN = 1.8V,
VOUT = 1.5V
50
Noise
Output noise voltage
100Hz to 100kHz, IOUT = 1.5A,
CSS = 0.001µF
VTRAN
%VOUT droop during load
transient
IOUT = 100mA to 3.0A at 1A/µs, COUT = 0µF
tSTR
Minimum startup time
IOUT = 1.5A, CSS = open
ISS
Soft-start charging current
VSS = 0.4V
VEN, HI
Enable input high level
VEN, LO
Enable input low level
VEN, HYS
Enable pin hysteresis
50
VEN, DG
Enable pin deglitch time
20
IEN
Enable pin current
VEN = 5V
VIT
PG trip threshold
VOUT decreasing
VHYS
PG trip hysteresis
VPG, LO
PG output low voltage
IPG = 1mA (sinking), VOUT < VIT
IPG, LKG
PG leakage current
VPG = 5.25V, VOUT > VIT
TJ
Operating junction
temperature
TSD
Thermal shutdown
temperature
(1)
(2)
(3)
A
dB
dB
16 × VOUT
µVRMS
4
%VOUT
µs
100
1
µA
1.1
5.5
V
0
0.4
V
0.5
86.5
0.73
mV
µs
0.1
1
µA
90
93.5
%VOUT
3
0.03
–40
Shutdown, temperature increasing
+155
Reset, temperature decreasing
+140
%VOUT
0.3
V
1
µA
+125
°C
°C
Adjustable devices tested at 0.8V; external resistor tolerance is not taken into account.
Dropout is defined as the voltage from the input to VOUT when VOUT is 2% below nominal.
IFB current flow is out of the device.
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SBVS066D – DECEMBER 2005 – REVISED AUGUST 2006
BLOCK DIAGRAM
IN
Current
Limit
BIAS
UVLO
OUT
VOUT
Thermal
Limit
0.73mA
R1
SS
CSS
Soft-Start
Discharge
VOUT = 0.8 x (1 +
0.8V
Reference
FB
PG
Hysteresis
and De-Glitch
EN
R2
0.9V ´ VREF
GND
Table 1. Standard 1% Resistor Values for Programming the Output Voltage (1)
(1)
R1 (kΩ)
R2 (kΩ)
VOUT (V)
Short
Open
0.8
0.619
4.99
0.9
1.13
4.53
1.0
1.37
4.42
1.05
1.87
4.99
1.1
2.49
4.99
1.2
4.12
4.75
1.5
3.57
2.87
1.8
3.57
1.69
2.5
3.57
1.15
3.3
VOUT = 0.8 × (1 + R1/R2)
Table 2. Standard Capacitor Values for Programming the Soft-Start Time (1)
(1)
4
CSS
SOFT-START TIME
Open
0.1ms
470pF
0.5ms
1000pF
1ms
4700pF
5ms
0.01µF
10ms
0.015µF
16ms
tSS(s) = 0.8 × CSS(F)/7.3 ×
10–7
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R1
)
R2
TPS74401
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SBVS066D – DECEMBER 2005 – REVISED AUGUST 2006
7-Lead
DDPAK (KTW)
Surface-Mount
IN
NC
NC
NC
OUT
5
4
3
2
1
5 ´ 5 QFN (RGW)
Package ¾ Top View
IN
6
20
OUT
IN
7
19
OUT
IN
8
18
OUT
PG
9
17
NC
BIAS
10
16
FB
11
12
13
14
15
EN
GND
NC
NC
SS
TPS74401
GND
1 2 3 4 5 6 7
SS
OUT IN EN
FB GND BIAS
PIN DESCRIPTIONS
NAME
KTW (DDPAK)
RGW (QFN)
IN
5
5–8
DESCRIPTION
Unregulated input to the device.
EN
7
11
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts
the regulator into shutdown mode. This pin must not be left floating.
SS
1
15
Soft-Start pin. A capacitor connected on this pin to ground sets the start-up
time. If this pin is left floating, the regulator output soft-start ramp time is
typically 100µs.
BIAS
6
10
Bias input voltage for error amplifier, reference, and internal control circuits.
PG
N/A
9
Power-Good (PG) is an open-drain, active-high output that indicates the status
of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a
high-impedance state. When VOUT is below this threshold the pin is driven to a
low-impedance state. A pull-up resistor from 10kΩ to 1MΩ should be
connected from this pin to a supply up to 5.5V. The supply can be higher than
the input voltage. Alternatively, the PG pin can be left floating if output
monitoring is not necessary.
FB
2
16
This pin is the feedback connection to the center tap of an external resistor
divider network that sets the output voltage. This pin must not be left floating.
OUT
3
1, 18–20
NC
N/A
2–4, 13, 14, 17
GND
4
12
PAD/TAB
Regulated output voltage. No capacitor is required on this pin for stability.
No connection. This pin can be left floating or connected to GND to allow better
thermal contact to the top-side plane.
Ground
Should be soldered to the ground plane for increased thermal performance.
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SBVS066D – DECEMBER 2005 – REVISED AUGUST 2006
TYPICAL CHARACTERISTICS
At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, CIN = 1µF, CBIAS = 1µF, CSS = 0.01µF, and COUT = 10µF,
unless otherwise noted.
LOAD REGULATION
1.0
LOAD REGULATION
0.050
Referred to IOUT = 50mA
0.9
Referred to IOUT = 50mA
0.025
0.7
0.6
-40°C
0.5
0.4
+25°C
0.3
0
Change in VOUT (%)
Change in VOUT (%)
0.8
0.2
-0.025
+25°C
-0.050
-40°C
-0.075
+125°C
-0.100
0.1
+125°C
0
-0.125
-0.150
-0.1
0
10
20
30
40
50
50
500
1000
1500
2000
2500
IOUT (mA)
IOUT (mA)
Figure 3.
Figure 4.
LINE REGULATION
VIN DROPOUT VOLTAGE vs
IOUT AND TEMPERATURE (TJ)
0.05
3000
200
0.04
0.02
Dropout Voltage (mV)
Change in VOUT (%)
0.03
TJ = -40°C
0.01
0
-0.01
TJ = +25°C
TJ = +125°C
-0.02
150
+125°C
100
50
-0.03
-40°C
-0.04
0
-0.05
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
500
1000
VIN - VOUT (V)
2000
2500
Figure 6.
VIN DROPOUT VOLTAGE vs
VBIAS – VOUT AND TEMPERATURE (TJ)
VIN DROPOUT VOLTAGE vs
VBIAS – VOUT AND TEMPERATURE (TJ)
200
IOUT = 3.0A
IOUT = 1.5A
180
160
Dropout Voltage (mV)
+125°C
200
+25°C
150
3000
IOUT (mA)
250
Dropout Voltage (mV)
1500
Figure 5.
300
100
140
120
+125°C
100
+25°C
80
60
40
50
-40°C
-40°C
20
0
0
0.9
6
+25°C
1.4
1.9
2.4
2.9
3.4
3.9
0.9
1.4
1.9
2.4
2.9
VBIAS - VOUT (V)
VBIAS - VOUT (V)
Figure 7.
Figure 8.
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3.4
3.9
TPS74401
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SBVS066D – DECEMBER 2005 – REVISED AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, CIN = 1µF, CBIAS = 1µF, CSS = 0.01µF, and COUT = 10µF,
unless otherwise noted.
VBIAS DROPOUT VOLTAGE vs
IOUT AND TEMPERATURE (TJ)
1400
+125°C
Power-Supply Rejection Ratio (dB)
VIN = VBIAS
1300
Dropout Voltage (mV)
VBIAS PSRR vs FREQUENCY
80
+25°C
1200
1100
1000
-40°C
900
800
700
600
IOUT = 3.0A
70
60
50
40
30
20
10
0
500
0
500
1000
1500
2000
2500
3000
10
100
1k
IOUT (mA)
10k
Figure 9.
COUT = 100mF C
OUT = 10mF
70
60
50
40
30
20
COUT = 0mF
10
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
VIN = 1.8, VOUT = 1.5V, IOUT = 100mA
80
VIN = 1.8, VOUT = 1.5V, IOUT = 1.5A
90
80
70
COUT = 100mF
60
COUT = 10mF
50
40
30
20
10
COUT = 0mF
0
0
10
100
1k
10k
100k
1M
10
10M
100
Figure 11.
Figure 12.
COUT = 100mF
COUT = 10mF
40
30
20
10
COUT = 0mF
0
100
1k
10k
100k
10M
1kHz
80
70
700kHz
60
50
40
300kHz
30
1M
10M
100kHz
20
COUT = 22mF
IOUT = 1.5A
10
0
10
1M
90
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
70
50
100k
VIN PSRR vs VIN – VOUT
80
60
10k
Frequency (Hz)
VIN = 1.8, VOUT = 1.5V, IOUT = 3A
90
1k
Frequency (Hz)
VIN PSRR vs FREQUENCY
100
10M
VIN PSRR vs FREQUENCY
100
90
1M
Figure 10.
VIN PSRR vs FREQUENCY
100
100k
Frequency (Hz)
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50
Frequency (Hz)
VIN - VOUT (V)
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, CIN = 1µF, CBIAS = 1µF, CSS = 0.01µF, and COUT = 10µF,
unless otherwise noted.
Output Spectral Noise Density (mV/ÖHz)
SPECTRAL NOISE DENSITY
1
LOAD TRANSIENT RESPONSE
IOUT = 3A
VOUT = 1.1V
50mV/div
50mV/div
CSS = 1nF
50mV/div
CSS = 0nF
COUT = 2 x 470mF (OSCON)
COUT = 100mF Cer.
COUT = 10mF Cer.
0.1
50mV/div
COUT = 0mF
CSS = 10nF
3.0A
1A/ms
2A/div
100mA
0.01
100
1k
10k
Time (50ms/div)
100k
Frequency (Hz)
Figure 15.
Figure 16.
VBIAS LINE TRANSIENT (3A)
10mV/div
10mV/div
10mV/div
10mV/div
VIN LINE TRANSIENT (3A)
COUT = 2 x 470mF
COUT = 2 x 470mF (OSCON)
COUT = 100mF (Cer.)
10mV/div
COUT = 10mF (Cer.)
10mV/div
COUT = 100mF (Cer.)
COUT = 10mF (Cer.)
COUT = 0mF
10mV/div
COUT = 0mF
2.5V
4.3V
1V/ms
1V/ms
500mV/div
500mV/div
3.3V
1.5V
Time (50ms/div)
Time (50ms/div)
Figure 17.
Figure 18.
TURN-ON RESPONSE
POWER-UP/POWER-DOWN
CSS = 0mF
CSS = 0.001mF
VOUT
VIN = VBIAS = VEN
CSS = 0.0047mF
1V/div
500mV/div
1.1V
1V/div
VPG (500mV/div)
VEN
VOUT
0V
Time (1ms/div)
Time (20ms/div)
Figure 19.
8
VOUT = 1.2V
(OSCON)
10mV/div
Figure 20.
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SBVS066D – DECEMBER 2005 – REVISED AUGUST 2006
TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VOUT = 1.5V, VIN = VOUT(TYP) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, CIN = 1µF, CBIAS = 1µF, CSS = 0.01µF, and COUT = 10µF,
unless otherwise noted.
IBIAS vs IOUT AND TEMPERATURE
IBIAS vs VBIAS AND VOUT
2.85
3.0
+125°C
2.8
TJ = +125°C
2.6
2.45
Bias Current (mA)
Bias Current (mA)
2.65
2.25
2.05
+25°C
1.85
1.65
-40°C
2.4
2.2
2.0
TJ = +25°C
1.8
1.6
TJ = -40°C
1.4
1.45
1.2
1.25
1.0
0
500
1000
1500
2000
2500
3000
2.0
2.5
3.0
3.5
4.0
4.5
IOUT (mA)
VBIAS (V)
Figure 21.
Figure 22.
IBIAS SHUTDOWN vs TEMPERATURE
SOFT-START CHARGING CURRENT (ISS)
vs TEMPERATURE
0.45
5.0
765
0.40
VBIAS = 2.375V
750
735
0.30
VBIAS = 5.5V
0.25
ISS (nA)
Bias Current (mA)
0.35
0.20
720
705
0.15
0.10
690
0.05
675
0
-40
0
-20
20
40
60
80
100
120
-40
-20
0
20
40
60
100
Figure 24.
LOW-LEVEL PG VOLTAGE vs PG CURRENT
OUTPUT SHORT-CIRCUIT RECOVERY
1.0
VOL Low-Level PG Voltage (V)
80
Figure 23.
120
VOUT = 0.8V
0.9
0.8
0.7
0.6
IOUT
1A/div
0.5
VOUT
50mV/div
Output Shorted
0.4
0.3
0.2
0.1
Output Open
0
0
2
4
6
8
10
12
Time (20ms/div)
PG Current (mA)
Figure 25.
Figure 26.
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APPLICATION INFORMATION
The TPS74401 belongs to a family of new
generation ultra-low dropout regulators that feature
soft-start and tracking capabilities. These regulators
use a low current bias input to power all internal
control circuitry, allowing the NMOS pass transistor
to regulate very low input and output voltages.
The use of an NMOS-pass FET offers several critical
advantages for many applications. Unlike a PMOS
topology device, the output capacitor has little effect
on loop stability. This architecture allows the
TPS74401 to be stable with any or even no output
capacitor. Transient response is also superior to
PMOS topologies, particularly for low VIN
applications.
The
TPS74401
features
a
programmable,
voltage-controlled soft-start circuit that provides a
smooth, monotonic start-up and limits startup inrush
currents that may be caused by large capacitive
loads. A power-good (PG) output is available to allow
supply monitoring and sequencing of other supplies.
An enable (EN) pin with hysteresis and deglitch
allows slow-ramping signals to be used for
sequencing the device. The low VIN and VOUT
capability allows for inexpensive, easy-to-design, and
efficient linear regulation between the multiple supply
voltages often present in processor intensive
systems.
Figure 27 illustrates a typical application circuit for
the TPS74401 adjustable input device.
R1 and R2 can be calculated for any output voltage
using the formula shown in Figure 27. Refer to
Table 1 for sample resistor values of common output
voltages. In order to achieve the maximum accuracy
specifications, R2 should be ≤ 4.99kΩ.
VIN
IN
CIN
1m F
R3
BIAS TPS74401
VBIAS
VOUT
OUT
R1
SS
CBIAS
1m F
VPG
PG
EN
FB
GND
CSS
COUT
Optional
R2
VOUT = 0.8 ´
(
1+
R1
R2
INPUT, OUTPUT, AND BIAS CAPACITOR
REQUIREMENTS
The device does not require any output capacitor for
stability. If an output capacitor is needed, the device
is designed to be stable for all available types and
values of output capacitance. The device is also
stable with multiple capacitors in parallel, of any type
or value.
The capacitance required on the IN and BIAS pins
strongly depends on the input supply source
impedance. To counteract any inductance in the
input, the minimum recommended capacitor for VIN
and VBIAS is 1µF. If VIN and VBIAS are connected to
the same supply, the recommended minimum
capacitor for VBIAS is 4.7µF. Good quality, low ESR
capacitors should be used on the input; ceramic X5R
and X7R capacitors are preferred. These capacitors
should be placed as close the pins as possible for
optimum performance.
TRANSIENT RESPONSE
The TPS74401 was designed to have transient
response within 5% for most applications without any
output capacitor. In some cases, the transient
response may be limited by the transient response of
the input supply. This limitation is especially true in
applications where the difference between the input
and output is less than 300mV. In this case, adding
additional input capacitance improves the transient
response much more than just adding additional
output capacitance. With a solid input supply, adding
additional output capacitance reduces undershoot
and overshoot during a transient at the expense of a
slightly longer VOUT recovery time. Refer to Figure 16
in the Typical Characteristics section. Since the
TPS74401 is stable without an output capacitor,
many applications may allow for little or no
capacitance at the LDO output. For these
applications, local bypass capacitance for the device
under power may be sufficient to meet the transient
requirements of the application. This design reduces
the total solution cost by avoiding the need to use
expensive high-value capacitors at the LDO output.
)
Figure 27. Typical Application Circuit for the
TPS74401 (Adjustable)
10
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DROPOUT VOLTAGE
VIN
The TPS74401 offers industry-leading dropout
performance, making it well-suited for high-current
low VIN/low VOUT applications. The extremely low
dropout of the TPS74401 allows the device to be
used in place of a DC/DC converter and still achieve
good efficiencies. This efficiency allows users to
rethink the power architecture for their applications to
achieve the smallest, simplest, and lowest cost
solution.
There are two different specifications for dropout
voltage with the TPS74401. The first specification
(see Figure 28) is referred to as VIN Dropout and is
for users that wish to apply an external bias voltage
to achieve low dropout. This specification assumes
that VBIAS is at least 1.62V above VOUT, which is the
case for VBIAS when powered by a 3.3V rail with 5%
tolerance and with VOUT = 1.5V. If VBIAS is higher
than 3.3V × 0.95 or VOUT is less than 1.5V, VIN
dropout is less than specified.
BIAS
Reference
IN
VBIAS = 5V ± 5%
VIN = 1.8V
VOUT = 1.5V
IOUT = 1.5A
Efficiency = 83%
OUT
VOUT
FB
Simplified Block Diagram
Figure 28. Typical Application of the TPS74401
Using an Auxiliary Bias Rail
The second specification (see Figure 29) is referred
to as VBIAS Dropout and is for users that wish to tie
IN and BIAS together. This option allows the device
to be used in applications where an auxiliary bias
voltage is not available or low dropout is not
required. Dropout is limited by BIAS in these
applications because VBIAS provides the gate drive to
the pass FET and therefore must be 1.4V above
VOUT.
BIAS
Reference
IN
VBIAS = 3.3V ± 5%
VIN = 3.3V ± 5%
VOUT = 1.5V
IOUT = 1.5A
Efficiency = 45%
OUT
VOUT
FB
Simplified Block Diagram
Figure 29. Typical Application of the TPS74401
Without an Auxiliary Bias
PROGRAMMABLE SOFT-START
The TPS74401 features a programmable, monotonic,
voltage-controlled soft-start that is set with an
external capacitor (CSS). This feature is important for
many applications because it eliminates power-up
initialization problems when powering FPGAs, DSPs,
or other processors. The controlled voltage ramp of
the output also reduces peak inrush current during
start-up, minimizing start-up transients to the input
power bus.
To achieve a linear and monotonic soft-start, the
TPS74401 error amplifier tracks the voltage ramp of
the external soft-start capacitor until the voltage
exceeds the internal reference. The soft-start ramp
time depends on the soft-start charging current (ISS),
the soft-start capacitance (CSS), and the internal
reference voltage (VREF), and can be calculated
using Equation 1:
ǒVREF CSSǓ
t SS +
I SS
(1)
If large output capacitors are used, the device
current limit (ICL) and the output capacitor may set
the start-up time. In this case, the start-up time is
given by Equation 2:
t SSCL +
ǒVOUT(NOM)
I CL(MIN)
COUTǓ
(2)
VOUT(NOM) is the nominal set output voltage as set by
the user, COUT is the output capacitance, and ICL(MIN)
is the minimum current limit for the device. In
applications where monotonic startup is required, the
soft-start time given by Equation 1 should be set to
be greater than Equation 2.
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The maximum recommended soft-start capacitor is
0.015µF. Larger soft-start capacitors can be used
and will not damage the device; however, the
soft-start capacitor discharge circuit may not be able
to fully discharge the soft-start capacitor when
re-enabled. Soft-start capacitors larger than 0.015µF
could be a problem in applications where the user
needs to rapidly pulse the enable pin and still
requires the device to soft-start from ground. CSS
must be low-leakage; X7R, X5R, or C0G dielectric
materials are preferred. Refer to Table 2 for
suggested soft-start capacitor values.
SEQUENCING REQUIREMENTS
IN
VOUT
OUT
CIN
1 mF
R1
BIAS TPS74401
FB
R2
R
VBIAS
CBIAS
1 mF
EN
C
GND
SS
CSS
Figure 30. Soft-Start Delay Using an RC Circuit
on Enable
If a signal is not available to enable the device after
IN and BIAS, simply connecting EN to IN is
acceptable for most applications as long as VIN is
greater than 1.1V and the ramp rate of VIN and VBIAS
is faster the set soft-start ramp rate. If the ramp rate
of the input sources is slower than the set soft-start
time, the output will track the slower supply minus
the dropout voltage until it reaches the set output
voltage. If EN is connected to BIAS, the device will
soft-start as programmed provided that VIN is present
before VBIAS. If VBIAS and VEN are present before VIN
is applied and the set soft-start time has expired then
VOUT will track VIN.
OUTPUT NOISE
The TPS74401 provides low output noise when a
soft-start capacitor is used. When the device reaches
the end of the soft-start cycle, the soft-start capacitor
serves as a filter for the internal reference. By using
a 0.001µF soft-start capacitor, the output noise is
12
ǒmVV Ǔ
V NǒmVRMSǓ + 16
RMS
V OUT(V)
(3)
The low output noise of the TPS74401 makes it a
good choice for powering transceivers, PLLs, or
other noise-sensitive circuitry.
ENABLE/SHUTDOWN
The device can have VIN, VBIAS, and VEN sequenced
in any order without causing damage to the device.
However, for the soft-start function to work as
intended, certain sequencing rules must be applied.
Enabling the device after VIN and VBIAS are present is
preferred, and can be accomplished using a digital
output from a processor or supply supervisor. An
analog signal from an external RC circuit, as shown
in Figure 30, can also be used as long as the delay
time is long enough for VIN and VBIAS to be present.
VIN
reduced by half and is typically 19µVRMS for a 1.2V
output (100Hz to 100kHz). Because most of the
output noise is generated by the internal reference,
the noise is a function of the set output voltage. The
RMS noise with a 0.001µF soft-start capacitor is
given in Equation 3.
The enable (EN) pin is active high and is compatible
with standard digital signaling levels. VEN below 0.4V
turns the regulator off, while VEN above 1.1V turns
the regulator on. Unlike many regulators, the enable
circuitry has hysteresis and deglitching for use with
relatively slow-ramping analog signals. This
configuration allows the TPS74401 to be enabled by
connecting the output of another supply to the EN
pin. The enable circuitry typically has 50mV of
hysteresis and a deglitch circuit to help avoid on-off
cycling because of small glitches in the VEN signal.
The enable threshold is typically 0.8V and varies with
temperature and process variations. Temperature
variation is approximately –1mV/°C; therefore,
process variation accounts for most of the variation
in the enable threshold. If precise turn-on timing is
required, a fast rise-time signal should be used to
enable the TPS74401.
If not used, EN can be connected to either IN or
BIAS. If EN is connected to IN, it should be
connected as close as possible to the largest
capacitance on the input to prevent voltage droops
on that line from triggering the enable circuit.
POWER-GOOD (QFN Package Only)
The power-good (PG) pin is an open-drain output
and can be connected to any 5.5V or lower rail
through an external pull-up resistor. This pin requires
at least 1.1V on VBIAS in order to have a valid output.
The PG output is high-impedance when VOUT is
greater than VIT + VHYS. If VOUT drops below VIT or if
VBIAS drops below 1.9V, the open-drain output turns
on and pulls the PG output low. The PG pin also
asserts when the device is disabled. The pull-up
resistor for PG should be in the range of 10kΩ to
1MΩ. PG is only provided on the QFN package. If
output voltage monitoring is not needed, the PG pin
can be left floating.
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INTERNAL CURRENT LIMIT
The TPS74401 features a factory-trimmed, accurate
current limit that is flat over temperature and supply
voltage. The current limit allows the device to supply
surges of up to 3.5A and maintain regulation. The
current limit responds in about 10µs to reduce the
current during a short-circuit fault. Recovery from a
short-circuit condition is well-controlled and results in
very little output overshoot when the load is
removed. See Figure 26 in the Typical
Characteristics section for short-circuit recovery
performance.
The internal current limit protection circuitry of the
TPS74401 is designed to protect against overload
conditions. It is not intended to allow operation above
the rated current of the device. Continuously running
the TPS74401 above the rated current degrades
device reliability.
THERMAL PROTECTION
Thermal protection disables the output when the
junction temperature rises to approximately +155°C,
allowing the device to cool. When the junction
temperature cools to approximately +140°C, the
output circuitry is enabled. Depending on power
dissipation, thermal resistance, and ambient
temperature the thermal protection circuit may cycle
on and off. This cycling limits the dissipation of the
regulator, protecting it from damage as a result of
overheating.
LAYOUT RECOMMENDATIONS AND POWER
DISSIPATION
An optimal layout can greatly improve transient
performance, PSRR, and noise. To minimize the
voltage droop on the input of the device during load
transients, the capacitance on IN and BIAS should
be connected as close as possible to the device.
This capacitance also minimizes the effects of
parasitic inductance and resistance of the input
source and can therefore improve stability. To
achieve optimal transient performance and accuracy,
the top side of R1 in Figure 27 should be connected
as close as possible to the load. If BIAS is connected
to IN, it is recommended to connect BIAS as close to
the sense point of the input supply as possible. This
connection minimizes the voltage droop on BIAS
during transient conditions and can improve the
turn-on response.
Knowing the device power dissipation and proper
sizing of the thermal plane that is connected to the
tab or pad is critical to avoiding thermal shutdown
and ensuring reliable operation. Power dissipation of
the device depends on input voltage and load
conditions, and can be calculated using Equation 4:
P D + ǒVIN * VOUTǓ I OUT
(4)
Power dissipation can be minimized and greater
efficiency can be achieved by using the lowest
possible input voltage necessary to achieve the
required output voltage regulation.
Activation of the thermal protection circuit indicates
excessive
power
dissipation
or
inadequate
heatsinking. For reliable operation, junction
temperature should be limited to +125°C maximum.
To estimate the margin of safety in a complete
design (including heatsink), increase the ambient
temperature until thermal protection is triggered; use
worst-case loads and signal conditions. For good
reliability, thermal protection should trigger at least
+30°C above the maximum expected ambient
condition of the application. This condition produces
a worst-case junction temperature of +125°C at the
highest expected ambient temperature and
worst-case load.
On both the QFN (RGW) and DDPAK (KTW)
packages, the primary conduction path for heat is
through the exposed pad or tab to the printed circuit
board (PCB). The pad or tab can be connected to
ground or be left floating; however, it should be
attached to an appropriate amount of copper PCB
area to ensure the device does not overheat. The
maximum junction-to-ambient thermal resistance
depends on the maximum ambient temperature,
maximum device junction temperature, and power
dissipation of the device, and can be calculated
using Equation 5:
ǒ)125°C * T AǓ
R qJA +
PD
(5)
The internal protection circuitry of the TPS74401 is
designed to protect against overload conditions. It is
not intended to replace proper heatsinking.
Continuously running the TPS74401 into thermal
shutdown degrades device reliability.
Knowing the maximum RθJA and system air flow, the
minimum amount of PCB copper area needed for
appropriate heatsinking can be calculated using
Figure 31 through Figure 35.
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TPS74401
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SBVS066D – DECEMBER 2005 – REVISED AUGUST 2006
PCB Top View
PCB Cross Section
TJ
RqJC
TC
RqCS
0.062in.
TS
RqSA
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
TA
RqJA = RqJC + RqCS + RqSA
55
50
0 LFM
qJA (°C/W)
45
40
150 LFM
35
250 LFM
30
25
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
2
Area (in )
Figure 31. PCB Layout and Corresponding RθJA Data, No Vias Under Thermal Pad
14
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PCB Top View
PCB Cross Section
TJ
RqJC
TC
RqCS
0.062in.
TS
RqSA
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
TA
RqJA = RqJC + RqCS + RqSA
50
45
0 LFM
qJA (°C/W)
40
150 LFM
35
30
250 LFM
25
20
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2
Area (in )
Figure 32. PCB Layout and Corresponding RθJA Data, Vias Under Thermal Pad
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TPS74401
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SBVS066D – DECEMBER 2005 – REVISED AUGUST 2006
PCB Top View
PCB Cross Section
TJ
RqJC
TC
RqCS
0.062in.
TS
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
RqSA
TA
RqJA = RqJC + RqCS + RqSA
90
80
qJA (°C/W)
70
0 LFM
60
150 LFM
50
40
250 LFM
30
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2
Area (in )
Figure 33. PCB Layout and Corresponding RθJA Data, Top Layer Only
16
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SBVS066D – DECEMBER 2005 – REVISED AUGUST 2006
PCB Top View
PCB Cross Section
TJ
RqJC
TC
RqCS
0.062in.
TS
RqSA
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
TA
RqJA = RqJC + RqCS + RqSA
35
0 LFM
qJA (°C/W)
30
25
20
15
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2
Area (in )
Figure 34. PCB Layout and Corresponding RθJA, Buried Thermal Plane
Submit Documentation Feedback
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TPS74401
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SBVS066D – DECEMBER 2005 – REVISED AUGUST 2006
PCB Top View
PCB Cross Section
TJ
RqJC
TC
RqCS
0.062in.
TS
RqSA
4-layer. 0.062” FR4
Vias are 0.012” diameter, plated
Top/Bottom layers are 2 oz. copper
Inner layers are 1 oz. copper
TA
RqJA = RqJC + RqCS + RqSA
55
50
45
qJA (°C/W)
40
35
30
0 LFM
25
20
15
10
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
2
Area (in )
Figure 35. PCB Layout and Corresponding RθJA, Top Layer Thermal Plane
18
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Oct-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS74401KTWR
PREVIEW
DDPAK
KTW
7
500
TBD
Call TI
Call TI
TPS74401KTWT
PREVIEW
DDPAK
KTW
7
50
TBD
Call TI
Call TI
TPS74401RGWR
ACTIVE
QFN
RGW
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS74401RGWRG4
ACTIVE
QFN
RGW
20
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS74401RGWT
ACTIVE
QFN
RGW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS74401RGWTG4
ACTIVE
QFN
RGW
20
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPSF015 – AUGUST 2001
KTW (R-PSFM-G7)
PLASTIC FLANGE-MOUNT
0.410 (10,41)
0.385 (9,78)
0.304 (7,72)
–A–
0.006
–B–
0.303 (7,70)
0.297 (7,54)
0.0625 (1,587) H
0.055 (1,40)
0.0585 (1,485)
0.300 (7,62)
0.064 (1,63)
0.045 (1,14)
0.252 (6,40)
0.056 (1,42)
0.187 (4,75)
0.370 (9,40)
0.179 (4,55)
0.330 (8,38)
H
0.296 (7,52)
A
0.605 (15,37)
0.595 (15,11)
0.012 (0,305)
C
0.000 (0,00)
0.019 (0,48)
0.104 (2,64)
0.096 (2,44)
H
0.017 (0,43)
0.050 (1,27)
C
C
F
0.034 (0,86)
0.022 (0,57)
0.010 (0,25) M
B
0.026 (0,66)
0.014 (0,36)
0°~3°
AM C M
0.183 (4,65)
0.170 (4,32)
4201284/A 08/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Lead width and height dimensions apply to the
plated lead.
D. Leads are not allowed above the Datum B.
E. Stand–off height is measured from lead tip
with reference to Datum B.
F. Lead width dimension does not include dambar
protrusion. Allowable dambar protrusion shall not
cause the lead width to exceed the maximum
dimension by more than 0.003”.
G. Cross–hatch indicates exposed metal surface.
H. Falls within JEDEC MO–169 with the exception
of the dimensions indicated.
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