19-2953; Rev 0; 7/03 Octal, 14-Bit Voltage-Output DAC with Parallel Interface ♦ Full 14-Bit Performance Without Adjustments ♦ Eight DACs in a Single Package ♦ Buffered Voltage Outputs ♦ Unipolar or Bipolar Voltage Swing of (VSS + 2.5V) to (VDD - 2.5V) ♦ 31µs Output Settling Time ♦ Low Power Consumption: 8mA (typ) ♦ Small 44-Pin MQFP Package ♦ Double-Buffered Digital Inputs ♦ Asynchronous Load Updates All DACs Simultaneously ♦ Asynchronous CLR Forces All DACs to DUTGND_ _ Potential Ordering Information TEMP RANGE PINPACKAGE INL (LSB) MX7841BS -40°C to +85°C 44 MQFP ±2 MX7841AS -40°C to +85°C 44 MQFP ±4 PART Pin Configuration 34 35 36 37 38 39 32 REFABREFAB+ VDD 3 31 4 30 5 29 VSS LDAC 6 7 27 A2 A1 A0 8 26 9 25 10 24 DB11 DB10 DB9 CS 11 23 DB8 28 22 21 20 19 18 16 15 MX7841 REFGH+ CLR DB13 DB12 WR VCC GND DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Functional Diagram appears at end of data sheet. 33 2 14 SONET Applications 1 13 Digital Offset/Gain Adjustment DUTGNDGH OUTH REFGH- DUTGNDAB OUTA 12 Minimum Component Count Analog Systems 40 Avionics Equipment 41 44 Arbitrary Function Generators 42 TOP VIEW Industrial Process Controls 43 OUTB OUTC DUTGNDCD OUTD REFCDEFREFCDEF+ VDD OUTE DUTGNDEF OUTF OUTG Applications Automatic Test Equipment (ATE) 17 An asynchronous CLR input sets the output of all eight DACs to the respective DUTGND input of the op amp. Note that CLR is a CMOS input, which is powered by VDD. All other logic inputs are TTL/CMOS compatible. The MX7841 is pin-for-pin compatible with AD7841. Features MQFP ________________________________________________________________ Maxim Integrated Products For pricing delivery, and ordering information please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MX7841 General Description The MX7841 contains eight 14-bit, voltage-output digital-to-analog converters (DACs). On-chip precision output amplifiers provide the voltage outputs. The device operates from ±15V supplies. Its bipolar output voltage swing ranges from (VSS + 2.5V) to (VDD - 2.5V) and is achieved with no external components. The MX7841 has three pairs of differential reference inputs; two of these pairs are connected to two DACs each, and a third pair is connected to four DACs. The references are independently controlled, providing different fullscale output voltages to the respective DACs. The MX7841 features double-buffered interface logic with a 14-bit parallel data bus. Each DAC has an input latch and a DAC latch. Data in the DAC latch sets the output voltage. The eight input latches are addressed with three address lines. Data is loaded to the input latch with a single write instruction. An asynchronous load input (LDAC) transfers data from the input latch to the DAC latch. The LDAC input controls all DACs; therefore, all DACs can be updated simultaneously by asserting LDAC. MX7841 Octal, 14-Bit Voltage-Output DAC with Parallel Interface ABSOLUTE MAXIMUM RATINGS VDD to GND ...........................................................-0.3V to +17V VSS to GND ........................................................... -17V to +0.3V VCC to GND ............................................................ -0.3V to +6V A_, DB_, WR, CS, LDAC, CLR to GND .....+0.3V to (VCC + 0.3V) REF_ _ _ _+, REF_ _ _ _-, DUTGND_ _ .................................(VSS - 0.3V) to (VDD + 0.3V) OUT_ ..........................................................................VDD to VSS Maximum Current into REF_ _ _ _ _, DUTGND_ _ ...........±10mA Maximum Current into Any Signal Pin ..............................±50mA OUT_ Short-Circuit Duration to VDD, VSS, and GND ................1s Continuous Power Dissipation (TA = +70°C) 44-Pin MQFP (derate 11.1mW/°C above +70°C).........870mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = +15V ±10%, VSS = -15V ±10%, VCC = +5V ±5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, RL = 5kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE (ANALOG SECTION) Resolution N Relative Accuracy INL Differential Nonlinearity DNL 14 Bits MX7841BS ±2 MX7841AS ±4 Guaranteed monotonic LSB ±1 LSB Zero-Scale Error ±2 ±8 LSB Full-Scale Error ±2 ±8 LSB Gain Error ±2 LSB Gain Temperature Coefficient (Note 1) 0.5 10 ppm FSR/°C DC Crosstalk (Note 1) 75 120 µV REFERENCE INPUTS Input Resistance 100 Input Current MΩ ±1 µA REF_ _ _ _+ Input Range 0 5 V REF_ _ _ _- Input Range -5 0 V (REF_ _ _ _+) - (REF_ _ _ _-) Range 2 10 V ANALOG OUTPUTS (VSS + 2.5) to (VDD - 2.5) Output Voltage Swing Resistive Load to GND 5 Capacitive Load to GND DC Output Impedance 2 V (Note 1) _______________________________________________________________________________________ kΩ 50 pF 0.5 Ω Octal, 14-Bit Voltage-Output DAC with Parallel Interface (VDD = +15V ±10%, VSS = -15V ±10%, VCC = +5V ±5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, RL = 5kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DUTGND_ _ CHARACTERISTICS Input Impedance per DAC 60 Maximum Input Current per DAC kΩ ±300 Input Range -2 µA +2 V DIGITAL INPUTS Input Voltage High VIH Input Voltage Low VIL 2.4 Input Capacitance CIN (Note 1) Input Current IIN Digital inputs = 0V or VCC V ±1 0.8 V 10 pF ±10 µA POWER SUPPLIES VDD Analog Power-Supply Range VDD 13.5 16.5 V VSS Analog Power-Supply Range VSS -16.75 -13.5 V VCC Digital Power Supply VCC 5.25 V Positive Supply Current IDD RL = ∞ 8 10 mA Negative Supply Current ISS RL = ∞ 8 10 mA Digital Supply Current ICC (Note 2) 0.5 mA 4.75 PSRR, ∆VOUT / ∆VDD VDD = +15V ±5% 90 dB PSRR, ∆VOUT / ∆VSS VSS = -15V ±5% 90 dB INTERFACE TIMING CHARACTERISTICS (VDD = +15V ±10%, VSS = -15V ±10%, VCC = +5V ±5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, Figure 2a, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CS Pulse Width Low t1 50 ns WR Pulse Width Low t2 50 ns LDAC Pulse Width Low t3 50 ns CS Low to WR Low t4 0 ns CS High to WR High t5 0 ns Data Valid to WR Setup t6 20 ns Data Valid to WR Hold t7 0 ns Address Valid to WR Setup t8 15 ns Address Valid to WR Hold t9 0 ns CLR Pulse-Activation Time t10 (Figure 2b) 300 ns _______________________________________________________________________________________ 3 MX7841 ELECTRICAL CHARACTERISTICS (continued) DYNAMIC CHARACTERISTICS (VDD = +15V ±10%, VSS = -15V ±10%, VCC = +5V ±5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, RL = 5kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS Output Settling Time MIN TYP To ±0.5 LSB of full scale Output Slew Rate MAX UNITS 31 µs 0.7 V/µs Digital Feedthrough (Note 3) 0.1 nV-s Digital Crosstalk (Note 4) 0.2 nV-s Digital-to-Analog Glitch Impulse 230 nV-s DAC-to-DAC Crosstalk 40 nV-s Channel-to-Channel Isolation 99 dB 200 nV/√Hz Output Noise Spectral Density Note 1: Note 2: Note 3: Note 4: VREF+ = VREF- = 0 Guaranteed by design. Not production tested. All digital inputs (DB_, A_, WR, CS, LDAC, and CLR) at GND or VCC potential. All digital inputs (DB_, A_, WR, CS, LDAC, and CLR) at +0.8V or +2.4V. All digital inputs (DB0 to DB13) transition from GND to VCC with WR = VCC Typical Operating Characteristics (VDD = +15V ±10%, VSS = -15V ±10%, VCC = +5V ±5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, TA = +25°C, unless otherwise noted.) 0.400 0.300 0.200 0.100 0.100 DNL (LSB) 0.200 0 -0.100 0.2 0 -0.100 -0.200 -0.200 -0.300 -0.300 -0.400 -0.400 -0.500 CODE 0.1 INL 0 -0.1 DNL -0.2 -0.3 -0.4 -0.500 0 2048 4096 6144 8192 10240 12288 14336 16384 0.3 ERROR (LSB) 0.300 0.4 MX7841 toc02 0.400 4 0.500 MX7841 toc01 0.500 INL AND DNL ERROR vs. TEMPERATURE DNL vs. CODE MX7841 toc03 INL vs. CODE INL (LSB) MX7841 Octal, 14-Bit Voltage-Output DAC with Parallel Interface 0 2048 4096 6144 8192 10240 12288 14336 16384 CODE -40 -20 0 20 40 TEMPERATURE (°C) _______________________________________________________________________________________ 60 80 Octal, 14-Bit Voltage-Output DAC with Parallel Interface ZERO-SCALE AND FULL-SCALE ERROR vs. TEMPERATURE 0.6 0.2 0 ZERO SCALE -0.2 7.0 ISS 6.5 6.0 -0.4 5.5 -0.6 24.5 24.0 23.5 23.0 22.5 22.0 21.5 21.0 20.5 -0.8 5.0 -40 -20 0 20 40 60 80 20.0 -40 -25 -10 5 20 35 50 65 80 -40 -25 -10 5 20 35 50 65 TEMPERATURE (°C) TEMPERATURE (°C) REFERENCE INPUT FREQUENCY RESPONSE SETTLING TIME vs. CAPACITIVE LOAD LARGE-SIGNAL STEP RESPONSE 90 80 SETTLING TIME (µs) -5 -10 -15 -20 -25 MX7841 toc08 MX7841 toc07 REF_ _ _ _ _ = 200mVp-p 0 100 80 MX7841 toc09 TEMPERATURE (°C) 5 LDAC 5V/div 70 60 OUT_ 5V/div 50 40 30 -30 20 -35 10 0 100k 1M 10M 10 100 1000 10,000 FREQUENCY (Hz) CAPACITIVE LOAD (pF) POSITIVE SETTLING TIME NEGATIVE SETTLING TIME LDAC 5V/div LDAC 5V/div OUT_ 1mV/div OUT_ 1mV/div 10µs/div 100,000 NOISE VOLTAGE DENSITY vs. FREQUENCY 1000 MX7841 toc12 10k MX7841 toc10 1k NOISE VOLTAGE DENSITY (nV/√Hz) -40 MX7841 toc11 AMPLITUDE (dB) 25.0 MX7841 toc06 7.5 IDD, ISS (mA) FULL SCALE 0.4 IDD DIGITAL SUPPLY CURRENT, ICC (µA) 0.8 MX7841 toc05 1.0 ERROR (LSB) 8.0 MX7841 toc04 1.2 DIGITAL SUPPLY CURRENT vs. TEMPERATURE IDD AND ISS vs. TEMPERATURE 100 10µs/div 10µs/div 10 100 1k 10k FREQUENCY (Hz) _______________________________________________________________________________________ 5 MX7841 Typical Operating Characteristics (continued) (VDD = +15V ±10%, VSS = -15V ±10%, VCC = +5V ±5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = +15V ±10%, VSS = -15V ±10%, VCC = +5V ±5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, TA = +25°C, unless otherwise noted.) MAJOR CARRY GLITCH IMPULSE (0xFFFF–0x10000) GAIN ERROR vs. VREF (VREF+ - VREF-) MAJOR CARRY GLITCH IMPULSE (0x1000–0xFFF) LDAC 5V/div 5V/div OUT 1.1 0.9 GAIN ERROR (LSB) LDAC OUT 5mV/div 5mV/div MX7841 toc15 MX7841 toc14 MX7841 toc13 0.7 0.5 0.3 0.1 -0.1 -0.3 -0.5 2µs/div 2 0 2µs/div 4 6 8 10 VREF (V) ZERO-SCALE ERROR vs. VREF (VREF+ - VREF-) 1.4 1.2 0.1 1.0 ZSE (LSB) 0.2 0 1.0 0.8 -0.1 0.6 -0.2 0.4 -0.3 0.2 -0.4 4 6 10 8 0.2 0 0 2 VREF (V) 4 6 10 8 2 0 4 VREF (V) SHORT-CIRCUIT CURRENT vs. TEMPERATURE 30 MX7841 toc19 0.5 0.4 20 SHORT CIRCUIT CURRENT (mA) 0.3 6 VREF (V) INL (MAX, MIN) vs. VREF (VREF+ - VREF-) INL (MAX, MIN) (LSB) 0.6 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 MX7841 toc20 2 0.8 0.4 0 0 10 ZERO-SCALE OUTPUT, SINKING CURRENT 0 -10 -20 FULL-SCALE OUTPUT, SOURCING CURRENT -30 -40 -0.5 0 2 4 6 VREF (V) 6 1.2 FSE (LSB) 0.3 1.4 MX7841 toc17 1.6 MX7841 toc16 0.4 FULL-SCALE ERROR vs. VREF (VREF+ - VREF-) MX7841 toc18 DNL (MAX, MIN) vs. VREF (VREF+ - VREF-) DNL (MAX, MIN) (LSB) MX7841 Octal, 14-Bit Voltage-Output DAC with Parallel Interface 8 10 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (°C) _______________________________________________________________________________________ 8 10 Octal, 14-Bit Voltage-Output DAC with Parallel Interface PIN NAME FUNCTION 1 DUTGNDAB Device Sense Ground Input for OUTA and OUTB. In normal operation, OUTA and OUTB are referenced to DUTGNDAB. When CLR is low, OUTA and OUTB are forced to the potential on DUTGNDAB. 2 OUTA 3 REFAB- Negative Reference Input for DACs A and B 4 REFAB+ Positive Reference Input for DACs A and B 5, 38 VDD Positive Analog Power Supply. Normally set to +15V. Connect both pins to the supply voltage. See the Power Supplies, Grounding, and Bypassing section for bypass requirements. 6 VSS Negative Analog Power Supply. Normally set to -15V. See the Power Supplies, Grounding, and Bypassing section for bypass requirements. 7 LDAC 8 A2 Address Bit 2 (MSB) 9 A1 Address Bit 1 10 A0 Address Bit 0 (LSB) 11 CS Chip Select. Active-low input. 12 WR Write Input. Active-low strobe for conventional memory write sequence. Input data latches are transparent when WR and CS are both low. WR latches data into the DAC input latch selected by A2, A1, A0 on the rising edge of CS. 13 VCC Digital Power Supply. Normally set to +5V. See the Power Supplies, Grounding, and Bypassing section for bypass requirements. 14 GND Ground 15–28 DB0–DB13 29 CLR 30 REFGH+ Positive Reference Input for DACs G and H 31 REFGH- Negative Reference Input for DACs G and H DAC A Buffered Output Voltage Load Input. Drive this asynchronous input low to transfer the contents of the input latches to their respective DAC latches. DAC latches are transparent when LDAC is low and latched when LDAC is high. Data Bits 0–13. Offset binary coding. Clear Input. Drive CLR low to force all DAC outputs to the voltage on their respective DUTGND _ _. Does not affect the status of internal registers. All DACs return to their previous levels when CLR goes high. _______________________________________________________________________________________ 7 MX7841 Pin Description Octal, 14-Bit Voltage-Output DAC with Parallel Interface MX7841 Pin Description (continued) 8 PIN NAME FUNCTION 32 OUTH 33 DUTGNDGH 34 OUTG DAC G Buffered Output Voltage 35 OUTF DAC F Buffered Output Voltage 36 DUTGNDEF 37 OUTE 39 REFCDEF+ Positive Reference Input for DACs C, D, E, and F 40 REFCDEF- Negative Reference Input for DACs C, D, E, and F 41 OUTD 42 DUTGNDCD 43 OUTC DAC C Buffered Output Voltage 44 OUTB DAC B Buffered Output Voltage DAC H Buffered Output Voltage Device Sense Ground Input for OUTG and OUTH. In normal operation, OUTG and OUTH are referenced to DUTGNDGH. When CLR is low, OUTG and OUTH are forced to the potential on DUTGNDGH. Device Sense Ground Input for OUTE and OUTF. In normal operation, OUTE and OUTF are referenced to DUTGNDEF. When CLR is low, OUTE and OUTF are forced to the potential on DUTGNDEF. DAC E Buffered Output Voltage DAC D Buffered Output Voltage Device Sense Ground Input for OUTC and OUTD. In normal operation, OUTC and OUTD are referenced to DUTGNDCD. When CLR is low, OUTC and OUTD are forced to the potential on DUTGNDCD. _______________________________________________________________________________________ Octal, 14-Bit Voltage-Output DAC with Parallel Interface CLR R Analog Section R OUT 2R 2R D0 2R 2R D12 D13 2R 2R DUTGND REF- The MX7841 contains eight 14-bit voltage-output DACs. These DACs are inverted R-2R ladder networks that convert 14-bit digital inputs into equivalent analog output voltages, in proportion to the applied reference voltages (Figure 1). The MX7841 has three positive reference inputs (REF_ _ _ _+) and three negative reference inputs (REF_ _ _ _-). The difference from REF_ _ _ _+ to REF_ _ _ _-, multiplied by two, sets the DAC output span. In addition to the differential reference inputs, the MX7841 has four analog-ground input pins (DUTGND_ _). When CLR is high (unasserted), the voltage on DUTGND_ _ offsets the DAC output voltage range. If CLR is asserted, the output amplifier is forced to the voltage present on DUTGND_ _. REF+ Figure 1. DAC Simplified Circuit Reference and DUTGND Inputs All of the MX7841’s reference inputs are buffered with precision amplifiers. This allows the flexibility of using resistive dividers to set the reference voltages. Because of the relatively high multiplying bandwidth of the reference input (188kHz), any signal present on the reference pin within this bandwidth is replicated on the DAC output. The DUTGND pins of the MX7841 are connected to the negative source resistor (nominally 115kΩ) of the output amplifier. The DUTGND pins are typically connected directly to analog ground. Each of these pins has an input current that varies with the DAC digital code. If the DUTGND pins are driven by external circuitry, budget ±200µA per DAC for load current. t1 CS t4 t5 t2 WR t8 t9 A0–A2 Output-Buffer Amplifiers t6 t7 DB0–DB13 t3 t3 (NOTE 3) The MX7841’s voltage outputs are internally buffered by precision gain-of-two amplifiers with a typical slew rate of 1V/µs. With a full-scale transition at its output, the typical settling time to ±1/2 LSB is 31µs. This settling time does not significantly vary with capacitive loads less than 10,000pF. Output Deglitching Circuit LDAC The MX7841’s internal connection from the DAC ladder to the output amplifier contains special deglitch circuitry. NOTES: 1. ALL INPUT RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF +5V. tr = tf = 5ns. CLR 2. MEASUREMENT REFERENCE LEVEL IS (VINH + VINL) / 2. 3. IF LDAC IS ACTIVATED WHILE WR IS LOW, THEN LDAC MUST STAY LOW FOR t3 OR LONGER AFTER WR GOES HIGH. Figure 2a. Digital Timing Diagram VOUT_ t10 t10 Figure 2b. Digital Timing Diagram _______________________________________________________________________________________ 9 MX7841 _______________Detailed Description MX7841 Octal, 14-Bit Voltage-Output DAC with Parallel Interface This glitch/deglitch circuitry is enabled on the falling edge of LDAC to remove the glitch from the R-2R DAC. This enables the MX7841 to exhibit a fraction of the glitch impulse energy of parts without the deglitching circuit. Digital Inputs and Interface Logic All digital inputs are compatible with both TTL and CMOS logic. The MX7841 interfaces with microprocessors using a data bus at least 14 bits wide. The interface is double buffered, allowing simultaneous updating of all DACs. There are two latches for each DAC (see the Functional Diagram): an input latch that receives data from the data bus, and a DAC latch that receives data from the input latch. Address lines A0, A1, and A2 select which DAC’s input latch receives data from the data bus as shown in Table 1. Both the input latches and the DAC latches are transparent when CS, WR, and LDAC are all low. Any change of DB0–DB13 during this condition appears at the output Table 1. MX7841 DAC Addressing instantly. Transfer data from the input latches to the DAC latches by asserting the asynchronous LDAC signal. Each DAC’s analog output reflects the data held in its DAC latch. All control inputs are level triggered. Table 2 is an interface truth table. Input Write Cycle Data can be latched or transferred directly to the DAC. CS and WR control the input latch, and LDAC transfers information from the input latch to the DAC latch. The input latch is transparent when CS and WR are low, and the DAC latch is transparent when LDAC is low. The address lines (A0, A1, A2) must be valid for the duration that CS and WR are low (Figure 2a) to prevent data from being inadvertently written to the wrong DAC. Data is latched within the input latch when either CS or WR is high. Loading the DACs Taking LDAC high latches data into the DAC latches. If LDAC is brought low when WR and CS are low, the DAC addressed by A0, A1, and A2 is directly controlled by the data on DB0–DB13. This allows the maximum digital update rate; however, it is sensitive to any glitches or skew in the input data stream. A2 A1 A0 FUNCTION 0 0 0 DAC A input latch 0 0 1 DAC B input latch 0 1 0 DAC C input latch 0 1 1 DAC D input latch 1 0 0 DAC E input latch 1 0 1 DAC F input latch 1 1 0 DAC G input latch Asynchronous Clear The MX7841 has an asynchronous clear pin (CLR) that, when asserted, sets all DAC outputs to the voltage present on their respective DUTGND pins. Deassert CLR to return the DAC output to its previous voltage. Note that CLR does not clear any of the internal digital registers. See Figure 2b. 1 1 1 DAC H input latch Applications Information Multiplying Operation Table 2. Interface Truth Table The MX7841 can be used for multiplying applications. Its reference accepts both DC and AC signals. Since the reference inputs are unipolar, multiplying operation is limited to two quadrants. See the graphs in the Typical Operating Characteristics for dynamic performance of the DACs and output buffers. CLR LD WR CS X X 0 0 Input register transparent X X X 1 Input register latched X X 1 X Input register latched X 0 X X DAC register transparent X 1 X X DAC register latched 0 X X X Outputs of DACs at DUTGND_ _ The MX7841 uses offset binary coding. A 14-bit two’s complement code is converted to a 14-bit offset binary code by adding 213 = 8192. X Outputs of DACs set to voltage defined by the DAC register, the references, and the corresponding DUTGND_ _ For typical operation, connect DUTGND to signal ground, VREF+ to +5V, and VREF- to -5V. Table 3 shows the relationship between digital code and output voltage. 1 1 X FUNCTION Digital Code and Analog Output Voltage Output Voltage Range X = Don’t care. 10 ______________________________________________________________________________________ Octal, 14-Bit Voltage-Output DAC with Parallel Interface INPUT CODE OUTPUT VOLTAGE (V) 11 1111 1111 1111 +9.998779 10 0000 0000 0000 0 01 0011 1011 0010 -3.845215 00 0000 0000 0001 -9.998779 00 0000 0000 0000 -10 Note: Output voltage is based on REF+ = +5V, REF- = -5V, and DUTGND = 0. The DAC digital code controls each leg of the 14-bit R-2R ladder. A code of 0x0 connects all legs of the ladder to REF-, corresponding to a DAC output voltage (VDAC) equal to REF-. A code of 0x3FFF connects all legs of the ladder to REF+, corresponding to a VDAC approximately equal to REF+. The output amplifier multiplies VDAC by 2, yielding an output voltage range of 2 ✕ REF- to 2 ✕ REF+ (Figure 1). Further manipulation of the output voltage span is accomplished by offsetting DUTGND. The output voltage of the MX7841 is described by the following equation: DATA VOUT = 2(VREF + − VREF − ) + VREF − 14 2 − VDUTGND where DATA is the numeric value of the DAC’s binary input code, and DATA ranges from 0 to 16,383 (214 - 1). The resolution of the MX7841, defined as 1 LSB, is described by the following equation: LSB = mum performance, drive LDAC low after the inputs are either latched or steady state. This is best accomplished by having the falling edge of LDAC occur at least 50ns after the rising edge of CS. Power Supplies, Grounding, and Bypassing For optimum performance, use a multilayer PC board with an unbroken analog ground. For normal operation, connect the four DUTGND pins directly to the ground plane. Avoid sharing the connections of these sensitive pins with other ground traces. As with any sensitive data-acquisition system, connect the digital and analog ground planes together at a single point, preferably directly underneath the MX7841. Avoid routing digital signals underneath the MX7841 to minimize their coupling into the IC. For normal operation, bypass VDD and VSS with 0.1µF ceramic chip capacitors to the analog ground plane. To enhance transient response and capacitive drive capability, add 10µF tantalum capacitors in parallel with the ceramic capacitors. Note, however, that the MX7841 does not require the additional capacitance for stability. Bypass VCC with a 0.1µF ceramic chip capacitor to the digital ground plane. Power-Supply Sequencing To guarantee proper operation of the MX7841, ensure that power is applied to VDD before VSS and VCC. Also ensure that V SS is never more than 300mV above ground. To prevent this situation, connect a Schottky diode between VSS and the analog ground plane, as shown in Figure 3. Do not power up the logic input pins 2(REF+ − REF− ) 214 VSS VSS VSS Reference Selection Because the MX7841 has precision buffers on its reference inputs, the requirements for interfacing to these inputs are minimal. Select a low-drift, low-noise reference within the recommended REF+ and REF- voltage ranges. The MX7841 does not require bypass capacitors on its reference inputs. Add capacitors only if the reference voltage source requires them to meet system specifications. MX7839 1N5817 GND SYSTEM GND Minimizing Output Glitch The MX7841’s internal deglitch circuitry is enabled on the falling edge of LDAC. Therefore, to achieve opti- Figure 3. Schottky Diode Between VSS and GND ______________________________________________________________________________________ 11 MX7841 Table 3. Analog Voltage vs. Digital Code MX7841 Octal, 14-Bit Voltage-Output DAC with Parallel Interface before establishing the supply voltages. If this is not possible and the digital lines can drive more than 10mA, place current-limiting resistors (e.g., 470Ω) in series with the logic pins. Chip Information TRANSISTOR COUNT: 13,225 PROCESS: BiCMOS Driving Capacitive Loads The MX7841 typically drives capacitive loads up to 0.01µF without a series output resistor. However, whenever driving high capacitive loads, it is prudent to use a 220Ω series resistor between the MX7841 output and the capacitive load. 12 ______________________________________________________________________________________ LDAC WR CS A0 A1 A2 GND VCC DB0– DB13 ADDRESS DECODE LOGIC DIGITAL POWER SUPPLY DATA REG H 14 DATA REG F 14 DATA REG G 14 DATA REG E 14 14 14 DATA REG D 14 14 14 14 14 DATA REG C 14 14 14 DATA REG B DATA R REG A 14 14 14 14 MX7841 DAC REG H DAC REG G 14 DAC H DAC G DAC F DAC E 14 DAC REG E DAC REG F DAC D DAC C DAC B DAC A 14 14 14 14 DAC REG D DAC REG C DAC REG B DAC REG A ANALOG POWER SUPPLY VDD DUTGNDGH OUTH OUTG DUTGNDEF OUTF OUTE DUTGNDCD OUTD OUTC DUTGNDAB OUTB OUTA VSS Functional Diagram REFAB- REFAB+ REFCDEF- REFCDEF+ REFGH- REFGH+ ______________________________________________________________________________________ 13 MX7841 CLR Octal, 14-Bit Voltage-Output DAC with Parallel Interface Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MQFP44.EPS MX7841 Octal, 14-Bit Voltage-Output DAC with Parallel Interface PACKAGE OUTLINE 44L MQFP, 1.60 LEAD FORM 21-0826 D 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.