MAXIM MAX2101CMQ

19-0298; Rev 4; 5/96
KIT
ATION
EVALU ABLE
AVAIL
6-Bit Quadrature Digitizer
The MAX2101 6-bit quadrature digitizer combines quadrature demodulation with analog-to-digital conversion on
a single bipolar silicon die. This unique RF-to-Bits TM
function bridges the gap between existing RF downconverters and CMOS digital signal processors (DSPs).
The MAX2101’s simple receiver subsystem is designed
for digital communications systems such as those used
in DBS, TVRO, WLAN, and other applications.
The MAX2101 accepts input signals from 400MHz to
700MHz and applies adjustable gain, providing at least
40dB of dynamic range.
Each baseband is filtered by an on-chip, 5th-order
Butterworth lowpass filter, or the user can select an
external filter path. Baseband sample rate is 60Msps.
The MAX2101 is available in a commercial temperature
range, 100-pin MQFP package.
____________________________Features
♦ ADCs Provide Greater than 5.5 Effective Bits at
fS = 60Msps, fIN = 15MHz
♦ Fully Integrated Lowpass Filters with
Externally Variable Bandwidth (10MHz to 30MHz)
♦ 40dB Dynamic Range
♦ Integrated VCO and Quadrature Generation
Network for I/Q Demodulation
♦ Divide-by-16 Prescaler for Oscillator PLL
♦ Programmable Counter for Variable Sample Rates
♦ Signal-Detection Function
♦ Selectable Offset Binary or Twos-Complement
Output Data Format
♦ Automatic Baseband Offset Cancellation
________________________Applications
Recovery of PSK and QAM Modulated RF Carriers
Direct-Broadcast Satellite (DBS) Systems
Television Receive-Only (TVRO) Systems
______________Ordering Information
PART
MAX2101CMQ
Cable Television (CATV) Systems
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
100 MQFP
Wireless Local Area Networks (WLANs)
__________________________________________________Typical Application Circuit
LOW-NOISE AMPLIFIER
X/KU BAND
H POLARIZATION
V POLARIZATION
950MHz to 2000MHz
LOCAL OSCILLATOR
600MHz
(NARROW BAND)
LOCAL OSCILLATOR
L-BAND DOWNCONVERTER
LOW-NOISE BLOCK
MATCHED
FILTERS
CLOCK
AND
CARRIER
RECOVERY
ERROR
DETECTION
AND
CORRECTION
MISCELLANEOUS
DSP
0°
QUADRATURE
GENERATION
A/D
CONVERSION
90°
DSP POST PROCESSING
DIV-16
MAX2101
612MHz PHASE LOCKED
TMRF-to-Bits
is a registered trademark of Tektronix, Inc.
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
MAX2101
_______________General Description
MAX2101
6-Bit Quadrature Digitizer
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Ranges (Note 1)
VCC ...................................................................(-0.3V to +6.5V)
VINA .....................................................................(VCCA + 0.3V)
VIND ....................................................................(VCCD + 0.3V)
Continuous Power Dissipation (TA = +70°C) .......................1.6W
Operating Temperature Range...............................0°C to +70°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, <10sec)...........................+300°C
Note 1: The digital control inputs are diode protected; however, permanent damage may occur on unconnected units under highenergy electrostatic fields. Keep unused units in conductive foam or shunt the terminals together. Discharge the conductive
foam to the destination socket before insertion.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 4.75V to 5.25V, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
DC SPECIFICATIONS (VGND = System Ground, VCCA = VCCD = 5.0V ±5%)
Digital Supply Current
ICCD
VCCA, VCCO, VCCD, VCCC
102
mA
ADC Supply Current
ICCAD
VCCAD
80
mA
RF Blocks Supply Current
ICCRF
VCCIF, VCC2, VCC1, VCCQ
170
mA
IF Port DC Dynamic Range
VIF
100
mV
Ω
IF Port Input Resistance
AGC Input Voltage
AGC Input Resistance
40
75
VAGMIN
RIF
VIF = 100mV
1.0
1.5
VAGMAX
VIF = 0.5mV
2.3
2.9
50
100
RAGC
AGC Input Capacitance
CAGC
AGC Range
AGCR
AGC Control Slope Variation
SVAGC
AGC Control Input Bias Current
0.5
IAGC
(Note 2)
2
40
±20
RILPF
Lowpass Filter Tune Input Capacitance
CILPF
TNKA, TNKB Resonant Port Bias Voltage
VLO
4.1V on complementary input
1
LO Resonant Port Input Resistance
RILO
(Note 2)
10
LO Resonant Port Input Capacitance
CILO
(Note 2)
LO Prescaler Output High (Note 3)
VOH
RL = 1MΩ, CL = 15pF
LO Prescaler Output Low
VOL
RL = 1MΩ, CL = 15pF
LO Prescaler Output Source Current
IOH
RL = 1MΩ, CL = 15pF, VO = 2.4V
400
IOL
RL = 1MΩ, CL = 15pF, VO = 0.5V
50
Baseband Input—Input Capacitance
CIBB
Baseband Amplifier I/Q Offset Match
(Note 4)
VOFFBB
LSB = 24mV, ENOPB = 0V,
VFTUNE = VFTMIN to VFTMAX
Baseband Amplifier Offset Adjust
Input Resistance
ROFFBB
Voltage Range = 1V to 4V
2
µA
10
kΩ
(Note 2)
AVBB
pF
4:1
Voltage range = 1V to 4V
Baseband Amplifier DC Gain
kΩ
dB
Variation dB/V
Lowpass Filter Tune Input Resistance
LO Prescaler Output Sink Current
V
2
3
V
kΩ
2
2.4
pF
V
0.5
27
pF
V
µA
µA
29
(Note 2)
10
_______________________________________________________________________________________
31
dB
2
pF
1.0
LSB
kΩ
6-Bit Quadrature Digitizer
(VCC = 4.75V to 5.25V, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
Power Detect Output Minimum
VPWR
VOBB = 0Vp-p
Power Detect Output Maximum
VPWR
VOBB > 2V DC
ADC LSB Size
ADC Input Offset
AVM
VOFFAD
ADC Differential Nonlinearity
ADC Integral Nonlinearity
RF Signal Path DC Gain
TYP
1.5
V
25
mV
V
21
Channel to channel
0.4
dB
LSB = 24mV, either channel
0.5
LSB
1.0
LSB
1.0
LSB
DNL
INL
AVRF
AGC set to maximum gain
Composite I/Q Gain Mismatch
∆M(IQ)
Entire signal path, DC,
VFTUNEI = VFTUNEQ = V2R5
Buffered Reference Voltage
(Zero Temperature Coefficient)
VREF
RL = 1kΩ, CL = 0.1µF
Buffered Reference Voltage
(Proportional to Absolute Temperature)
VPTAT
RL = 40kΩ,
CL = 0.01µF
VPTAT Temperature Coefficient
MAX UNITS
3.75
LSB
ADC Amplitude Response Match
MIN
63
dB
0.5
dB
1.18
1.25
V
TA = +25°C
1.0
1.3
TA = 0°C to +70°C
(Note 2)
0.9
1.5
TA = 0°C to +70°C
4.5
V
mV/°C
Buffered Reference Voltage
(2 x VREF)
V2R5
Ratio of V2R5 to VREF
1.9
Data Output High (Note 3)
VOH
RL = 1MΩ, CL = 15pF
2.2
Data Output Low
VOL
RL = 1MΩ, CL = 15pF
Data Output Source Current (Note 3)
IOH
RL = 1MΩ, CL = 15pF, VO = 2.4V
Data Output Sink Current
IOL
Data Clock Output High (Note 3)
VOH
Data Clock Output Low
VOL
RL = 1MΩ, CL = 15pF
Data Clock Output Source Current (Note 3)
IOH
RL = 1MΩ, CL = 15pF, VO = 2.4V
400
µA
Data Clock Output Sink Current
IOL
RL = 1MΩ, CL = 15pF, VO = 0.5V
50
µA
RL = 50Ω external, f = 5MHz
0
Master Clock Input Dynamic Range
PMCLK
Master Clock Input Resistance
RIMCLK
Master Clock Input Capacitance
CIMCLK
2.1
V
V
0.5
V
400
µA
RL = 1MΩ, CL = 15pF, VO = 0.5V
50
µA
RL = 1MΩ, CL = 15pF
2.2
V
0.5
10
2
VOH
RL = 10MΩ, CL = 15pF
Reference Clock Output Low
VOL
RL = 10MΩ, CL = 15pF
Reference Clock Output Source Current
(Note 3)
IOH
RL = 1MΩ, CL = 15pF, VO = 2.4V
400
RL = 1MΩ, CL = 15pF, VO = 0.5V
50
dBm
kΩ
5
Reference Clock Output High (Note 3)
V
2.2
pF
V
0.5
V
µA
Reference Clock Output Sink Current
IOL
Digital Input High Threshold (Note 5)
VIH
µA
Digital Input Low Threshold (Note 5)
VIL
Digital Input Current High (Note 5)
IIH
VIH = 2.0V
-150
-500
µA
Digital Input Current Low (Note 5)
IIL
VIL = 0.8V
-400
-790
µA
FLTRSEL Input Current High
IIH
VIH = 2.0V
µA
FLTRSEL Input Current Low
IIL
VIL = 0.8V
µA
2.0
0.8
V
V
_______________________________________________________________________________________
3
MAX2101
ELECTRICAL CHARACTERISTICS (continued)
MAX2101
6-Bit Quadrature Digitizer
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 4.75V to 5.25V, TA = +25°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
AC SPECIFICATIONS (GND = System Ground, VCC = VCCD = 5.0V ±5%)
IF Port Dynamic Range (Notes 2, 6)
IF Port VSWR (Note 6)
IF Input Frequency Range
PIF
VSWR
RS = 50Ω, fIF = 400MHz to 700MHz
-50
RS = 50Ω, RTERM = 25Ω, no matching
network, fIF = 400MHz to 700MHz
-10
dBm
700
MHz
1.7
fIF
(Note 2)
Noise Figure (Note 6)
NF
RTERM = 50Ω,
gain configured for PIF = -50dBm
20
dB
Noise Figure Variation
∆NF
Maximum gain to minimum gain
1
dB/dB
Gain configured for PIF = -10dBm,
fBB1 = 5MHz, fBB2 = 6MHz
6
Gain configured for PIF = -50dBm,
fBB1 = 5MHz, fBB2 = 6MHz
-34
Input 3rd-Order Intercept Point
IIP3
400
dBm
LO Frequency Coverage
fLO
External resonator, guaranteed
LO Device Phase Noise Floor
ΦN
10MHz off fC, 1Hz bandwidth
400
-140
700
dBc/Hz
MHz
LO Device Phase Noise
ΦN
10kHz off fC, 1Hz bandwidth
(limited by external tank Q)
-88
dBc/Hz
MIXER Output Baseband Gain Flatness
∆AV
5Hz to 20MHz
0.4
dB
Lowpass Filter Stop-Band Attenuation
ASB
f = 2 x fC
(with respect to signal level at f = 0.5 x fC)
28
dB
VFTMIN
fC = 10MHz
1.5
2.1
VFTMAX
fC = 30MHz
2.3
2.9
Composite I/Q Amplitude Balance
∆M(IQ)
fLO = 650MHz
0.3
dB
Composite I/Q Phase Balance
∆Φ(IQ)
fLO = 650MHz
1.5
degree
100Hz to 15MHz, each channel excluding
filter
0.5
ns
20
MHz
Lowpass Filter Tune Voltage
Composite Group Delay Variation
ADC 0.1dB Bandwidth
ADC Maximum Sample Rate, Each Section
∆T
BW0.1dB
SRMAX
ADC Aperture Uncertainty
tAU
ADC Transient Response
tTRAN
Baseband Overdrive Recovery
ADC Effective Number of Bits
ADC Input IP3 Rejection
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
4
Recover
(Note 2)
60
V
Msps
fS = 60Msps
80
ps
Full-scale transition, settle to within 1%
10
ns
VBASEBAND = 3Vp-p
10
ns
ENB
fIN = 15MHz, fS = 60Msps, VIN = 95% FS
5.5
Bits
IIP3AD
f1 = 10MHz, FS - 7dB; f2 = 12MHz, FS - 7dB
-38
dBc
Guaranteed by design.
A warm-up of 10 seconds is required at TA = 0°C.
Sample characterization at TA = 0°C to +70°C.
Digital inputs include Programmable Sample Rate Control (S0–S2), Binary Enable (BINEN).
RS = Source Resistance of signal source driving IF input (IFIN, pin 90).
RTERM = Termination Resistance for inverting IF input (IFINB, pin 91).
_______________________________________________________________________________________
6-Bit Quadrature Digitizer
MAX2101
TIMING CHARACTERISTICS
(VGND = system ground, VCCA = VCCD = 5.0V ±5%, TA = +25°C, unless otherwise noted.) (Note 4)
PARAMETER
SYMBOL
Data Clock Period (Figure 2)
MIN
TYP
MAX
UNITS
tPC
16
ns
Propagation Delay, Clock to Data (Figure 2)
tPCQ
4
ns
Data Output Skew (all 12 outputs) Settled within 20% (Figure 2)
tSKEW
1
ns
Aperture Delay Relative to Data Clock (Figure 2)
tAPERTURE
1
ns
Aperture Delay Match, Channel to Channel
tAP-MATCH
20
ps
Data Output Rise, Fall Time (20% to 80%) (Note 7)
tr, tf
4
ns
Data Clock Output Rise, Fall Time (20% to 80%) (Note 7)
tr, tf
3
ns
Reference (Div 6) Clock Output Rise, Fall Time (20% to 80%) (Note 7)
tr, tf
5
ns
tj
30
ps
tr, tf
3
ns
Reference Clock Output Jitter, RMS
VCO Prescaler Output Rise, Fall Time (20% to 80%) (Note 7)
Note 7: RL = 1MΩ, CL = 15pF
__________________________________________Typical Operating Characteristics
(VCC = 5V, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs.
TEMPERATURE
245
240
280
1.218
1.216
270
260
VREF (V)
250
1.220
MAX2101 TOC 02
290
SUPPLY CURRENT (mA)
255
ICC (mA)
300
MAX2101-TOC 01
260
VREF (PIN 88) VOLTAGE vs.
TEMPERATURE
MAX2101 TOC 03
SUPPLY CURRENT vs.
SUPPLY VOLTAGE
250
240
230
1.214
1.212
1.210
220
235
1.208
210
230
200
4.75
4.85
4.95
5.05
VCC (V)
5.15
5.25
1.206
0
10
20
30
40
50
TEMPERATURE (°C)
60
70
0
10
20
30
40
50
60
70
TEMPERATURE (°C)
_______________________________________________________________________________________
5
____________________________Typical Operating Characteristics (continued)
(VCC = 5V, TA = +25°C, unless otherwise noted.)
VPTAT (PIN 97) vs.
TEMPERATURE
1.3
1.213
1.212
1.18
1.16
1.14
1.2
VPTAT (V)
VPTAT (V)
1.214
1.20
MAX2101 TOC 05
1.4
MAX2101 TOC 04
1.215
VPTAT (PIN 97) VOLTAGE vs.
SUPPLY VOLTAGE
1.1
1.0
1.211
MAX2101 TOC 06
VREF (PIN 88) VOLTAGE vs.
SUPPLY VOLTAGE
VREF (V)
1.12
1.10
1.08
1.06
1.04
0.9
1.02
1.210
4.75
0.8
4.85
4.95
5.05
5.15
1.00
0
5.25
10
20
30
40
50
60
70
4.75
4.85
TEMPERATURE (°C)
VCC (V)
4.95
MAX2101 TOC 07
4.5
4.0
TA = +70°C
3.5
PWR (V)
3.0
2.5
2.0
TA = +25°C
1.5
1.0
0.5
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
BASEBAND AMPLITUDE (V)
MAX2101 TOC 10
DIFFERENTIAL LINEARITY vs.
ADC CODE
100m
50m
0
-50m
-100m
ADJ CODE DELTA ERROR (LSB) vs. CODE
DNL = 0.173 LSB
-150m
5
10
15
20
25
30
35
40
45
50
55
60
CODE
6
5.05
VCC (V)
PWR (PINS 85, 96) VOLTAGE vs.
BASEBAND AMPLITUDE
ADJ CODE DELTA ERROR (LSB)
MAX2101
6-Bit Quadrature Digitizer
_______________________________________________________________________________________
5.15
5.25
6-Bit Quadrature Digitizer
MAX2101 TOC 11
INTEGRAL NONLINEARITY vs.
ADC CODE
100m
ERROR (LSB)
50m
0
-50m
-100m
ADC ERROR (LSB) vs. CODE
INL = 0.15 LSB
-150m
5
10
15
20
25
30
35
40
45
50
55
60
CODE
RF SIGNAL PATH GAIN vs.
AGC (PIN 93) VOLTAGE
0
30
20
7
-5
-15
-30
4
fLO = 464MHz or 668MHz
fBB1 = 5.1MHz
fBB2 = 6.1MHz
P(BB1) = P(BB2) = -16dBm
P(FSIN) = -10dBm
1
0
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5
VAGC (V)
IF POWER (dBm)
5
10
15
20
25
30
35
CUTOFF FREQUENCY (MHz)
IFIN (PIN 90) VSWR vs.
FREQUENCY
NOISE FIGURE vs.
IF INPUT POWER
28
26
MAX2101-TOC 16
2.0
MAX2101-TOC 15
30
1.9
1.8
1.7
24
IFIN VSWR
NF (dB) (DSB)
5
2
@ P(FSIN) = -50dBm
-35
6
3
P(BB1) = P(BB2) = -16dBm
@ P(FSIN) = -10dBm
P(BB1) = P(BB2) = -56dBm
-25
0
8
-10
-20
10
9
IIP3 (dBm)
IIP3 (dBm)
40
GAIN (dB)
fLO = 668MHz
fBB1 = 5.1MHz
fBB2 = 6.1MHz
fC = 10MHz
5
MAX2101-TOC 14
fLO = 624MHz
fBB = 5.1MHz
MAX2101-TOC 13
50
10
MAX2101-TOC 12
60
INPUT IP3 vs.
FILTER CUTOFF FREQUENCY
INPUT IP3 vs.
IF POWER
22
20
18
1.6
1.5
1.4
1.3
16
1.2
14
fLO = 624MHz
fBB = 10MHz
12
10
-55
-50
1.1
1.0
-45
-40
IF POWER (dBm)
-35
-30
RS = 50Ω
(PIN 91) IFINB AC TERMINATED IN 25Ω
200
300
400
500
600
700
800
900
FREQUENCY (MHz)
_______________________________________________________________________________________
7
MAX2101
____________________________Typical Operating Characteristics (continued)
(VCC = 5V, TA = +25°C, unless otherwise noted.)
MAX2101
6-Bit Quadrature Digitizer
______________________________________________________________Pin Description
PIN
FUNCTION
PIN
NAME
35
D1Q
Q Channel Data Output, bit 1
36
D0Q
Q Channel Data Output, bit 0 (LSB)
39
RCLK
Reference Clock, divide by six from
master clock (MCLK)
41
DCLKB
Data Clock Complementary Output
42
DCLK
45
D0I
I Channel Data Output, bit 0 (LSB)
Q Channel Baseband Amplifier,
External Input
46
D1I
I Channel Data Output, bit 1
49
D2I
I Channel Data Output, bit 2
Q Channel Filter Cutoff
Frequency Control
50
D3I
I Channel Data Output, bit 3
53
D4I
I Channel Data Output, bit 4
Q Channel Baseband Amplifier
Offset Adjust
54
D5I
I Channel Data Output, bit 5 (MSB)
56
BINEN
57
S2
Programmable Sample Rate
Control Input, bit 2 (MSB)
58
S1
Programmable Sample Rate
Control Input, bit 1
60, 61
VCCAD
GND
2
VGNDQ
Q Channel Baseband Ground
BBINQ
3
4
5
FTUNEQ
OFFQ
Ground
6
BBOUTQ
Q Channel Baseband Amplifier
Output
7
BBOUTQB
Q Channel Baseband Amplifier
Inverted Output
Data Clock Output
Binary Enable
8
VCCQ
VGNDP
11
VCCP
Prescaler +5V Supply
62
S0
14
TNKB
Oscillator Resonator Port
64
VCCC
Clock Buffer +5V Supply
15
VCC2
Oscillator +5V Supply
65
MCLK
Master Clock
16
VGND2
Oscillator Ground
66
VGNDC
Clock Buffer Ground
17
TNKA
Oscillator Resonator Port
68
ENOPB
Offset Correction/Enable Correction
20, 21
VGNDAD
A/D Converter Ground
22, 59
VSUBAD
A/D Converter Substrate
69
CQB
23
VCOPRE
Divide-by-16 Prescaler Output
70
CQ
Noninverting Input Q Channel
Offset Correction
71
CI
Noninverting Input I Channel Offset
Correction
72
CIB
Noninverting Input I Channel Offset
Correction
73
VCCI
74
BBOUTIB
75
BBOUTI
76
OFFI
77
FTUNEI
VCOPREB
Q Channel Baseband +5V Supply
FUNCTION
10
24
8
NAME
1, 9,
12, 13,
18, 19,
63, 67,
82, 83,
89, 92,
98, 99
Prescaler Ground
Divide-by-16 Prescaler
Complementary Output
25, 29,
38, 40,
44, 52
VCCO
26
VGNDO
27
D5Q
Q Channel Data Output, bit 5 (MSB)
28
D4Q
Q Channel Data Output, bit 4
30, 37,
43, 51,
55
VGNDO
31
D3Q
Q Channel Data Output, bit 3
32
D2Q
Q Channel Data Output, bit 2
33, 48
VCCD
34, 47
VGNDD
Digital Output +5V Supply
Digital Output Ground
Digital Output Ground
Digital Logic +5V Supply
A/D Converter +5V Supply
Programmable Sample Rate
Control Input, bit 0 (LSB)
Inverting Input Q Channel Offset
Correction
I Channel Baseband +5V Supply
I Channel Baseband Amplifier
Inverted Output
I Channel Baseband Amplifier Output
I Channel Baseband Amplifier
Offset Adjust
I Channel Filter Cutoff Frequency
Control
Digital Logic Ground
_______________________________________________________________________________________
6-Bit Quadrature Digitizer
PIN
NAME
FUNCTION
78
BBINI
I Channel Baseband Amplifier,
External Input
79
VGNDI
I Channel Baseband Ground
80
VREFIN
High Impedance, connect to VREF
(pin 88)
81
MIXOUTI
I Channel Mixer Output
84
VSUBRF
RF Demodulator Substrate
85
PWRI
I Channel Power Indicator
86
2R5
87
VCCIF
IF Signal Processing +5V Supply
88
VREF
Bandgap Reference Voltage
Output
2x VREF Output
90
IFIN
91
IFINB
IF Amplifier Noninverting Input
IF Amplifier Inverting Input
93
AGC
Automatic Gain Control Input
94
VGNDIF
IF Signal-Processing Ground
95
FLTRSEL
Baseband Signal Path Select
96
PWRQ
Q Channel Power Indicator
97
VPTAT
PTAT Reference Voltage Output
100
MIXOUTQ
Q Channel Mixer Output
______________Detailed Description
The MAX2101 6-bit quadrature digitizer solves one of
the most challenging problems of high dynamic range
digital-receiver design by combining quadrature
demodulation and analog-to-digital (A/D) conversion in
a single device. The MAX2101’s unique RF-to-Bits
function bridges the gap between RF downconverters
and CMOS digital signal processors (DSPs). Figure 1
is a simplified connection diagram.
The MAX2101 accepts input signals from 400MHz to
700MHz and applies gain depending on the input
amplitude. The signal is then split and downconverted
to baseband by two mixers, which are driven by two
local oscillator (LO) signals in quadrature. An internal
voltage-controlled oscillator (VCO) feeds the two LOs.
Each baseband is filtered by an internal 5th-order
Butterworth lowpass filter. The on-board lowpass filters
have an externally variable bandwidth of 10MHz to
30MHz. Each baseband is then converted by a 6-bit
analog-to-digital converter (ADC). The conversion result
is stored in a register and is output using the data
clock. See Figure 2 for the relation between baseband
signal, sample and data clock, and digitized data. The
external master clock is internally divided by six and is
available at RCLK for external system functions, frequency synthesizers, etc. See Figures 3 and 4 for functional diagrams.
IF Input Port (IFIN, IFINB)
The MAX2101 provides a balanced IF input. The inputs
are self-biasing, so the input signals should be AC terminated, depending on system requirements. To minimize
noise, the unused input should be AC terminated with
25Ω. To minimize distortion, AC terminate the unused
input with a 50Ω resistor.
VCO Resonator Tank Ports
(TNKA, TNKB) and Prescaler
The MAX2101 integrates a negative impedance oscillator with balanced inputs. Use a parallel tank network,
as shown in Figure 5. The phase-noise performance of
the oscillator near the carrier is dominated by the resonant network. The resonant inductor must have a sufficiently high Q and a self-resonant frequency (SRF) that
is more than twice the intended LO frequency. Be sure
to minimize parasitic elements surrounding the tank
network by using proper layout techniques. See the
Applications Information section.
The VCO prescaler output provides phase-lock loop
capability for controlling the VCO frequency. The
prescaler generates the VCO frequency divided by 16.
As a result, the prescaler delivers a 25MHz to
43.75MHz signal over the VCO operating frequency
range of 400MHz to 700MHz. The differential outputs
should have equivalent termination.
_______________________________________________________________________________________
9
MAX2101
_______Pin Description (continued)
MAX2101
6-Bit Quadrature Digitizer
VCC
1k
68
ENOPB
FLTRSEL
BINEN
71 CI
VCC
0.22µF
GAIN
ADJUST
72
0.22µF
76
2k
77
0.01µF
S0
S1
CIB
S2
95
56
62
58
57
OFFI
0.1µF
MCLK
FTUNEI
65
I CHANNEL
POWER-DETECT
OUTPUT
50Ω
93
IF INPUT SIGNAL
400MHz to
700MHz
90
25Ω
0.01µF
AGC
PWRI
0.01µF
91
D5I 54
53
D4I
50
D3I
49
D2I
46
D1I
45
D0I
0.01µF
88
VREF
97
VPTAT
0.1µF
20k
4
1⁄
2
0.01µF MAX407
I CHANNEL DATA OUTPUT
FTUNEQ
50Ω
DCLK
80
50Ω
10k
IFIN
IFINB
2.2k
85
MASTER
CLOCK
INPUT
(60MHz)
DCLKB
VREFIN
42
41
DATA
CLOCK
20k
MAX2101
4k
20k
5.6k
0.01µF
5
1⁄
0.22µF
2
MAX407
D5Q
OFFQ
D4Q
69
31
32
D2Q
35
D1Q
36
D0Q
D3Q
CQB
0.1µF
VCC
20k
2k
70
FILTER
TUNE
Q CHANNEL DATA OUTPUT
CQ
PWRQ
0.22µF
RCLK
23 VCOPRE
24
27
28
TNKA
VCOPREB
TNKB
96
39
17
14
10k
PARALLEL
RESONANT
TANK
(FIGURE 5)
1000pF
PHASE-LOCKED LOOP
REFERENCE FREQUENCY
INPUT
50Ω
PHASE
DETECTOR
LOOP
FILTER
Figure 1. Typical Connection Diagram
10
______________________________________________________________________________________
0.01µF
Q CHANNEL
POWER-DETECT
OUTPUT
6-Bit Quadrature Digitizer
N
N+1
MAX2101
ANALOG
INPUT
N+2
tAPERTURE
tPC
DATA
CLOCK
tPCQ
tSKEW
DATA
OUT
DATA VALID N-1
DATA VALID N
NOTE: DATA IS VALID ON
THE RISING EDGE OF DCLK.
Figure 2. Baseband Signal, Sample/Data Clock, and Digitized Data Timing
IFIN
(PIN 90)
OFFI
(PIN 76)
AGC
(PIN 93)
CIB
(PIN 72)
MIXOUTI BBINI
(PIN 81) (PIN 78)
6dB
IFINB
(PIN 91)
CI
(PIN 71)
150k
AGC
40dB to 0dB
BBOUTI
(PIN 75)
BBOUTIB
(PIN 74)
150k
EN
FTUNEI
(PIN 77)
400MHz to 700MHz
2
1
LPF
10MHz to 30MHz
0dB
EN
1.5Vp-p
(DIFFERENTIAL)
BASEBAND
CHANNEL I
2:1
0 MUX
0⁄
1
PWRI
(PIN 85)
ENOPB
(PIN 68)
FLTRSEL
(PIN 95)
GND: ENABLE
VCC: DISABLE
0: INTERNAL
1: EXTERNAL
0dB
PWRQ
(PIN 96)
EN
LPF
10MHz to 30MHz
0⁄
1
1.5Vp-p
(DIFFERENTIAL)
BASEBAND
CHANNEL Q
2:1
0 MUX
1
0°
2
FTUNEQ
(PIN 4)
90°
150k
EN
6dB
MIXOUTQ BBINQ
(PIN 100) (PIN 3)
TNKA
(PIN 17)
DIV-16
TNKB
(PIN 14)
150k
400MHz to 700MHz
BBOUTQ
(PIN 6)
BBOUTQB
(PIN 7)
VCOPRE
(PIN 23)
VCOPREB
(PIN 24)
OFFQ
(PIN 5)
CQB
(PIN 69)
CQ
(PIN 70)
Figure 3. Functional Diagram—MAX2101 RF Front-End Section
______________________________________________________________________________________
11
MAX2101
6-Bit Quadrature Digitizer
REFERENCE
AMPLIFIER
–
BASEBAND
CHANNEL I
S0-S2
FULL-SCALE/2
COMMON
+ MODE
DATA
BUFFER
3
VREF
ADC
6
D0I-D5I
B/2
6
DCLK
(PIN 42)
VREF
(PIN 88)
DCLKB
(PIN 41)
SAMPLE-RATE
ADJUST
BANDGAP
REFERENCE
MCLK
(PIN 65)
VPTAT
(PIN 97)
DIV 6
RCLK
(PIN 39)
BASEBAND
CHANNEL Q
ADC
BINEN
(PIN 56)
6
DATA
BUFFER 6
VREF
COMMON
MODE
FULL-SCALE/2
D0Q-D5Q
B/2
REFERENCE
AMPLIFIER
Figure 4. Functional Diagram—MAX2101 ADCs and Supporting Sections
Filter Tuning
The MAX2101 integrates two 5th-order Butterworth lowpass filters for anti-alias filtering of the baseband signal. One filter exists for each of the I and Q channels.
The filters’ cutoff frequency is set by driving the FTUNE
pins, pin 77 (I channel) and pin 4 (Q channel). The user
sets the I/Q channel filters independently. Figure 6
shows a typical transfer curve of a filter’s cutoff frequency versus FTUNE voltage.
The MAX2101’s anti-aliasing filtering function provides
superior channel-to-channel matching compared to a
discrete implementation. The filters are realized using a
gyrator topology, which inherently has a strong temperature dependency. The temperature dependency of the
filters must be compensated to achieve a consistent filter response over ambient temperature. This compensation is easily summed with the user-supplied filter
tune signal, with the techniques discussed for both current-drive and voltage-drive implementations later in
this section. Figure 7 shows a typical characteristic of
the FTUNE signal required to provide a constant filter
cutoff frequency over temperature.
12
V+
RCHOKE
1k
CVAR
2pF to 10pF
FROM
PLL
FILTER
RBUF
10k
CVAR
2pF to 10pF
CC
470pF
14
RBUF
10k
CSH
3pF to 12pF
CFLTR
0.1µF
CC
470pF
LRES
8nH
17
Figure 5. Typical Parallel Resonant Network
______________________________________________________________________________________
TNKB
MAX2101
TNKA
6-Bit Quadrature Digitizer
FTUNE (V)
25
fC = 15MHz
1.95
20
15
MAX2101 TOC Fig. 7
TA = +25°C
CUTOFF FREQUENCY (MHz)
2.00
MAX2101 TOC Fig 6
30
MAX2101
FILTER CUTOFF FREQUENCY
TEMPERATURE DEPENDENCE
FILTER CUTOFF FREQUENCY
vs. FTUNE
1.90
1.85
1.80
10
1.75
1.70
5
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8
FTUNE (V)
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
Figure 6. Typical Filter Cutoff Frequency vs. FTUNE Input
Voltage
Figure 7. Typical Filter Cutoff Frequency Temperature
Dependence
The MAX2101 provides temperature-compensated bias
voltages that, when scaled and summed with the usersupplied filter-control signal, provide the necessary
compensation for the filters. The filter-control signal can
originate in one of two forms: an analog current, or an
analog voltage. The temperature compensation signal
will be added to the control signal as discussed below.
Current Drive
An alternate form of filter drive uses a current source,
such as a current-output DAC. The current is transformed to the appropriate voltage via a transresistance
network, which will drive the FTUNE input(s). The temperature compensation signals, VPTAT and VREF, are
shifted and scaled, transformed to current, added to
the user-supplied current, and the sum is transformed
back into the temperature compensated control voltage
(Figure 9).
Voltage Drive
A suggested technique of filter drive uses a voltage
source, such as a voltage output DAC. The temperature compensation signals, VPTAT and VREF, are shifted and scaled, then summed with the control voltage,
and the sum is applied to the FTUNE inputs. See Figure
8 for a possible implementation.
The transfer function for Figure 8’s voltage drive configuration can be evaluated as follows:
VTC = VREF +
RF
(VREF − VPTAT )
R TC
VFTUNE = VSET +
RF
(VREF − VPTAT )
R TC
Amplifier U1A generates a shifted reference signal,
V TC . V TC is transformed into a current through the
resistor RTC . R TC also scales this signal such that,
when compared to the feedback resistor RF, the proper
temperature dependence is added to the user-supplied
filter control current ISET to compensate for the TC of
the filter.
The expression for the final filter tune signal is
expressed as:
R
VFTUNE = ISET (RF ) + F (VREF − VPTAT )
R TC
Thus, the user-supplied signal VSET, which is characterized by a very small (ideally 0) temperature coefficient,
will be summed with a small signal (|VREF - VPTAT| ≤
200mV) whose temperature dependence compensates
for the filter’s TC.
______________________________________________________________________________________
13
MAX2101
6-Bit Quadrature Digitizer
R
VREF
(PIN 88)
VSET
R
1⁄
4
MAX418
R
27Ω
FTUNEI
(PIN 77)
0.01µF
DACA
VREF
(PIN 88)
VPTAT
(PIN 97)
R
RS
2.2k
RTC
1⁄
4
MAX418
5.6k
VTC
RF
R
4.7k
VREF
(PIN 88)
VSET
R
R
1⁄
4
MAX418
R
27Ω
FTUNELQ
(PIN 4)
0.01µF
DACB
R = 33kΩ, 1%
VCC = 5V
Figure 8. Independent Filter Tune Control Using Two Voltage-Output DACs
RF
4k
ISET
0.3mA to 1mA
VPTAT
(PIN 97)
(Q CHANNEL, PIN 4)
27Ω
0.01µF
FTUNE
(I CHANNEL, PIN 77)
DAC
1⁄
2
MAX407
0.01µF
33k, 1%
RTC
5k,
1%
33k, 1%
1⁄
2
MAX407
VREF
(PIN 88)
27Ω
VTC
33k, 1%
VCC = 5V
33k, 1%
Figure 9. Filter Tune Control Using a Single Current-Output DAC
14
______________________________________________________________________________________
6-Bit Quadrature Digitizer
by choosing the appropriate value of capacitance,
according to the following relation:
1
C=
2πfO (150kΩ)
where:
Baseband Offset Correction
The MAX2101 integrates a high level of RF signal processing, and applies substantial gain from the IF inputs
to the baseband signals applied to the ADC. Offset in
the signal path can seriously decrease the component’s dynamic range, and variation in offset between I
and Q channels can seriously degrade overall receiver
performance. Several circuit design techniques are
used to minimize offset within the chip. However, two
characteristics of the component contribute to offset in
the signal path.
The off-chip tank network for the VCO resonates the LO
frequency with a relatively large amplitude. If the LO
couples into the IF input, the coupled LO will mix down
to a DC value, which depends on the AGC setting. This
DC signal manifests itself as an offset in the baseband
signal. The second source of offset is the active lowpass anti-aliasing filters. This offset depends on the
cutoff frequency. These two elements represent the
major contributors to DC offset in the signal path.
Offset Adjust Pins OFFI, OFFQ
The MAX2101 offers an offset adjust pin for each of the
I and Q channels, labeled OFFI and OFFQ, respectively. The offset adjust input exhibits an adjustment range
that is sufficient to correct for the errors mentioned
above. The polarity of the OFF_ input is such that a
positive change of the OFF_ voltage results in a negative transition in the baseband signal, BBOUT_. The offset adjust range compensates for up to 5LSBs of offset.
A feedback-controlled, offset-correction network can
be realized that will null any offset detected in the baseband signal applied to the ADCs. The differential baseband signal is sampled at the input to the ADC and
integrated over a sufficiently large period of time (determined by the minimum frequency of the baseband signal), extracting the offset signal. This error signal is
internally applied to the OFF_ input, completing the
feedback loop. The MAX2101 integrates the op amps
and 150kΩ pickoff resistors of the offset correction network. Figure 10 shows a simplified schematic diagram
of the network. Simply connect the appropriate capacitors as shown in Figure 11.
The network in Figure 11 is a lowpass filter with a 5Hz
cutoff frequency. The user can tailor the cutoff frequency
C = integrator capacitance
for cutoff frequency
Frequency components of the baseband signal near or
below the cutoff frequency will interfere with the operation of this network. Fortunately, the compressed and
encoded nature of baseband signals at this stage of
the signal chain in typical applications will insure minimal low-frequency components. Hence, this technique
will eliminate all offsets, independent of AGC setting, filter cutoff frequency, or changes in ambient temperature.
Pin 68, ENOPB, is normally connected to ground.
Pulling ENOPB to V CC disables the op amps, thus
opening the servo loop, and disabling offset correction.
The baseband pins (6, 7, 74, 75) should be left unconnected, or buffered with a high-impedance load (resistive load greater than 10kΩ and capacitive load less
than 3pF).
Sample Clock Generation
The master sample clock (MCLK) input for the
MAX2101 is typically driven by a low-noise, low-drift
crystal oscillator. The signal should be between 0dBm
and +10dBm, and must be AC coupled to the MCLK
input. This signal is buffered and divided according to
the programmable sample-rate prescaler (PSRP). The
actual sample rates are binary weighted divisors of the
MCLK frequency. Program the sample rates with pins
S0, S1, and S2, as shown in Table 1.
Table 1. Sample-Rate Control
S2 S1 S0
Sample Rate
Description
0 0 0
fc/ 1
Full Sample Rate
0 0 1
fc/2
Div–2 Sample Rate
0 1 0
fc/4
Div–4 Sample Rate
0 1 1
fc/8
Div–8 Sample Rate
1 0 0
fc/8
Div–8 Sample Rate
1 0 1
fc/16
Div–16 Sample Rate
1 1 0
fc/32
Div–32 Sample Rate
1 1 1
fc/64
Div–64 Sample Rate
Note: The inputs S0, S1, and S2 are not latched.
______________________________________________________________________________________
15
MAX2101
Filter Temperature Compensation
In both techniques discussed above, the ratio RF/RTC determines the compensation required to produce a
filter response with 0TC. As noted in the VPTAT vs.
Temperature graph in the Typical Operating Characteristics,
this ratio should be set at 0.8.
MAX2101
6-Bit Quadrature Digitizer
76
72
71
CIB
CI
150k
BBOUTI
75
BBOUTIB
74
OFFI
150k
5
OFFQ
OFFI
220nF
MAX2101
68
ENOPB
MAX2101
CQ
150k
5
7
BBOUTQ
6
CQB
CQ
69
70
ENOPB
Figure 10. Offset Correction Network
Digital Signal Interfacing
The single-ended, LS-TTL compatible data outputs
from the ADCs are clocked out with respect to the rising edge of the data clock (DCLK). The output drivers
provide sufficient logic levels at speeds up to 60Mbps
into a fanout of 1 with a total load capacitance of 15pF.
All data outputs should have approximately equivalent
loading to ensure proper setup and hold timing.
The data clock outputs are also LS-TTL compatible and
provide a signal to latch the data at rates up to
60Mbps. The outputs are differential to minimize the
harmonic energy that might feed back into the LO or IF
inputs. The balanced outputs should have equivalent
termination to minimize unwanted EMI.
Select either binary or twos-complement output with the
binary enable (BINEN) pin. A logic high will select offset
binary, and a logic low will select a twos-complement
format.
Input Termination Network
The MAX2101 accepts as an input a narrow band IF
whose center frequency is located somewhere in the UHF
range, between 400MHz and 700MHz. The MAX2101
comprises a significant part of a receiver chain characterized by extremely high dynamic range coupled with
demanding intermodulation requirements. As such, it is
imperative to provide proper input termination to the
MAX2101, to minimize effective VSWR and noise figure at
this stage of the system RF signal processing chain.
The input of the MAX2101 is designed to deliver a
VSWR less than 2:1 over the 400MHz to 700MHz range.
16
CQB
OFFQ
150k
CIB
CI
BBOUTQB
76
220nF
72
71
70
69
220nF
220nF
68
Figure 11. Offset Correction
The equivalent input network of the input pins IFIN and
IFINB is discussed and illustrated below. However,
standard narrow-band impedance matching techniques can be used to improve on this VSWR for the
intended IF of the system.
Equivalent Input Circuitry
The MAX2101’s input amplifier is designed to provide a
controlled input impedance, provide gain for the signal
path, and provide for the component’s minimum noise
figure. The amplifier uses a feedback topology to provide gain that is insensitive to input frequency, in addition to delivering constant input impedance. Figure 12
illustrates the amplifier’s input portion.
Ideally, the input amplifier will be designed to match to
an anticipated source impedance of 50Ω. The resistive
portion of the input impedance at pin IFIN can be
approximated as follows:
R +r
RIN = F E
(1 + AV )
where rE is the dynamic resistance at Q3’s emitter, and
AV is the open-loop gain of the differential-pair amplifier
stage.
The amplifier can be designed so the frequency
response does not appreciably affect the input impedance. Details of the amplifier are left out for simplicity.
Figure 12 shows how several parasitic elements contribute to the input impedance over the frequencies of
interest. C PAD represents the parasitic capacitance
associated with the bond pad and input metallization.
______________________________________________________________________________________
6-Bit Quadrature Digitizer
MAX2101
VCC
RI
RI
Q3
IFIN
(PIN 90)
Q4
RF
LBW
RF
Q1
CPAD
LBW
IFINB
(PIN 91)
Q2
RE
RE
CPAD
Figure 12. Equivalent Input Network
As a result, it is challenging to achieve an extremely low
VSWR for the input of a monolithic amplifier, especially
over a wide range of frequencies. The MAX2101 provides
a VSWR less than 2:1, and delivers this performance over
the wide range of anticipated IFs currently considered.
Fortunately, for DBS, TVRO, and related applications, the
UHF IF is relatively narrow band, allowing the use of standard techniques for narrow-band impedance matching.
Narrow-Band Match
Many references cover narrow-band matching techniques. The match network synthesis is simplified by
assuming the impedance of the source driving the
MAX2101’s IFIN port is positive, real, and equal to 50Ω.
For a given IF, you can simply use a Smith chart to
“map” an impedance to the intended source resistance. Using a two-element matching network, you can
choose the element next to the input (CSH in Figure 14)
to translate the real portion of the impedance to match
the source resistance. The second element (LSER in
Figure 14) cancels the reactive component of the network (including the effect of CSH), resulting in a real,
matched input impedance that provides maximum
80
60
RE (ZIN)
MAX2101 TOC Fig. 15
IFIN (PIN 90) INPUT IMPEDENCE vs.
FREQUENCY
40
ZIN (Ω)
At frequencies of interest, CPAD will add a small phase
error to the impedance term. The inductance LBW models the bond wire and lead frame in series with the
input amplifier. This inductor represents a significant
portion of the input impedance, and will contribute the
majority of the variation in input impedance as the input
frequency is swept from 400MHz to 700MHz. These
variables combine to produce an actual input impedance versus frequency (Figure 13).
20
0
IM (ZIN)
-20
-40
200 300
400
500 600
700
800
900
FREQUENCY (MHz)
TA = +25°C
VCC = 5V
RS = 50Ω
IFINB (PIN 91) AC TERMINATED IN 25Ω
Figure 13. Typical MAX2101 IFIN ZIN vs. Frequency (Zs = 50)
power transfer. The transformation uses only reactive
elements so that no additional resistive thermal noise is
added, which would degrade the noise figure.
Figure 14 shows the resulting impedance matching network. The incident signal is AC coupled by CC. LSER
and C SH are the matching elements. C SH includes
board layout capacitance. The values of these ele-
______________________________________________________________________________________
17
MAX2101
6-Bit Quadrature Digitizer
RS
50Ω
VS
(fS = 600MHz)
CC
10nF
LSER
90
8nH
IFIN
CSH
1pF
(-47dBm to -7dBm)
MAX2101
91
IFINB
RTERM
25Ω
CTERM
10nF
Figure 14. Example of Input Network to Minimize VSWR and Noise Figure
ments were calculated assuming a 600MHz source frequency. Capacitor CTERM provides an AC termination
for the complementary input IFINB. Resistor RTERM provides superior noise figure performance by optimizing
the tradeoff between thermal induced noise and the
gain of the input amplifier. This network also provides
ancillary rejection of out-of-band energy, improving the
receiver noise figure and resulting SNR. The topology
shown above produces a VSWR less than 1.7:1 over
the intended UHF band. Do not DC couple the inputs to
ground, as this would result in saturation of the input
stage.
More elaborate matching networks can be designed
depending on the need of the receiver system.
__________Applications Information
Voltage-Controlled Oscillator Equivalent
Input Network and Resonator Issues
The MAX2101 performs the quadrature demodulation
and digitizing functions within a digital receiver system.
A vital component of the quadrature detection function
is the generation of a local oscillator (LO) frequency.
This signal is typically generated by a VCO controlled
by a phase-locked loop. The VCO topology normally
used for high dynamic range receivers is the negative
resistance amplifier and resonator, due to superior
phase-noise performance. The MAX2101 provides the
negative resistance amplifier on-chip, and can be easily interfaced with an off-chip resonant network.
The MAX2101’s VCO amplifier uses a differential topology for several reasons. The differential interface with
18
the resonator network provides superior rejection of
spurious signals that might otherwise add to or distort
the resulting LO. The differential interface minimizes the
effect of parasitic package-related elements that affect
the resonant frequency and the loaded Q of the network. The differential-drive network minimizes secondharmonic distortion that might create undesirable
mixing products within the signal chain.
Figure 15 shows the simplified input network of the
negative impedance amplifier, configured as a Wilson
oscillator. The amplifier is a simple differential emitter
coupled pair with emitter degeneration for controlled
open-loop gain. The positive feedback necessary to
create the negative input impedance is performed with
the feedback capacitors, CF, and the coupling capacitors, CC . The capacitors ensure operation over the
intended 400MHz to 700MHz spectrum, and add minimal noise to the system. RB1 provides a proper bias
voltage for the capacitors (partially constructed with
voltage-dependent pn junctions) and provides for DC
interface with a shunting resonant inductor. Note that
biasing networks are simplified for brevity.
The MAX2101’s negative impedance amplifier expects
a parallel resonant network. Figure 5 shows an example
of a tunable resonant network. The resonator is driven
from the phase-locked loop filter output, as noted. The
loaded Q of the resonant network, and to a lesser
extent the absolute values of the resonant elements,
determine the VCO’s phase-noise performance. As a
result, take care during the design of the resonator to
maximize the loaded Q. To achieve the phase-noise
______________________________________________________________________________________
6-Bit Quadrature Digitizer
MAX2101
VCC
RI
RI
CF
CF
CC
TNKA
(PIN 17)
RE
RB1
CC
TNKB
(PIN 14)
RE
RB2
RB2
VB1
RB1
VB2
IEE
Figure 15. Simplified Input Network for VCO Resonator Ports
performance in the specification, the resonant network
should exhibit a loaded Q greater than 20.
The resonating inductor LRES should exhibit as high a
Q factor as is reasonably possible. The inductor’s selfresonant frequency (SRF) should be well in excess of
the intended frequencies of operation. An air-wound
design is a simple example of an inductor that would fit
these criteria.
A dual varactor topology is recommended for CVAR to
compensate for the large-signal amplitude incident
across the resonator ports. The dual varactor in the
arrangement shown in Figure 5 (to first order) allows
cancellation of capacitance modulation due to the large
signals, as the two diodes are driven in a complementary fashion by the LO signal. The dual varactor design
also allows use of devices with larger CO values, simplifying device selection. The varactor should be driven
with a large reverse bias to increase the MAX2101’s
effective Q.
The resonant frequency is primarily determined by
CSH, which shunts the varactor diodes. CSH is trimmed
(selected) to determine the approximate tuning range
of the phase-locked loop. For applications relevant to
the MAX2101, this frequency range can cover the UHF
spectrum from 400MHz to 700MHz. The varactor within
the loop will then determine the actual LO frequency
within a much narrower tuning range. Depending on
the expected tuning range variation, CSH could be
made of a combination of fixed capacitance and
trimmed capacitance. This shunt capacitance will
increase the loaded Q of the resonator and lower the V
to F gain constant, improving the oscillator’s phasenoise performance.
The coupling capacitors CC couple the variable capacitor network to the tank ports and resonating inductor.
These elements should be selected to present low
impedance (less than 1Ω) at the lowest expected operating frequency. These capacitors should also exhibit
low effective series resistance (ESR) to maintain a high
resonator-loaded Q. RCHOKE provides a DC bias for
the varactors, while ensuring a high impedance at the
intended operating frequency. The magnitude of the
choke network’s series impedance should be approximately 10 times the resonant inductor’s impedance at
the operating frequency. Resistors RBUF provide drive
for the varactor while ensuring adequate isolation
between the two differential resonator ports. CFLTR, in
combination with RBUF, provides additional filtering of
the drive signal from the loop.
______________________________________________________________________________________
19
MAX2101
6-Bit Quadrature Digitizer
DBS System Application
A direct-broadcast satellite (DBS) receiver consists of
an antenna to receive the X/Ku band carrier from the
satellite, a low-noise block (LNB), an L-band downconverter, and a quadrature demodulator. The system
stages include a dual ADC, a matched filter, clock and
carrier recovery, error detection and correction, and
additional system-dependent DSP. See the Typical
Application Circuit on the first page of the data sheet.
The LNB provides polar demodulation (vertical and horizontal) and downconversion of the X/Ku band signals
to a first intermediate frequency (IF1) in the 950MHz to
2000MHz range. The L-band downconverter converts
IF 1 to a second IF (IF 2 ) in the 400MHz to 700MHz
range. The MAX2101 performs the next stages as follows: 1) the quadrature demodulator converts IF2 to
two baseband signals, I and Q; and 2) the dual ADCs
digitize the baseband signals, which are then
processed by the various digital blocks to compensate
for transmission distortion and to extract the digital
baseband data.
One interface that causes system designers trouble is
the quadrature demodulator to ADC interface. Power is
needed to drive the low-impedance interconnect
between these two functions. Additionally, this portion
of the signal path can introduce phase and amplitude
errors that complicate back-end error correction. The
integrated MAX2101 solves all of these design problems associated with DBS systems.
The MAX2101 combines bipolar technology with excellent RF and data-converter design to integrate the
quadrature demodulation and ADC functions. The
MAX2101 also includes an IF gain block, a VCO and
prescaler necessary to generate an accurate LO frequency, and fully integrated baseband anti-aliasing filters for both I and Q channels. By integrating several
functions supporting the quadrature demodulation and
A/D block, the MAX2101 replaces several components
and eliminates many board-level design and manufacturing problems.
Layout, Grounding, Bypassing
The MAX2101’s supply pins are separated to isolate
high-current digital noise spikes from sensitive RF and
analog sections. All ground potentials must be DC coupled, and resistive drops should contribute no more
than 50mV difference between the ground pins. A single-point analog ground (“star” ground point) should be
established at the ground supply connection to the PC
20
board, separate from the active circuitry. Three ground
planes should be established, connected at the star
ground point. The three ground planes should be dedicated as follows: analog and RF ground plane, digital
ground plane, and output ground plane. The various
ground pins should be connected to this star ground
network according to Table 2. The ground current
return path for all supplies should be low impedance at
frequencies of interest for each supply.
Table 2. Ground Plane Assignments
Ground Pin
Pin Number
Ground Plane
VGNDIF
94
analog
VGNDI
79
analog
VGNDQ
2
analog
VGND2
16
analog
20, 21
analog
VGNDP
10
digital
VGNDC
66
digital
VGNDD
34, 47
digital
VGNDO
26, 30, 37, 43, 51, 55
output
VGNDAD
For best performance, use printed circuit boards. Wirewrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital (especially clock) lines parallel to one another, or
digital lines underneath the MAX2101 package.
The MAX2101 requires +5V ±5% for all supply pins.
Bypass the supply pins with high-quality 0.1µF and
0.001µF ceramic capacitors located as close to the
package as possible. The high-frequency supplies,
VCCIF and VCC2, both require an additional ceramic
surface-mount bypass capacitor nominally valued at
47pF. The baseband supplies (VCCI and VCCQ) need
additional filtering to ensure sufficient channel-to-channel isolation. Place a small-value resistor, such as 5Ω,
between the supply and the pins to create a single-pole
filter with the bypass capacitor. The DC IR drop across
the resistor should not exceed 150mV. Alternatively,
place an RF choke between the supply and the pins.
The SRF of the selected choke must be high enough to
block energy from the other baseband channel.
______________________________________________________________________________________
6-Bit Quadrature Digitizer
MIXOUTQ
GND
GND
VPTAT
PWRQ
FLTRSEL
VGNDIF
AGC
GND
IFINB
IFIN
GND
VREF
VCCIF
2R5
PWRI
VSUBRF
GND
GND
MIXOUTI
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
TOP VIEW
GND
1
80
VREFIN
VGNDQ
2
79
VGNDI
BBINQ
3
78
BBINI
FTUNEQ
4
77
FTUNEI
OFFQ
5
76
OFFI
BBOUTQ
6
75
BBOUTI
BBOUTQB
7
74
BBOUTIB
VCCQ
8
73
VCCI
GND
9
72
CIB
VGNDP
10
71
CI
VCCP
11
70
CQ
GND
12
69
CQB
GND
13
68
ENOPB
TNKB
14
67
GND
VCC2
15
66
VGNDC
VGND2
16
65
MCLK
TNKA
17
64
VCCC
GND
18
63
GND
GND
19
62
S0
VGNDAD
20
61
VCCAD
MAX2101
44
45
46
47
48
49
50
VCCO
D0I
D1I
VGNDD
VCCD
D2I
D3I
VGNDO
43
51
42
30
DCLK
VCCO
VGNDO
VGNDO
VCCO
52
41
D4I
29
DCLKB
53
40
28
VCCO
D5I
D4Q
39
VGNDO
54
38
55
27
RCLK
26
D5Q
VCCO
VGNDO
37
BINEN
VGNDO
56
36
25
D0Q
S2
VCCO
35
57
D1Q
24
34
S1
VCOPREB
33
58
VCCD
VSUBAD
23
VGNDD
59
VCOPRE
32
22
31
60
VSUBAD
D3Q
21
VCCAD
D2Q
VGNDAD
MQFP
______________________________________________________________________________________
21
MAX2101
____________________________________________________________Pin Configuration
MAX2101
6-Bit Quadrature Digitizer
________________________________________________________Package Information
D
D1
D3
DIM
S
0.40
0.016 MIN.
ZD
R 0.012
E 0.005
E1
DETAIL "A"
0° MIN.
E3
DATUM
PLANE
α
R 0.012
0.005 MIN.
L
PIN #1
1.6
0.063
ZE
5°-16°
A
A
BASE
PLANE
22
e
B
SEATING
PLANE
MILLIMETERS
MIN
MAX
2.79
3.40
0.25
–
2.55
3.05
0.22
0.38
22.95
23.45
16.95
17.45
13.90
14.10
12.35 REF
0.65 BSC
19.90
20.10
18.85 REF
0.65
0.95
0.58 REF
0.83 REF
0°
7°
21-7003A
A1
A2
A
A1
A2
B
D
E
E1
E3
e
D1
D3
L
ZD
ZE
α
INCHES
MIN
MAX
0.110
0.134
0.010
–
0.100
0.120
0.009
0.015
0.904
0.923
0.667
0.687
0.547
0.555
0.486 REF
0.0256 BSC
0.783
0.791
0.742 REF
0.026
0.037
0.023 REF
0.033 REF
0°
7°
100-PIN MQFP
METRIC
QUAD FLAT PACK
______________________________________________________________________________________
6-Bit Quadrature Digitizer
MAX2101
______________________________________________________________________________________
23
MAX2101
6-Bit Quadrature Digitizer
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 1996 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.