19-1270; Rev 0; 7/97 KIT ATION EVALU LE B A IL A AV Low-Power, 60Msps, Dual, 6-Bit ADC ____________________________Features ♦ ±1/4LSB INL and DNL, Typical The MAX1002 input amplifiers feature true differential inputs, a 55MHz -0.5dB analog bandwidth, and userprogrammable input full-scale ranges of 125mVp-p, 250mVp-p, or 500mVp-p. With an AC-coupled input signal, matching performance between input channels is typically 0.1dB gain, 1/4LSB offset, and 0.5° phase. Dynamic performance is 5.85 effective number of bits (ENOB) with a 20MHz analog input signal, or 5.78 ENOB with a 50MHz input signal. The MAX1002 operates with a single +5V power supply and provides TTL-compatible digital outputs. The device is available in the commercial temperature range (0°C to +70°C) and comes in a 36-pin SSOP package. ♦ 55MHz (-0.5dB) Bandwidth Input Amplifiers with True Differential Inputs ♦ User-Selectable Input Full-Scale Range (125mVp-p, 250mVp-p, or 500mVp-p) ♦ Single-Ended or Differential Input Drive ________________________Applications Direct Broadcast Satellite (DBS) Receivers VSAT Receivers Wide Local Area Networks (WLAN) Cable Television Set-Top Boxes ♦ 1/4LSB (typ) Channel-to-Channel Offset Matching ♦ 0.1dB Gain and 0.5° Phase Matching, Typical ♦ Internal Bandgap Voltage Reference ♦ Two Matched 6-Bit, 60Msps ADCs ♦ Excellent Dynamic Performance: 5.85 ENOB with 20MHz Analog Input 5.7 ENOB with 50MHz Analog Input ♦ Internal Oscillator with Overdrive Capability ♦ +5V Single Supply ♦ TTL Outputs ♦ 90Msps Upgrade with +3.3V CMOS-Compatible Output Available (MAX1003) ______________Ordering Information PART TEMP. RANGE MAX1002CAX PIN-PACKAGE 0°C to +70°C 36 SSOP Pin Configuration appears at end of data sheet. _________________________________________________________Functional Diagram IOCC+ IOCC- IIN+ IIN- INPUT AMP I ADC I VREF 6 OFFSET CORRECTION I GAIN QIN- CLOCK OUT MAX1002 VREF ADC Q QOCC+ DCLK TNK- OFFSET CORRECTION Q INPUT AMP Q D0I–D5I TNK+ CLOCK DRIVER BANDGAP REFERENCE QIN+ 6 DATA BUFFER I 6 DATA BUFFER Q 6 DQ0–DQ5 QOCC- ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800 For small orders, phone 408-737-7600 ext. 3468. MAX1002 _______________General Description The MAX1002 is a dual, 6-bit analog-to-digital converter (ADC) that combines high-speed, low-power operation with a user-selectable input range, an internal reference, and a clock oscillator. The dual, parallel ADCs are designed to convert in-phase (I) and quadrature (Q) analog signals into two 6-bit offset-binary-coded digital outputs at sampling rates up to 60Msps while achieving typical integral nonlinearity (INL) and differential nonlinearity (DNL) of ±1/4LSB. The ability to interface directly with baseband I and Q signals makes the MAX1002 ideal for use in direct-broadcast satellite, VSAT, and QAM16 demodulation applications. MAX1002 Low-Power, 60Msps, Dual, 6-Bit ADC ABSOLUTE MAXIMUM RATINGS VCC to GND .........................................................-0.3V to +6.5V VCCO to OGND.........................................................-0.3V, +6.5V GND to OGND .........................................................-0.3V, +0.3V Digital and Clock Output Pins to OGND ........-0.3V, VCCO (<10sec) All Other Pins to GND..................................................-0.3V, VCC Continuous Power Dissipation (TA = +70°C) SSOP (derate 45mW/°C above +70°C) ......................941mW Operating Temperature Range...............................0°C to +70°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, <10sec)...........................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC, VCCO = +5V ±5%; TA = TMIN to TMAX; unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note 1) Resolution RES 6 Integral Nonlinearity INL -0.5 ±0.25 0.5 LSB Bits Differential Nonlinearity DNL No missing codes over temperature -0.5 ±0.25 0.5 LSB VFSH GAIN = VCC (high gain) 118.75 125 131.25 Full-Scale Input Range VFSM GAIN = open (mid gain) 237.5 250 262.5 VFSL GAIN = GND (low gain) 475 500 525 mVp-p INVERTING AND NONINVERTING ANALOG INPUTS Input Open-Circuit Voltage VAOC 2.25 2.35 2.45 V Input Resistance RIN 13 20 29 kΩ Input Capacitance CIN Guaranteed by design 3 5 pF Common-Mode Voltage Range VCM Other analog input driven with external source (Note 2) 1.75 2.75 V ROSC Other oscillator input tied to VCC + 0.3V 4.8 12.1 kΩ 2.4 OSCILLATOR INPUTS Oscillator Input Resistance 8 DIGITAL OUTPUTS (DI0–DI5, DQ0–DQ5) Digital Outputs Logic-High Voltage VOH ISOURCE = 50µA Digital Outputs Logic-Low Voltage VOL ISINK = 400µA V 0.5 V 63 104 mA -75 -40 dB 24 mA POWER SUPPLY Supply Current Power-Supply Rejection Ratio Digital Outputs Supply Current Power Dissipation 2 ICC PSRR VCC = 4.75V to 5.25V (Note 3) ICCO 20MHz, FS I & Q analog inputs, CLOAD = 15pF (Note 4) PD 380 _______________________________________________________________________________________ mW Low-Power, 60Msps, Dual, 6-Bit ADC (VCC, VCCO = +5V ±5%; TA = +25°C; unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DYNAMIC PERFORMANCE (GAIN = open; external 60MHz clock (Figure 7); VINI, VINIQ = 20MHz sine; amplitude -1dB below FS; unless otherwise noted.) Maximum Sample Rate fMAX Analog Input -0.5dB Bandwidth BW 60 Gain = GND, open, VCC GAIN = open (mid gain) 5.7 ENOBH ENOBL Gain = VCC (high gain) Gain = VCC (low gain) 5.8 5.85 SINAD Gain = open (mid gain) 35.4 I channel -0.5 0.5 Q channel -0.5 0.5 OFF Crosstalk Between ADCs XTLK Amplitude Match Between ADCs Phase Match Between ADCs MHz 5.85 GAIN = open (mid gain), VIN = 50MHz, -1dB below FS Input Offset (Note 5) Offset Mismatch Between ADCs 5.6 ENOBM Effective Number of Bits Signal-to-Noise and Distortion Ratio Msps 55 OMM2 Bits 37 dB -55 (Note 5) LSB dB -0.5 ±0.25 0.5 LSB AM -0.2 ±0.1 0.2 dB PM -2 ±0.5 2 degrees TIMING CHARACTERISTICS (data outputs: RL = 1MΩ, CL = 15pF, Figure 8) DCLK to Data-Propagation Delay tPD (Note 6) 7.1 ns Data Valid Skew tSKEW (Note 6) 3.6 ns Input to DCLK Delay tDCLK TNK+ to DCLK (Note 6) 5.3 ns Aperture Delay tAP 5.5 ns Pipeline Delay PD 1 clock cycle Note 1: Best straight-line linearity method. Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V). However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this commonmode input range (Figures 4, 5). Note 3: PSSR is defined as the change in the mid-gain, full-scale range as a function of the variation in VCC supply voltage (expressed in decibels). Note 4: The current in the VCCO supply is a strong function of the capacitive loading on the digital outputs. To minimize supply transients and achieve the best dynamic performance, reduce the capacitive loading effects by keeping line lengths on the digital outputs to a minimum. Note 5: Offset-correction compensation enabled, 0.22µF at Q and I compensation inputs (Figures 2, 3). Note 6: tPD and tSKEW are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a data bit. tDCLK is measured from the 50% level of the clock overdrive signal on TNK+ to the 1.4V level of DCLK. The capacitive load on the outputs is 15pF. _______________________________________________________________________________________ 3 MAX1002 AC ELECTRICAL CHARACTERISTICS __________________________________________Typical Operating Characteristics (VCC, VCCO = +5V ±5%; MAX1002/MAX1003 evaluation kit; TA = +25°C; unless otherwise noted.) EFFECTIVE NUMBER OF BITS vs. ANALOG INPUT FREQUENCY EFFECTIVE NUMBER OF BITS vs. SAMPLING FREQUENCY ANALOG INPUT BANDWIDTH 0 MAX1002-03 6.0 MAX1002-02 MAX1002-01 6.0 5.9 5.8 5.6 5.4 5.2 5.8 ENOB MAGNITUDE (dB) -0.2 -0.4 5.7 -0.6 -0.8 5.6 -1.0 5.5 fIN = 20MHz fCLK = 60Msps 5.0 1 100 10 10 100 10 SAMPLING FREQUENCY (MHz) OPEN-LOOP PHASE NOISE vs. FREQUENCY FFT PLOT 0 MAX1002-TOC4 -50 -70 PHASE NOISE (dBc) 100 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz) MAX1002-05 ENOB (bits) fIN = 19.930MHz fCLK = 60.000MHz 1024 POINTS AC COUPLED SINGLE ENDED AVERAGED -20 -90 -40 -110 -60 -130 -80 -150 1k 100k 10k 1M 0 6 FREQUENCY (Hz) 12 18 24 30 FREQUENCY (MHz) DIFFERENTIAL NONLINEARITY vs. CODE DIFFERENTIAL NONLINEARITY vs. CODE 0.25 MAX1002-07 0.50 MAX1002-06 0.50 0.25 DNL (LSB) DNL (LSB) MAX1002 Low-Power, 60Msps, Dual, 6-Bit ADC 0 -0.25 0 -0.25 -0.50 0 10 20 30 CODE 4 40 50 60 64 -0.50 0 10 20 30 40 _______________________________________________________________________________________ 50 60 64 Low-Power, 60Msps, Dual, 6-Bit ADC PIN NAME 1 GAIN FUNCTION 2 IOCC+ Positive I-Channel Offset-Correction Compensation. Connect 0.22µF capacitor for AC-coupled inputs (Figures 2, 3). Ground for DC-coupled inputs (Figures 4, 5). 3 IOCC- Negative I-Channel Offset-Correction Compensation. Connect 0.22µF capacitor for AC-coupled inputs (Figures 2, 3). Ground for DC-coupled inputs (Figures 4, 5). 4 IIN+ I-Channel Noninverting Analog Input 5 IIN- I-Channel Inverting Analog Input 6 VCC +5V ±5% Supply. Bypass with 0.01µF capacitor to GND (Pin 7). 7, 11, 12, 18, 19 GND Analog Ground 8 VCC +5V ±5% Supply. Bypass with 0.01µF capacitor to GND (Pin 11). 9 TNK+ Positive Oscillator/Clock Input 10 TNK- Negative Oscillator/Clock Input 13 VCC +5V ±5% Supply. Bypass with 0.01µF capacitor to GND (Pin 12). 14 QIN- Q-Channel Inverting Analog Input 15 QIN+ Q-Channel Noninverting Analog Input 16 QOCC- Negative Q-Channel Offset-Correction Compensation. Connect 0.22µF capacitor for AC-coupled inputs (Figures 2, 3). Ground for DC-coupled inputs (Figures 4, 5). 17 QOCC+ Positive Q-Channel Offset-Correction Compensation. Connect 0.22µF capacitor for AC-coupled inputs (Figures 2, 3). Ground for DC-coupled inputs (Figures 4, 5). Gain-Select Input. Sets input full-scale range: 125/250/500mVp-p (Table 1). 20–25 DQ5–DQ0 Q-Channel Digital Outputs 0–5. DQ5 is the most significant bit (MSB). 26, 28 VCCO +5V ±5% Digital Supply. Bypass each with 47pF to OGND (Pin 27). 27 OGND Digital Output Ground Digital Clock Output. Frames the output data. 29 DCLK 30–35 DI0–DI5 36 VCC I-Channel Digital Outputs 0–5. DI5 is the most significant bit (MSB). +5V ±5% Supply. Bypass with 0.01µF to GND (Pin 19). _______________Detailed Description Converter Operation The MAX1002 contains two 6-bit analog-to-digital converters (ADCs), a buffered voltage reference, and oscillator circuitry. The ADCs use a flash-conversion technique to convert an analog input signal into a 6-bit parallel digital output code. The MAX1002’s unique design includes 63 fully differential comparators and a proprietary encoding scheme that ensures no more than 1LSB dynamic encoding error. The control logic interfaces easily to most digital signal processors (DSPs) and microprocessors (µPs) with +5V CMOScompatible logic interfaces. Figure 1 shows the MAX1002 in a typical application. Programmable Input Amplifiers The MAX1002 has in-phase (I) and quadrature (Q) programmable-gain input amplifiers with a 55MHz -0.5dB bandwidth and true differential inputs. To maximize performance in high-speed systems, each amplifier has less than 5pF of input capacitance. The input amplifier gain is programmed via the GAIN pin to provide three possible input full-scale ranges (FSR) (Table 1). Table 1. Input Amplifier Programming GAIN INPUT FULL-SCALE RANGE (mVp-p) GND 500 Open 250 VCC 125 _______________________________________________________________________________________ 5 MAX1002 ______________________________________________________________Pin Description MAX1002 Low-Power, 60Msps, Dual, 6-Bit ADC Figures 2 and 3 show single-ended and differential ACcoupled input circuits. Each of the amplifier inputs is internally biased to a 2.35V reference through a 20kΩ resistor, eliminating external DC bias circuits. A series 0.1µF capacitor is required at each amplifier input for AC-coupled signals. When operating with AC-coupled inputs, the input amplifiers’ DC offset voltage is nulled to within ±1/2LSB by an on-chip offset-correction amplifier. An external compensation capacitor is required to set the dominant pole of the offset-correction amplifier’s frequency response (Figures 2 and 3). The compensation capacitor determines the low-frequency corner of the analog input response according to the following formula: fc = 1 / (0.1 x C) where C is the value of the compensation capacitor in µF, and fc is the corner frequency in Hz. LNB 75Ω CABLE 950MHz TO 2150MHz F-CONNECTOR FOR 2ND SET-TOP BOX KU BAND F-CONNECTOR INPUT OR VARACTOR-TUNED PRESELECTION FILTER FROM TANK VOLTAGE VCC (x7) AGC AGC 6 BITS RFIN IIN IOUT RFIN 0 60Msps 90 EXTERNAL VCO DATA BUFFER CLK IN MAX2102 DSP 6 BITS QOUT DATA BUFFER QIN LO DAC OR ADC CLOCK DIV LO TANK MAX1002 OFFSET CORRECTION SYNTHESIZER MODCTL OR OFFI OFFQ OFFI PSOUT MOD GND (x8) OFFQ TANK TSA5055 or EQUIVALENT Figure 1. Commercial Satellite Receiver System 6 _______________________________________________________________________________________ FIN CAR Low-Power, 60Msps, Dual, 6-Bit ADC ADCs The I and Q ADC blocks receive the analog signals from the respective I and Q input amplifiers. The ADCs use flash conversion with 63 fully differential comparators to digitize the analog input signal into a 6-bit output in offset binary format. 0.22µF 0.22µF _OCC+ _OCC+ _OCC- OFFSET CORRECTION OFFSET CORRECTION 0.1µF 0.1µF _IN+ INPUT AMP VSOURCE _IN+ INPUT AMP VSOURCE _IN- _IN- 0.1µF 0.1µF 20k MAX1002 20k 20k MAX1002 20k 2.35V INTERNAL REFERENCE 2.35V INTERNAL REFERENCE (ONE CHANNEL SHOWN) (ONE CHANNEL SHOWN) Figure 3. Differential AC-Coupled Input Figure 2. Single-Ended AC-Coupled Input OFFSET-CORRECTION DISABLED OFFSET-CORRECTION DISABLED _IOCC+ _IOCC+ _IOCC- _IIN+ _IIN+ INPUT AMP VSOURCE INPUT AMP VSOURCE _IIN- _IIN20k _IOCCOFFSET CORRECTION OFFSET CORRECTION VCM 1.75V TO 2.75V _OCC- MAX1002 20k 2.35V INTERNAL REFERENCE 20k DIFFERENTIAL SOURCE WITH 1.75V TO 2.75V COMMON-MODE RANGE MAX1002 20k 2.35V INTERNAL REFERENCE (ONE CHANNEL SHOWN) (ONE CHANNEL SHOWN) Figure 4. Single-Ended DC-Coupled Input Figure 5. Differential DC-Coupled Input _______________________________________________________________________________________ 7 MAX1002 Figures 4 and 5 show single-ended and differential DCcoupled input circuits for applications where a DC component of the input signal is present. The amplifiers’ input common-mode voltage range extends from 1.75V to 2.75V. To prevent attenuation of the input signal’s DC component when operating in this mode, disable the offset-correction amplifier by grounding the _OCC+ and _OCC- pins for the I and Q blocks (Figures 4 and 5). MAX1002 Low-Power, 60Msps, Dual, 6-Bit ADC The MAX1002 features a proprietary encoding scheme that ensures no more than 1LSB dynamic encoding error. Dynamic encoding errors resulting from metastable states may occur when the analog input voltage, at the time the sample is taken, falls close to the decision point for any one of the input comparators. The resulting output code for typical converters can be incorrect, including false full- or zero-scale outputs. The MAX1002’s unique design reduces the magnitude of this type of error to 1LSB. Internal Voltage Reference An internal buffered bandgap reference is included on the MAX1002 to drive the ADC’s reference ladders. The on-chip reference and buffer eliminate any external (high-impedance) connections to the reference ladder, minimizing the potential for noise coupling from external circuitry while ensuring that the voltage reference, input amplifier, and reference ladder track well with variations in temperature and power supplies. Oscillator Circuit The MAX1002 includes a differential oscillator, which is controlled by an external parallel resonant (tank) network (Figure 6). As an alternative, the oscillator may be overdriven with an external clock source (Figure 7). Internal-Clock Operation (Tank) If the tank circuit is used, the resonant inductor should have a sufficiently high Q and a self-resonant frequency (SRF) of at least twice the intended oscillator frequency. Coilcraft's 1008HS-221, with a 700MHz SRF and a Q of 45, works well for this application. Generate different clock-frequency ranges by adjusting varactor and tank elements. An internal-clock-driver buffer is included to provide sharp clock edges to the internal flash comparators. The buffer ensures that the comparators are simultaneously clocked, maximizing the ADC’s effective number of bits of performance. External-Clock Operation To accommodate designs that use an external clock, the MAX1002’s internal oscillator can be overdriven by an external clock source (Figure 7). The external clock source should be a sinusoid to minimize clock-phase noise and jitter, which can degrade the ADC’s effective bits performance. AC couple the clock source (recommended voltage level is approximately 1Vp-p) to the oscillator inputs (Figure 7). 47k 47pF TNK+ 0.1µF 50Ω 10k 22pF VTUNE CL0CK DRIVER 220nH Z0 = 50Ω TNK+ VC TNK- 50Ω CLOCK DRIVER 47pF 47k MAX1002 TNK0.1µF MAX1002 50Ω VTUNE = 0V TO 8V fOSC = 55MHz TO 65MHz VARACTOR DIODE PAIR IS M/A-COM MA4ST079CK-287 (SOT23 PACKAGE). INDUCTOR IS COILCRAFT 1008HS-221. Figure 6. Tank-Resonator Oscillator 8 VCLOCK = 300mVp-p TO 1.25Vp-p Figure 7. External-Clock-Drive Circuit _______________________________________________________________________________________ Low-Power, 60Msps, Dual, 6-Bit ADC MAX1002 N N+1 ANALOG INPUT N+2 tAP 50% TNK+ (INPUT CLOCK) tDCLK 1.4V tPD DCLK tSKEW DATA OUT DATA VALID N - 1 1.4V DATA VALID N Figure 8. MAX1002 Timing Diagram Output Data Format Transfer Function Figure 9 shows the MAX1002’s nominal transfer function. Output coding is offset binary with 1LSB = FSR / 63. 111111 111110 111101 OUTPUT CODE The conversion results are output on a dual 6-bit-wide data bus. Data is latched into the ADC output latch following a pipeline delay of one clock cycle (Figure 8). Output data is clocked out of the respective ADC’s dataoutput pins (D_0 through D_5) on the rising edge of the clock output (DCLK), with a DCLK-to-data propagation delay (tPD) of 7.1ns. The MAX1002 outputs are TTL compatible. 100001 100000 011111 011110 000011 000010 000001 000000 -FSR 2 1LSB 0 FSR 2 INPUT VOLTAGE (_IN+ to _IN-) Figure 9. Ideal Transfer Function _______________________________________________________________________________________ 9 MAX1002 Low-Power, 60Msps, Dual, 6-Bit ADC __________Applications Information _____________Dynamic Performance Layout, Grounding, and Bypassing Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to all other ADC output signals. The output spectrum is limited to frequencies above DC and below one-half the ADC sample rate. The theoretical minimum A/D noise is caused by quantization error, and results directly from the ADC’s resolution: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. Therefore, a perfect 6-bit ADC can do no better than 38dB. The FFT Plot (see Typical Operating Characteristics) shows the result of sampling a pure 20MHz sinusoid at a 60MHz clock rate. This FFT plot of the output shows the output level in various spectral bands. The plot has been averaged to reduce the quantization noise floor and reveal the low-amplitude spurs. This emphasizes the excellent spurious-free dynamic range of the MAX1002. The effective resolution (or ENOB) the ADC provides can be measured by transposing the equation that converts resolution to SNR: N = (SINAD - 1.76) / 6.02 (see Typical Operating Characteristics). The MAX1002 is designed with separate analog and digital power-supply and ground connections to isolate high-current digital noise spikes from the more sensitive analog circuitry. The high-current digital output ground (OGND) and analog ground (GND) should be at the same DC level, connected at only one location on the board. This provides best noise immunity and improved conversion accuracy. Use of separate ground planes is strongly recommended. The entire board requires good DC bypassing for both analog and digital supplies. Place the bypass capacitors close to where the power is routed onto the board, i.e., close to the connector. 10µF electrolytic capacitors with low ESR-ratings are recommended. For best effective bits performance, minimize capacitive loading at the digital outputs. Keep the digital output traces as short as possible. The MAX1002 can operate with one +5V supply. For optimum performance, separate +5V ±5% supplies and bypassing are recommended. Bypass each of the VCC supply pins to its respective GND with highquality ceramic capacitors located as close to the package as possible (Table 2). Consult the evaluation kit for a suggested layout and bypassing scheme. Table 2. Bypassing SUPPLY FUNCTION VCC / VCCO BYPASS TO GND/OGND CAPACITOR VALUE Analog Inputs 6 7 0.01µF Oscillator/Clock 8 11 0.01µF Converter 13 12 0.01µF Digital Q Output 26 27 47pF Digital I Output 28 27 47pF Buffer 36 19 0.01µF 10 ______________________________________________________________________________________ Low-Power, 60Msps, Dual, 6-Bit ADC ___________________Chip Information TRANSISTOR COUNT: 6097 TOP VIEW GAIN 1 36 VCC IOCC+ 2 35 DI5 IOCC- 3 34 DI4 IIN+ 4 33 DI3 IIN- 5 32 DI2 VCC 6 MAX1002 31 DI1 GND 7 30 DI0 VCC 8 29 DCLK TNK+ 9 28 VCCO TNK- 10 27 OGND GND 11 26 VCCO GND 12 25 DQ0 VCC 13 24 DQ1 QIN- 14 23 DQ2 QIN+ 15 22 DQ3 QOCC- 16 21 DQ4 QOCC+ 17 20 DQ5 GND 18 19 GND SSOP ______________________________________________________________________________________ 11 MAX1002 __________________Pin Configuration ________________________________________________________Package Information SSOP2.EPS MAX1002 Low-Power, 60Msps, Dual, 6-Bit ADC Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1997 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.