Quad-Channel Isolators with Integrated DC-to-DC Converter ADuM5401W/ADuM5402W/ADuM5403W FUNCTIONAL BLOCK DIAGRAMS VDD1 1 OSC RECT REG GND1 2 VIA/VOA 3 VIB/VOB 4 VIC/VOC 5 16 VISO 15 GNDISO 14 VOA/VIA 4 CHANNEL iCOUPLER CORE ADuM5401W/ADuM5402W/ ADuM5403W VOD 6 13 VOB/VIB 12 VOC/VIC 11 VID RCOUT 7 10 VSEL GND1 8 9 GNDISO Figure 1. ADuM5401W/ADuM5402W/ADuM5403W Block Diagram VIA VIB VIC APPLICATIONS VOD Hybrid electric battery management 3 4 ADuM5401W 14 13 5 12 6 11 VOA VOB VOC VID 08758-002 isoPower integrated, isolated dc-to-dc converter Qualified for automotive applications Regulated 5 V output Up to 500 mW output power Quad dc-to-25 Mbps (NRZ) signal isolation channels 16-lead SOIC package with 7.6 mm creepage High temperature operation: 105°C High common-mode transient immunity: >25 kV/μs Safety and regulatory approvals UL recognition: 2500 V rms for 1 minute per UL1577 CSA Component Acceptance Notice #5A VDE certificate of conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 560 V peak 08758-001 FEATURES Figure 2. ADuM5401W GENERAL DESCRIPTION VIB VOC VOD 3 4 ADuM5402W 14 13 5 12 6 11 VOA VOB VIC VID 08758-003 VIA The ADuM5401W/ADuM5402W/ADuM5403W1 devices are quad-channel digital isolators with isoPower®, an integrated, isolated dc-to-dc converter. Based on the Analog Devices, Inc., iCoupler® technology, the dc-to-dc converter provides up to 500 mW of regulated, isolated power at 5.0 V. This eliminates the need for a separate, isolated dc-to-dc converter in low power, isolated designs. The iCoupler chip-scale transformer technology is used to isolate the logic signals and for the magnetic components of the dc-to-dc converter. The result is a small form factor, total isolation solution. Figure 3. ADuM5402W VOC VOD The ADuM5401W/ADuM5402W/ADuM5403W isolators provide four independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide for more information). 3 4 ADuM5403W 14 13 5 12 6 11 VOA VIB VIC VID 08758-004 VIA VOB Figure 4. ADuM5403W isoPower uses high frequency switching elements to transfer power through its transformer. Special care must be taken during printed circuit board (PCB) layout to meet emissions standards. Refer to the AN-0971 application note for board layout recommendations at www.analog.com. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. ADuM5401W/ADuM5402W/ADuM5403W TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 12 Applications ....................................................................................... 1 Terminology .................................................................................... 14 General Description ......................................................................... 1 Applications Information .............................................................. 15 Functional Block Diagrams ............................................................. 1 Theory of Operation .................................................................. 15 Revision History ............................................................................... 2 PCB Layout ................................................................................. 15 Specifications..................................................................................... 3 Thermal Analysis ....................................................................... 15 Electrical Characteristics—5 V Primary Input Supply/5 V Secondary Isolated Supply .......................................................... 3 Propagation Delay-Related Parameters ................................... 16 Package Characteristics ............................................................... 5 DC Correctness and Magnetic Field Immunity........................... 16 Regulatory Approvals................................................................... 5 Power Consumption .................................................................. 17 Insulation and Safety-Related Specifications ............................ 5 Power Considerations ................................................................ 17 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics .............................................................................. 6 Insulation Lifetime ..................................................................... 18 Recommended Operating Conditions ...................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution .................................................................................. 7 EMI Considerations ................................................................... 16 VISO Startup Issues ...................................................................... 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20 Pin Configurations and Function Descriptions ........................... 8 Truth Table .................................................................................. 11 REVISION HISTORY 1/10—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADuM5401W/ADuM5402W/ADuM5403W SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY All typical specifications are at TA = 25°C, VDD1 = VISO = 5 V. Minimum/maximum specifications apply over the entire recommended operation range, which is 4.5 V ≤ VDD1, VISO ≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted. Table 1. DC-to-DC Converter Static Specifications Parameter DC-TO-DC CONVERTER SUPPLY Setpoint Line Regulation Load Regulation Output Ripple Output Noise Switching Frequency PW Modulation Frequency Output Supply Current Efficiency at IISO (MAX) IDD1, No VISO Load IDD1, Full VISO Load Symbol Min Typ Max Unit Test Conditions VISO VISO (LINE) VISO (LOAD) VISO (RIP) VISO (NOISE) fOSC fPWM IISO (MAX) 4.7 5.0 1 1 75 200 180 625 5.4 V mV/V % mV p-p mV p-p MHz kHz mA % mA mA IISO = 0 mA IISO = 50 mA, VDD1 = 4.5 V to 5.5 V IISO = 10 mA to 90 mA 20 MHz bandwidth, CBYPASS = 0.1 μF||10 μF, IISO = 90 mA CBYPASS = 0.1 μF||10 μF, IISO = 90 mA 5 100 34 20 290 IDD1 (Q) IDD1 (MAX) 35 VISO > 4.5 V IISO = 100 mA Table 2. DC-to-DC Converter Dynamic Specifications Parameter SUPPLY CURRENT Input ADuM5401W ADuM5402W ADuM5403W Available to Load ADuM5401W ADuM5402W ADuM5403W Symbol Min 25 Mbps Typ Max Unit Test Conditions IDD1 IDD1 IDD1 68 71 75 mA mA mA No VISO load No VISO load No VISO load IISO (LOAD) IISO (LOAD) IISO (LOAD) 87 85 83 mA mA mA Calculated Calculated Calculated Unit Test Conditions Limited by maximum PWD 50% input to 50% output |tPLH − tPHL| 15 Mbps ns ns ps/°C ns ns 6 15 ns ns Table 3. Switching Specifications Parameter SWITCHING SPECIFICATIONS Data Rate Propagation Delay Pulse Width Distortion Change vs. Temperature Pulse Width Propagation Delay Skew Channel Matching Codirectional 1 Opposing Directional 2 Symbol Min tPHL, tPLH PWD 25 Mbps Typ Max 45 25 60 6 5 PW tPSK tPSKCD tPSKOD 40 1 Limited by maximum PWD Between any two units Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. 2 Opposing directional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on opposing sides of the isolation barrier. 7 Rev. 0 | Page 3 of 20 ADuM5401W/ADuM5402W/ADuM5403W Table 4. Input and Output Characteristics Parameter DC SPECIFICATIONS Logic High Input Threshold 1 Logic Low Input Threshold1 Logic High Output Voltages2 Logic Low Output Voltages2 Undervoltage Lockout Positive Going Threshold Negative Going Threshold Hysteresis Input Currents Per Channel AC SPECIFICATIONS Output Rise/Fall Time Common-Mode Transient Immunity 3 Refresh Rate Symbol Min VIH VIL VOH 0.7 VISO or 0.7 VDD1 Typ Max 0.1 0.4 V V V V V V +20 V V V μA 0.3 VISO or 0.3 VDD1 VDD1 − 0.3 or VISO − 0.3 VDD1 − 0.5 or VISO − 0.5 VOL 5.0 4.8 0.0 0.2 Unit VUV+ VUV− VUVH IIL, IIH −20 2.7 2.4 0.3 +0.01 tR/tF |CM| 25 2.5 35 ns kV/μs 1.0 Mbps fr 1 Test Conditions IOx = −20 μA, VIx = VIxH IOx = −4 mA, VIx = VIxH IOx = 20 μA, VIx = VIxL IOx = 4 mA, VIx = VIxL VDD1, VISO supply 0 V ≤ VIx ≤ VDDX or VISO 10% to 90% VIx = VDD1 or VISO, VCM = 1000 V, transient magnitude = 800 V VSEL is a nonstandard input that has a logic threshold of approximately 0.9 V. RCOUT is a nonstandard output intended to interface with other isoPower parts. It is not recommended for standard digital loads. 3 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 × VDD1 or 0.8 × VISO for a high input or VO < 0.8 × VDD1 or 0.8 × VISO for a low input. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. 2 Rev. 0 | Page 4 of 20 ADuM5401W/ADuM5402W/ADuM5403W PACKAGE CHARACTERISTICS Table 5. Thermal and Isolation Characteristics Parameter Resistance (Input to Output) 1 Capacitance (Input to Output)1 Input Capacitance 2 IC Junction to Ambient Thermal Resistance Symbol RI-O CI-O CI θJA Min Typ 1012 2.2 4.0 45 Max Unit Ω pF pF °C/W Test Conditions f = 1 MHz Thermocouple located at center of package underside, test conducted on 4-layer board with thin traces 3 1 The device is considered a 2-terminal device; Pin 1 to Pin 8 are shorted together, and Pin 9 to Pin 16 are shorted together. Input capacitance is from any input data pin to ground. 3 See the Thermal Analysis section for thermal model definitions. 2 REGULATORY APPROVALS Table 6. UL 1 Recognized under 1577 component recognition program1 Single protection, 2500 V rms isolation voltage File E214100 CSA Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage File 205078 VDE (Pending) 2 Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Reinforced insulation, 560 V peak File 2471900-4880-0001 1 In accordance with UL 1577, each ADuM5401W/ADuM5402W/ADuM5403W is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 10 μA). 2 In accordance with DIN V VDE V 0884-10, each ADuM540xW is proof tested by applying an insulation test voltage ≥1590 V peak for 1 second (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 7. Critical Safety-Related Dimensions and Material Properties Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol Value 2500 L(I01) >8.0 Unit Test Conditions/Comments V rms 1-minute duration mm Measured from input terminals to output terminals, shortest distance through air 7.7 mm Measured from input terminals to output terminals, shortest distance path along body 0.017 min mm Distance through insulation >175 V DIN IEC 112/VDE 0303, Part 1 IIIa Material group (DIN VDE 0110, 1/89, Table 1) Minimum External Tracking (Creepage) L(I02) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI Rev. 0 | Page 5 of 20 ADuM5401W/ADuM5402W/ADuM5403W DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by the protective circuits. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval. Table 8. VDE Characteristics Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method b1 Conditions VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC Input-to-Output Test Voltage, Method a After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety Limiting Values Symbol Characteristic Unit VIORM VPR I to IV I to III I to II 40/105/21 2 560 1050 V peak V peak 896 672 V peak V peak VTR 4000 V peak TS IS1 RS 150 555 >109 °C mA Ω VPR VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 sec Maximum value allowed in the event of a failure (see Figure 5) Case Temperature Side 1 IDD1 Current Insulation Resistance at TS VIO = 500 V 500 400 300 200 100 0 08758-005 SAFE OPERATING VDD1 CURRENT (mA) 600 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 Figure 5. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2 RECOMMENDED OPERATING CONDITIONS Table 9. Parameter Operating Temperature 1 Supply Voltages 2 1 2 Symbol TA VDD1 Operation at 105°C requires reduction of the maximum load current, as specified in Table 10. Each voltage is relative to its respective ground. Rev. 0 | Page 6 of 20 Min −40 4.5 Max +105 5.5 Unit °C V ADuM5401W/ADuM5402W/ADuM5403W ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Table 11. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime1 Table 10. Parameter Storage Temperature (TST) Ambient Operating Temperature Range (TA) Supply Voltages (VDD, VISO)1 VISO Supply Current2 TA = −40°C to +85°C TA = −40°C to +105°C Input Voltage (VIA, VIB, VIC, VID)1, 3 Output Voltage (RCOUT, VOA, VOB, VOC, VOD)1, 3 Average Output Current Per Data Output Pin4 Maximum Cumulative AC HiPot Maximum Cumulative DC HiPot Common-Mode Transients5 Rating −55°C to +150°C −40°C to +105°C −0.5 V to +7.0 V 100 mA 60 mA −0.5 V to VDDI + 0.5 V −0.5 V to VDDO + 0.5 V −10 mA to +10 mA 5 min @ 2500 V rms 5 min @ 3500 VDC −100 kV/μs to +100 kV/μs Max Unit 424 V peak Basic Insulation 560 V peak Unipolar Waveform Basic Insulation 560 V peak Working voltage per IEC 60950-1 560 V peak Working voltage per IEC 60950-1 DC Voltage Basic Insulation 1 All certifications, 50-year operation Working voltage per IEC 60950-1 Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information. 1 All voltages are relative to their respective grounds. The VISO provides current for dc and dynamic loads on the VISO I/O channels. This current must be included when determining the total VISO supply current. For ambient temperatures between 85°C and 105°C, maximum allowed current is reduced. 3 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PCB Layout section. 4 See Figure 5 for the maximum rated current values for various temperatures. 5 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage. Applicable Certification Parameter AC Voltage Bipolar Waveform 2 ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 20 ADuM5401W/ADuM5402W/ADuM5403W PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDD1 1 16 VISO GND1 2 15 GNDISO VIA 3 14 VOA VIC 5 ADuM5401W 13 VOB TOP VIEW (Not to Scale) 12 VOC VOD 6 11 VID RCOUT 7 10 VSEL GND1 8 9 GNDISO 08758-006 VIB 4 Figure 6. ADuM5401W Pin Configuration Table 12. ADuM5401W Pin Function Descriptions Pin No. Mnemonic Description 1 VDD1 Primary Supply Voltage, 4.5 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source. 2, 8 GND1 Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both pins be connected to a common ground. 3 VIA Logic Input A. 4 VIB Logic Input B. 5 VIC Logic Input C. 6 VOD Logic Output D. 7 RCOUT Regulation Control Output. This pin is connected to the RCIN of a slave isoPower device to allow the ADuM5401W to control the regulation of the slave device. 9, 15 GNDISO Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be connected to a common ground. 10 VSEL This pin must be connected to VISO for proper operation of the part. 11 VID Logic Input D. 12 VOC Logic Output C. 13 VOB Logic Output B. 14 VOA Logic Output A. 16 VISO Secondary Supply Voltage Output, 5.0 V for External Loads. Rev. 0 | Page 8 of 20 ADuM5401W/ADuM5402W/ADuM5403W VDD1 1 16 VISO GND1 2 15 GNDISO VIA 3 14 VOA VOC 5 ADuM5402W 13 VOB TOP VIEW (Not to Scale) 12 VIC VOD 6 11 VID RCOUT 7 10 VSEL GND1 8 9 GNDISO 08758-007 VIB 4 Figure 7. ADuM5402W Pin Configuration Table 13. ADuM5402W Pin Function Descriptions Pin No. Mnemonic Description 1 VDD1 Primary Supply Voltage, 4.5 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source. 2, 8 GND1 Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both pins be connected to a common ground. 3 VIA Logic Input A. 4 VIB Logic Input B. 5 VOC Logic Output C. 6 VOD Logic Output D. 7 RCOUT Regulation Control Output. This pin is connected to the RCIN of a slave isoPower device to allow the ADuM5401W to control the regulation of the slave device. 9, 15 GNDISO Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be connected to a common ground. 10 VSEL This pin must be connected to VISO for proper operation of the part. 11 VID Logic Input D. 12 VIC Logic Input C. 13 VOB Logic Output B. 14 VOA Logic Output A. 16 VISO Secondary Supply Voltage Output, 5.0 V for External Loads. Rev. 0 | Page 9 of 20 ADuM5401W/ADuM5402W/ADuM5403W VDD1 1 16 VISO GND1 2 15 GNDISO VIA 3 14 VOA VOC 5 ADuM5403W 13 VIB TOP VIEW (Not to Scale) 12 VIC VOD 6 11 VID RCOUT 7 10 VSEL GND1 8 9 GNDISO 08758-008 VOB 4 Figure 8. ADuM5403W Pin Configuration Table 14. ADuM5403W Pin Function Descriptions Pin No. Mnemonic Description 1 VDD1 Primary Supply Voltage, 4.5 V to 5.5 V. Pin 1 and Pin 7 must be connected to the same external voltage source. 2, 8 GND1 Ground 1. Ground reference for isolator primary. Pin 2 and Pin 8 are internally connected, and it is recommended that both pins be connected to a common ground. 3 VIA Logic Input A. 4 VOB Logic Output B. 5 VOC Logic Output C. 6 VOD Logic Output D. 7 RCOUT Regulation Control Output. This pin is connected to the RCIN of a slave isoPower device to allow the ADuM5401W to control the regulation of the slave device. 9, 15 GNDISO Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and it is recommended that both pins be connected to a common ground. 10 VSEL This pin must be connected to VISO for proper operation of the part. 11 VID Logic Input D. 12 VIC Logic Input C. 13 VIB Logic Input B. 14 VOA Logic Output A. 16 VISO Secondary Supply Voltage Output, 5.0 V for External Loads. Rev. 0 | Page 10 of 20 ADuM5401W/ADuM5402W/ADuM5403W TRUTH TABLE Table 15. Truth Table (Positive Logic) VIx Input 1 High Low 1 VDD1 State Powered Powered VDD1 Input (V) 5.0 5.0 VISO State Powered Powered VISO Output (V) 5.0 5.0 VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D). Rev. 0 | Page 11 of 20 VOx Output1 High Low Notes Normal operation, data is high Normal operation, data is low ADuM5401W/ADuM5402W/ADuM5403W TYPICAL PERFORMANCE CHARACTERISTICS 4.0 5V INPUT/5V OUTPUT 0.35 3.5 INPUT CURRENT (A) 0.30 EFFICIENCY (%) 4.0 0.25 0.20 0.15 3.5 POWER 3.0 3.0 2.5 2.5 2.0 2.0 1.5 1.5 1.0 1.0 0.10 POWER (W) 0.40 0 0 0.02 0.04 0.06 0.08 OUTPUT CURRENT (A) 0.10 0.5 0.5 08758-009 0.05 0 3.0 0.12 3.5 4.0 4.5 5.0 5.5 6.0 0 6.5 INPUT SUPPLY VOLTAGE (V) Figure 12. Typical Short-Circuit Input Current and Power vs. VDD1 Supply Voltage Figure 9. Typical Power Supply Efficiency at 5 V/5 V OUTPUT VOLTAGE (500mV/DIV) 1.0 0.9 0.7 0.6 0.5 10% LOAD 0.3 VDD1 = 5V, VISO = 5V 0 0.02 0.04 0.06 IISO (A) 0.08 0.10 08758-010 0.2 08758-013 0.4 0.1 90% LOAD DYNAMIC LOAD POWER DISSIPATION (W) 0.8 0 (100µs/DIV) 0.12 Figure 10. Typical Total Power Dissipation vs. IISO with Data Channels Idle Figure 13. Typical VISO Transient Load Response, 5 V Output, 10% to 90% Load Step OUTPUT VOLTAGE (500mV/DIV) 0.12 0.08 0.06 5V INPUT/5V OUTPUT 0 0.05 0.10 0.15 0.20 0.25 0.30 08758-011 0.02 10% LOAD 90% LOAD 08758-014 0.04 DYNAMIC LOAD OUTPUT CURRENT (A) 0.10 0 08758-012 IDD1 (100µs/DIV) 0.35 INPUT CURRENT (A) Figure 11. Typical Isolated Output Supply Current, IISO, as a Function of External Load, No Dynamic Current Draw at 5 V/5 V Rev. 0 | Page 12 of 20 Figure 14. Typical Transient Load Response, 3 V Output, 10% to 90% Load Step ADuM5401W/ADuM5402W/ADuM5403W 5V OUTPUT RIPPLE (10mV/DIV) 5 SUPPLY CURRENT (mA) 4 5 10 15 DATA RATE (Mbps) 20 25 3.0 2.5 SUPPLY CURRENT (mA) 16 12 8 4 2.0 1.5 5V 1.0 0 5 10 15 DATA RATE (Mbps) 20 0 25 20 16 12 8 08758-017 4 5V INPUT/5V OUTPUT 5 10 15 DATA RATE (Mbps) 20 0 5 10 15 DATA RATE (Mbps) 20 25 Figure 19. Typical IISO (D) Dynamic Supply Current per Output (15 pF Output Load) Figure 16. Typical ICHn Supply Current per Forward Data Channel (15 pF Output Load) 0 08758-019 08758-016 0.5 5V INPUT/5V OUTPUT 0 0 Figure 18. Typical IISO (D) Dynamic Supply Current per Input 20 0 08758-018 08758-015 0 Figure 15. Typical VISO = 5 V Output Voltage Ripple at 90% Load SUPPLY CURRENT (mA) 5V 2 1 BW = 20MHz (400ns/DIV) SUPPLY CURRENT (mA) 3 25 Figure 17. Typical ICHn Supply Current per Reverse Data Channel (15 pF Output Load) Rev. 0 | Page 13 of 20 ADuM5401W/ADuM5402W/ADuM5403W TERMINOLOGY IDD1 (Q) IDD1 (Q) is the minimum operating current drawn at the VDD1 pin when there is no external load at VISO and the I/O pins are operating below 2 Mbps, requiring no additional dynamic supply current. IDD1 (Q) reflects the minimum current operating condition. IDD1 (D) IDD1 (D) is the typical input supply current with all channels simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Resistive loads on the outputs should be treated separately from the dynamic load. IDD1 (MAX) IDD1 (MAX) is the input current under full dynamic and VISO load conditions. IISO (LOAD) IISO (LOAD) is the current available to an external VISO load. tPHL Propagation Delay tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH Propagation Delay tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. tPSK Propagation Delay Skew tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. tPSKCD/tPSKOD Channel-to-Channel Matching Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads. Minimum Pulse Width The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. Maximum Data Rate The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. Rev. 0 | Page 14 of 20 ADuM5401W/ADuM5402W/ADuM5403W APPLICATIONS INFORMATION The dc-to-dc converter section of the ADuM5401W/ADuM5402W/ ADuM5403W works on principles that are common to most modern power supplies. It is a secondary side controller architecture with isolated pulse-width modulation (PWM) feedback. VDD1 power is supplied to an oscillating circuit that switches current into a chip-scale air core transformer. Power transferred to the secondary side is rectified and regulated to 5 V. The secondary (VISO) side controller regulates the output by creating a PWM control signal that is sent to the primary (VDD1) side by a dedicated iCoupler data channel. The PWM modulates the oscillator circuit to control the power being sent to the secondary side. Feedback allows for significantly higher power and efficiency. The ADuM5401W/ADuM5402W/ADuM5403W implement undervoltage lockout (UVLO) with hysteresis on the VDD1 power input. This feature ensures that the converter does not enter oscillation due to noisy input power or slow power-on ramp rates. A minimum load current of 10 mA is recommended to ensure optimum load regulation. Smaller loads can generate excess noise on chip due to short or erratic PWM pulses. Excess noise generated this way can cause data corruption, in some circumstances. PCB LAYOUT The ADuM5401W/ADuM5402W/ADuM5403W digital isolators with 0.5 W isoPower integrated dc-to-dc converters require no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins (see Figure 20). Note that a low ESR bypass capacitor is required between Pin 1 and Pin 2 as well as between Pin 15 and Pin 16, as close to the chip pads as possible. The power supply section of the ADuM5401W/ADuM5402W/ ADuM5403W uses a 180 MHz oscillator frequency to efficiently pass power through its chip-scale transformers. In addition, normal operation of the data section of the iCoupler introduces switching transients on the power supply pins. Bypass capacitors are required for several operating frequencies. Noise suppression requires a low inductance, high frequency capacitor; ripple suppression and proper regulation require a large value capacitor. These are most conveniently connected between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VISO. To suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. The recommended capacitor values are 0.1 μF and 10 μF for VDD1 and VISO. A 10 nF capacitor should be used when optimum EMI emissions performance is desired. The smaller capacitors must have a low ESR; for example, use of an NPO ceramic capacitor is advised. Note that the total lead length between the ends of the low ESR capacitor and the input power supply pin must not exceed 2 mm. Installing the bypass capacitor with traces more than 2 mm in length may result in data corruption. A bypass between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should also be considered unless both common ground pins are connected together close to the package. BYPASS < 2mm VDD1 GND1 VIA VISO GNDISO VOA VIB/VOB VOB/VIB VIC/VOC VOC/VIC VOD RCOUT GND1 VID VSEL GNDISO 08758-020 THEORY OF OPERATION Figure 20. Recommended Printed Circuit Board Layout In applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. Furthermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins, exceeding the absolute maximum ratings specified in Table 10, thereby leading to latch-up and/or permanent damage. The ADuM5401W/ADuM5402W/ADuM5403W are power devices that dissipate about 1 W of power when fully loaded and running at maximum speed. Because it is not possible to apply a heat sink to an isolation device, the devices primarily depend on heat dissipation into the PCB through the ground pins. If the devices are used at high ambient temperatures, provide a thermal path from the ground pins to the PCB ground plane. The board layout in Figure 20 shows enlarged pads for Pin 8 and Pin 9. Large diameter vias should be implemented from the pad to the ground, and power planes should be used to reduce inductance. Multiple vias in the thermal pads can significantly reduce temperatures inside the chip. The dimensions of the expanded pads are left to the discretion of the designer and the available board space. THERMAL ANALYSIS The ADuM5401W/ADuM5402W/ADuM5403W parts consist of four internal die attached to a split lead frame with two die attach paddles. For the purposes of thermal analysis, the die is treated as a thermal unit, with the highest junction temperature reflected in the θJA from Table 5. The value of θJA is based on measurements taken with the parts mounted on a JEDEC standard, 4-layer board with fine width traces and still air. Under normal operating conditions, the ADuM5401W/ADuM5402W/ADuM5403W devices operate at full load across the full temperature range without derating the output current. However, following the recommendations in the PCB Layout section decreases thermal resistance to the PCB, allowing increased thermal margins in high ambient temperatures. Rev. 0 | Page 15 of 20 ADuM5401W/ADuM5402W/ADuM5403W PROPAGATION DELAY RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component (see Figure 21). The propagation delay to a logic low output may differ from the propagation delay to a logic high. 50% OUTPUT (VOx) tPHL 08758-021 tPLH 50% The pulses at the transformer output have an amplitude of >1.0 V. The decoder has a sensing threshold of about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (−dβ/dt)∑πrn2; n = 1, 2, … , N Figure 21. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal timing is preserved. Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM5401W/ADuM5402W/ADuM5403W component. Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM5401W/ ADuM5402W/ADuM5403W components operating under the same conditions. where: β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM5401W/ ADuM5402W/ADuM5403W, and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 22. EMI CONSIDERATIONS The dc-to-dc converter section of the ADuM5401W/ ADuM5402W/ADuM5403W components must, of necessity, operate at a very high frequency to allow efficient power transfer through the small transformers. This creates high frequency currents that can propagate in circuit board ground and power planes, causing edge and dipole radiation. Grounded enclosures are recommended for applications that use these devices. If grounded enclosures are not possible, follow good RF design practices in the layout of the PCB. See www.analog.com for the most current PCB layout recommendations specifically for the ADuM5401W/ADuM5402W/ADuM5403W. DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than 1 μs, periodic sets of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than approximately 5 μs, the input side is assumed to be not powered or nonfunctional, in which case, the isolator output is forced to a default high state by the watchdog timer circuit. This situation should only occur during power-up and power-down operations. MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kGauss) 100 10 1 0.1 0.01 0.001 1k 08758-022 INPUT (VIx) The limitation on the ADuM5401W/ADuM5402W/ADuM5403W magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. 10k 1M 10M 100k MAGNETIC FIELD FREQUENCY (Hz) 100M Figure 22. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V, which is still well above the 0.5 V sensing threshold of the decoder. Rev. 0 | Page 16 of 20 ADuM5401W/ADuM5402W/ADuM5403W The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM5401W/ ADuM5402W/ADuM5403W transformers. Figure 23 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown in Figure 23, the ADuM5401W/ ADuM5402W/ADuM5403W are extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example, a 0.5 kA current placed 5 mm away from the ADuM5401W/ADuM5402W/ ADuM5403W is required to affect component operation. Dynamic I/O current is consumed only when operating a channel at speeds higher than the refresh rate of fr. The dynamic current of each channel is determined by its data rate. Figure 16 shows the current for a channel in the forward direction, meaning that the input is on the VDD1 side of the part. Figure 17 shows the current for a channel in the reverse direction, meaning that the input is on the VISO side of the part. Both figures assume a typical 15 pF load. The following relationship allows the total IDD1 current to be calculated: IDD1 = (IISO × VISO)/(E × VDD1) + Σ ICHn; n = 1 to 4 100 10 DISTANCE = 100mm 1 DISTANCE = 5mm The maximum external load can be calculated by subtracting the dynamic output load from the maximum allowable load. 0.1 0.01 1k 10k 100k IISO (LOAD) = IISO (MAX) − Σ IISO (D)n; n = 1 to 4 1M 10M 100M MAGNETIC FIELD FREQUENCY (Hz) Figure 23. Maximum Allowable Current for Various Current-to-ADuM5401W/ADuM5402W/ADuM5403W Spacings Note that, in combinations of strong magnetic field and high frequency, any loops formed by PCB traces can induce error voltages sufficiently large to trigger the thresholds of succeeding circuitry. Exercise care in the layout of such traces to avoid this possibility. POWER CONSUMPTION The VDD1 power supply input provides power to the iCoupler data channels, as well as to the power converter. For this reason, the quiescent currents drawn by the power converter and the primary and secondary I/O channels cannot be determined separately. All of these quiescent power demands have been combined into the IDD1 (Q) current, as shown in Figure 24. The total IDD1 supply current is equal to the sum of the quiescent operating current; the dynamic current, IDD1 (D), demanded by the I/O channels; and any external IISO load. IDD1(Q) CONVERTER PRIMARY IDDP(D) PRIMARY DATA INPUT/OUTPUT 4-CHANNEL The preceding analysis assumes a 15 pF capacitive load on each data output. If the capacitive load is larger than 15 pF, the additional current must be included in the analysis of IDD1 and IISO (LOAD). POWER CONSIDERATIONS The ADuM5401W/ADuM5402W/ADuM5403W power input, data input channels on the primary side, and data channels on the secondary side are all protected from premature operation by UVLO circuitry. Below the minimum operating voltage, the power converter holds its oscillator inactive and all input channel drivers and refresh circuits are idle. Outputs remain in a high impedance state to prevent transmission of undefined states during power-up and power-down operations. During application of power to VDD1, the primary side circuitry is held idle until the UVLO preset voltage is reached. At that time, the data channels initialize to their default low output state until they receive data pulses from the secondary side. IISO E (2) where: IISO (LOAD) is the current available to supply an external secondary side load. IISO (MAX) is the maximum external secondary side load current available at VISO. IISO (D)n is the dynamic load current drawn from VISO by an input or output channel, as shown in Figure 18 and Figure 19. CONVERTER SECONDARY IISO(D) SECONDARY DATA INPUT/OUTPUT 4-CHANNEL 08758-024 IDD1(D) (1) where: IDD1 is the total supply input current. ICHn is the current drawn by a single channel determined from Figure 16 or Figure 17, depending on channel direction. IISO is the current drawn by the secondary side external load. E is the power supply efficiency at 100 mA load from Figure 9 at the VISO and VDD1 condition of interest. DISTANCE = 1m 08758-023 MAXIMUM ALLOWABLE CURRENT (kA) 1k Figure 24. Power Consumption Within the ADuM5401W/ADuM5402W/ADuM5403W Rev. 0 | Page 17 of 20 ADuM5401W/ADuM5402W/ADuM5403W When the primary side is above the UVLO threshold, the data input channels sample their inputs and begin sending encoded pulses to the inactive secondary output channels. The outputs on the primary side remain in their default low state because no data comes from the secondary side inputs until secondary power is established. The primary side oscillator also begins to operate, transferring power to the secondary power circuits. The secondary VISO voltage is below its UVLO limit at this point; the regulation control signal from the secondary is not being generated. The primary side power oscillator is allowed to free run in this circumstance, supplying the maximum amount of power to the secondary, until the secondary voltage rises to its regulation setpoint. This creates a large inrush current transient at VDD1. When the regulation point is reached, the regulation control circuit produces the regulation control signal that modulates the oscillator on the primary side. The VDD1 current is reduced and is then proportional to the load current. The inrush current is less than the short-circuit current shown in Figure 12. The duration of the inrush depends on the VISO loading conditions and the current available at the VDD1 pin. Accelerated life testing is performed using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined, allowing calculation of the time to failure at the working voltage of interest. The values shown in Table 11 summarize the peak voltages for 50 years of service life in several operating conditions. In many cases, the working voltage approved by agency testing is higher than the 50-year service life voltage. Operation at working voltages higher than the service life voltage listed leads to premature insulation failure. As the secondary side converter begins to accept power from the primary, the VISO voltage starts to rise. When the secondary side UVLO is reached, the secondary side outputs are initialized to their default low state until data is received from the corresponding primary side input. It can take up to 1 μs after the secondary side is initialized for the state of the output to correlate with the primary side input. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 11 can be applied while maintaining the 50-year minimum lifetime, provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross-insulation voltage waveform that does not conform to Figure 26 or Figure 27 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 11. Bipolar ac voltage is the most stringent environment. A 50-year operating lifetime under the bipolar ac condition determines the Analog Devices recommended maximum working voltage. When power is removed from VDD1, the primary side converter and coupler shut down when the UVLO level is reached. The secondary side stops receiving power and starts to discharge. The outputs on the secondary side hold the last state that they received from the primary side. Either the UVLO level is reached and the outputs are placed in their high impedance state, or the outputs detect a lack of activity from the primary side inputs and the outputs are set to their default low value before the secondary power reaches UVLO. RATED PEAK VOLTAGE 08758-025 Because the rate of charge of the secondary side power supply is dependent on loading conditions, the input voltage, and the output voltage level selected, take care with the design to allow the converter sufficient time to stabilize before valid data is required. 0V Figure 25. Bipolar AC Waveform RATED PEAK VOLTAGE 08758-026 Secondary side inputs sample their state and transmit it to the primary side. Outputs are valid about 1 μs after the secondary side becomes active. The insulation lifetime of the ADuM5401W/ADuM5402W/ ADuM5403W depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates, depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 25, Figure 26, and Figure 27 illustrate these different isolation voltage waveforms. 0V Figure 26. DC Waveform RATED PEAK VOLTAGE All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. Analog Devices conducts an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM5401W/ADuM5402W/ ADuM5403W. Rev. 0 | Page 18 of 20 NOTES 1. THE VOLTAGE IS SHOWN AS SINUSOIDAL FOR ILLUSTRATION PURPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLTAGE WAVEFORM VARYING BETWEEN 0 AND SOME LIMITING VALUE. THE LIMITING VALUE CAN BE POSITIVE OR NEGATIVE, BUT THE VOLTAGE CANNOT CROSS 0V. Figure 27. Unipolar AC Waveform 08758-027 0V INSULATION LIFETIME ADuM5401W/ADuM5402W/ADuM5403W VISO STARTUP ISSUES Solution An issue with reliable startup has been identified in the ADuM5401W/5402W/5403W components. It is related to initialization of the band gap voltage references on the primary (power input) and secondary (power output) sides of the isoPower device and are being addressed in future revisions of the silicon. For current versions of the silicon, the user must follow these design guidelines to guarantee proper operation of the device. The slew rate of VISO is determined by the resistive and capacitive load present on the output. Designs that attempt to reduce ripple by adding capacitance to the VISO output can slow the slew rate enough to see startup errors. Choose values for bulk capacitance based on the effective dc load. Calculate the dc load as the resistive equivalent to the current drawn from the VISO line. Determine the range of allowable capacitance for the VISO output from Figure 28. Choose the bulk capacitance for VISO to achieve the applications required ripple, unless the value is in the disallowed combinations area, then the value has to be reduced to avoid restart issues. The band gap voltage references are vulnerable to slow powerup slew rate. The susceptibility to power-up errors is process sensitive so not all devices display these behaviors. These recommendations should be implemented for all designs until the corrections are made to the silicon. The symptoms and corrective actions required for issues with the primary and secondary side startup are different. 100k 10k DISALLOWED COMBINATIONS 1k 100 10 1 08758-028 The VISO output voltage restarts to an incorrect voltage between 3.4 V and 4.7 V when power is removed at VDD1 and then reapplied between 250 ms and 3 sec later. The error only occurs on restart, it does not occur at initial power-up. If the part initializes incorrectly, power must be remove for an extended time to allow internal nodes to discharge and reset. The amount of time required can be several minutes at low temperature; therefore, it is critical to avoid allowing the device to initialize improperly. RVISO (Ω) Symptom 1 10 100 CVISO (µF) Cause The secondary side band gap reference does not initialize to the proper voltage due to a slow slew rate on VISO after the internal nodes are precharged during the previous power cycle. The secondary side band gap sets the output voltage of the regulator. Rev. 0 | Page 19 of 20 Figure 28. Maximum Capacitive Load for Proper Restart 1k ADuM5401W/ADuM5402W/ADuM5403W OUTLINE DIMENSIONS 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 45° 8° 0° 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 032707-B 1 Figure 29. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches) ORDERING GUIDE Model 1, 2 ADuM5401WCRWZ ADuM5402WCRWZ ADuM5403WCRWZ 1 2 Number of Inputs, VDD1 Side 3 2 1 Number of Inputs, VISO Side 1 2 3 Maximum Data Rate (Mbps) 25 25 25 Maximum Propagation Delay, 5 V (ns) 60 60 60 Maximum Pulse Width Distortion (ns) 6 6 6 Z = RoHS Compliant Part. Tape and reel are available. The addition of an RL suffix designates a 13” (1,000 units) tape and reel option. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08758-0-1/10(0) Rev. 0 | Page 20 of 20 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W Package Option RW-16 RW-16 RW-16