Revised July 1999 74F175 Quad D-Type Flip-Flop General Description Features The 74F175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, LOW. ■ Edge-triggered D-type inputs ■ Buffered positive edge-triggered clock ■ Asynchronous common reset ■ True and complement output Ordering Code: Order Number Package Number Package Description 74F175SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74F175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74F175PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009490 www.fairchildsemi.com 74F175 Quad D-Type Flip-Flop April 1988 74F175 Unit Loading/Fan Out Pin Names U.L. Input IIH/IIL Description HIGH/LOW Output IOH/IOL D0–D3 Data Inputs 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA MR Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA Q0–Q3 True Outputs 50/33.3 −1 mA/20 mA Q0–Q3 Complement Outputs 50/33.3 −1 mA/20 mA Truth Table Functional Description The 74F175 consists of four edge-triggered D-type flipflops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOWto-HIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The 74F175 is useful for general logic applications where a common Master Reset and Clock are acceptable. Inputs MR CP L H H X Outputs Dn Qn Qn X L H H H L L L H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Clock Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output twice the rated IOL (mA) in LOW State (Max) DC Electrical Characteristics Symbol Parameter Min Typ Max VCC VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min VOH Output HIGH V Min 0.5 V Min IOL = 20 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V −150 mA Max VOUT = 0V 34.0 mA Max VOL Output LOW 10% VCC 2.5 5% VCC 2.7 V Conditions Input HIGH Voltage Voltage 2.0 Units VIH 10% VCC Voltage IIH Input HIGH Current IBVI Input HIGH Current Breakdown Test ICEX Output HIGH Leakage Current VID Input Leakage Test IOD 4.75 Output Leakage Circuit Current IIL Input LOW Current IOS Output Short-Circuit Current ICC Power Supply Current −60 22.5 Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA IOH = −1 mA IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded CP = Dn = MR = HIGH 3 www.fairchildsemi.com 74F175 Absolute Maximum Ratings(Note 1) 74F175 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Clock Frequency 100 140 tPLH Propagation Delay 4.0 5.0 6.5 3.5 8.5 4.0 7.5 tPHL CP to Qn or Qn 4.0 6.5 8.5 4.0 10.5 4.0 9.5 tPHL Propagation Delay 4.5 9.0 11.5 4.5 15.0 4.5 13.0 ns 4.0 6.5 8.0 4.0 10.0 4.0 9.0 ns MR to Qn tPLH Propagation Delay MR to Qn Max Min Max 80 Min Units Max 100 MHz ns AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°C to +125°C VCC = +5.0V VCC = +5.0V Min Max Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 3.0 3.0 3.0 tS(L) Dn to CP 3.0 3.0 3.0 tH(H) Hold Time, HIGH or LOW 1.0 1.0 1.0 Units Max ns tH(L) Dn to CP 1.0 2.0 1.0 tW(H) CP Pulse Width 4.0 4.0 4.0 tW(L) HIGH or LOW 5.0 5.0 5.0 tW(L) MR Pulse Width, LOW 5.0 5.0 5.0 ns tREC Recovery Time, MR to CP 5.0 5.0 5.0 ns www.fairchildsemi.com 4 ns 74F175 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D 5 www.fairchildsemi.com 74F175 Quad D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6