LTC1645 Dual-Channel Hot Swap Controller/Power Sequencer U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO Allows Safe Board Insertion and Removal from a Live Backplane Programmable Power Supply Sequencing Programmable Electronic Circuit Breaker User-Programmable Supply Voltage Power-Up and Power-Down Rate High Side Drivers for External N-Channel FETs Controls Supply Voltages from 1.2V to 12V Ensures Proper Power-Up Behavior Undervoltage Lockout Glitch Filter Protects Against Spurious RESET Signals U APPLICATIO S ■ ■ ■ Hot Board Insertion Power Supply Sequencing Electronic Circuit Breaker The LTC®1645 is a 2-channel Hot SwapTM controller that allows a board to be safely inserted and removed from a live backplane. Using external N-channel pass transistors, the supply voltages can be ramped at a programmable rate. Two high side switch drivers control the N-channel gates for supply voltages ranging from 1.2V to 12V. The two channels can be set to ramp up and down separately, or they can be programmed to rise and fall simultaneously, ensuring power supply tracking at the two outputs. Programmable electronic circuit breakers protect against shorts at either output. The RESET output can be used to generate a system reset when a supply voltage falls below a user-programmed voltage. An additional spare comparator is available for monitoring a second supply voltage. The LTC1645 is available in the 8- and 14-pin SO packages. , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. U TYPICAL APPLICATIO 5V and 3.3V Hot Swap 5V and 3.3V Hot Swap Waveforms VOUT2 3.3V 5A 0.005Ω* IRF7413 VIN2 + CLOAD2 0.005Ω* VOUT1 5V 5A IRF7413 VIN1 + CLOAD1 10Ω ON CONNECTOR 1 CONNECTOR 2 10Ω 0.01µF 25V 0.01µF 25V 7 6 SENSE1 GATE1 8 5 1 2 3 GATEn 10V/DIV VOUT2 5V/DIV VCC2 SENSE2 GATE2 VCC1 ON ON 5V/DIV VOUT1 5V/DIV LTC1645 (8-LEAD) 10k GND 1645 TA01 4 GND BACKPLANE PLUG-IN CARD *LRF1206-01-R005-J (IRC) 1 LTC1645 W W W AXI U U ABSOLUTE RATI GS (Note 1) Supply Voltage (VCC1, VCC2) ................................. 13.2V Input Voltage FB, ON, COMP + ..................... – 0.3V to (VCC1 + 0.3V) TIMER ................................................. – 0.3V to 2.5V SENSE1 ..................... (VCC1 – 0.7V) to (VCC1 + 0.3V) SENSE2 ...................... (VCC1 – 0.7V) to (VCC2 + 0.3V) Output Voltage RESET, COMPOUT, FAULT .....................– 0.3V to 16V GATE1, GATE2 ................. Internally Limited (Note 3) Output Current GATE1, GATE2 ............................................... ±20mA Operating Temperature Range LTC1645C ............................................... 0°C to 70°C LTC1645I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C U U W PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW VCC2 1 8 VCC1 SENSE2 2 7 SENSE1 GATE2 3 6 GATE1 GND 4 5 ON LTC1645CS8 LTC1645IS8 S8 PART MARKING S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 125°C, θJA = 150°C/ W 1645 1645I ORDER PART NUMBER TOP VIEW VCC2 1 14 VCC1 SENSE2 2 13 SENSE1 GATE2 3 12 GATE1 FAULT 4 11 TIMER RESET 5 10 ON FB 6 9 COMPOUT GND 7 8 COMP + LTC1645CS LTC1645IS S PACKAGE 14-LEAD PLASTIC SO TJMAX = 125°C, θJA = 110°C/ W Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. 2.375V ≤ VCC1 ≤ 12V, 1.2V ≤ VCC2 ≤ 12V unless otherwise noted (Note 2). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS DC Characteristics ICC1 VCC1 Supply Current ON = VCC1 = 5V, VCC2 = 3.3V ● 1.1 2.0 mA ICC2 VCC2 Supply Current ON = VCC1 = 5V, VCC2 = 3.3V ● 0.28 0.4 mA VLKO1 VCC1 Undervoltage Lockout High to Low ● 2.16 2.23 2.3 V VLKO2 VCC2 Undervoltage Lockout High to Low ● 1.06 1.12 1.18 V VLKHn VCCn Undervoltage Lockout Hysteresis VFB FB Pin Voltage Threshold High to Low ● ∆VFB FB Pin Threshold Line Regulation High to Low, VCC1 = 2.375V to 12V ● VFBHST FB Pin Voltage Threshold Hysteresis VCOMP COMP + ∆VCOMP COMP + Pin Threshold Line Regulation VCOMPHST COMP + Pin Voltage Threshold Hysteresis 2 Pin Voltage Threshold 25 1.226 mV 1.238 1.250 1 4 5 High to Low ● High to Low, VCC1 = 2.375V to 12V ● 1.226 mV 1.238 1.250 1 4 5 V mV V mV mV LTC1645 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. 2.375V ≤ VCC1 ≤ 12V, 1.2V ≤ VCC2 ≤ 12V unless otherwise noted (Note 2). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 1.212 1.230 1.248 1 9 mV VTM TIMER Pin Voltage Threshold ∆VTM TIMER Pin Threshold Line Regulation VCC1 = 2.375V to 12V ● ITM TIMER Pin Current Timer On, VTIMER = 0.6V, VCC1 = 5V Timer Off, VTIMER = 1.5V ● – 2.3 –2 12 – 1.7 µA mA VCB1 Circuit Breaker Trip Voltage 1 VCB1 = (VCC1 – VSENSE1) ● 46 50 56 mV VCB2 Circuit Breaker Trip Voltage 2 VCB2 = (VCC2 – VSENSE2) ● 46 50 56 mV t CBDn Circuit Breaker Trip Delay VCBn = (VCCn – VSENSEn) > 60mV ICP GATEn Pin Output Current ON = 2.2V, VGATEn = VCCn, VCC1 = 5V, VCC2 = 3.3V ON = 0.7V, VGATEn = VCCn, VCC1 = 5V, VCC2 = 3.3V ON = 0.3V, VGATEn = VCCn, VCC1 = 5V, VCC2 = 3.3V ● ● – 12.5 30 – 10 40 12 – 7.5 50 µA µA mA ∆VGATEn External N-Channel Gate Drive ∆VGATEn = (VGATEn – VCCn) ● 4.5 VONFPD ON Pin Fast Pull-Down Threshold Low to High High to Low, Fast Pull-Down Engaged ● ● 0.375 0.35 VON1 ON Pin Threshold #1 Low to High, GATE1 Turns On High to Low, GATE1 Turns Off ● ● VON2 ON Pin Threshold #2 Low to High, GATE2 Turns On High to Low, GATE2 Turns Off ● ● VONHYST ON Pin Hysteresis ION ON Pin Input Current VCC1 = 5V, VCC2 = 3.3V ● ±0.01 ±2 µA VOL Output Low Voltage RESET, FAULT, COMPOUT, IOUT = 1.6mA, VCC1 = 5V ● 0.16 0.4 V ● V µs 1.5 16 V 0.4 0.375 0.425 0.4 V V 0.8 0.775 0.825 0.8 0.85 0.825 V V 2 1.975 2.025 2 2.050 2.025 V V 25 mV Note 3: An internal zener on the GATEn pins clamps the charge pump voltage to a typical maximum operating voltage of 22V. External overdrive of a GATE pin (for example, from capacitive coupling of VCCn glitches) beyond the internal zener voltage may damage the device. If a lower GATEn pin clamp voltage is desired, use an external zener diode. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. U W TYPICAL PERFOR A CE CHARACTERISTICS VCC1 Supply Current vs Voltage VCC2 Supply Current vs Voltage 3.5 TA = 25°C 2.5 ICC2 (mA) ICC1 (mA) 2.0 1.5 VCC2 = 1.5V 1.0 TA = 25°C 3.0 1.2 2.5 1.0 2.0 VCC1 = 2.375V 1.5 1.0 VCC2 = 12V 0 4 5 6 7 8 VCC1 (V) 9 10 11 12 1645 G01 ICC1 0.8 0.6 0.4 ICC2 0.2 0.5 3 VCC1 = 5V VCC2 = 3.3V VCC1 = 12V 0.5 2 Supply Current vs Temperature 1.4 ICCn (mA) 3.0 0 1 2 3 4 5 7 8 VCC2 (V) 6 9 10 11 12 1645 G02 0 –40 –20 40 20 60 0 TEMPERATURE (°C) 80 100 1645 G03 3 LTC1645 U W TYPICAL PERFOR A CE CHARACTERISTICS GATE Voltage vs Supply Voltage Glitch Filter Time vs Feedback Transient GATE Voltage vs Temperature 16.0 25 100 VCC1 = 5V 15.8 VCC2 = 3.3V TA = 25°C GLITCH FILTER TIME (µs) 15.6 20 GATEn (V) GATEn (V) 15.4 15 10 15.2 15.0 14.8 14.6 70 60 50 40 30 14.4 20 14.2 10 0 14.0 –40 – 20 4 3 5 6 7 8 9 HIGHEST VCC (V) 10 11 12 0 40 20 0 60 TEMPERATURE (°C) 800 VCC1 = 5V 400 OUTPUT VOLTAGE (mV) 250 200 150 SINK CURRENT = 1.6mA 100 500 SINK CURRENT = 3mA 400 300 200 SINK CURRENT = 1.6mA –20 0 20 40 60 TEMPERATURE (°C) 80 100 80 120 160 200 240 FEEDBACK TRANSIENT (mV) 2 3 4 5 6 7 8 VCC1 (V) 280 Fast Pull-Down Current vs VCC1 18 TA = 25°C 17 VCC2 = 1.5V 16 15 14 13 12 11 10 9 0 1645 G07 4 600 100 50 40 1645 G06 FAST PULL-DOWN CURRENT (mA) SINK CURRENT = 3mA 300 0 TA = 25°C 700 350 0 –40 100 RESET, FAULT, COMPOUT Output Voltage vs VCC1 RESET, FAULT, COMPOUT Output Voltage vs Temperature 450 80 1645 G05 1645 G04 OUTPUT VOLTAGE (mV) 80 5 2 TA = 25°C 90 9 10 11 12 1645 G08 8 2 3 4 5 6 7 8 VCC1 (V) 9 10 11 12 1645 G09 LTC1645 U U U PI FU CTIO S (14-Lead Package/8-Lead Package) VCC2 (Pin 1/Pin 1): Positive Supply Input. VCC2 can range from 1.2V to 12V for normal operation. ICC2 is typically 0.2mA. An undervoltage lockout circuit disables the LTC1645 whenever the voltage at VCC2 is less than 1.12V. SENSE2 (Pin 2/Pin 2): VCC2 Circuit Breaker Set Pin. With a sense resistor placed in the supply path between VCC2 and SENSE2, the circuit breaker trips when the voltage across the resistor exceeds 50mV for more than 1.5µs. If the circuit breaker trip current is set to twice the normal operating current, only 25mV is dropped across the sense resistor during normal operation. To disable the circuit breaker, short VCC2 and SENSE2 together. GATE2 (Pin 3/Pin 3): Channel 2 High Side Gate Drive. Connect to the gate of an external N-channel MOSFET. An internal charge pump guarantees at least 4.5V of gate drive. The charge pump is powered by the higher of VCC1 and VCC2. When the ON pin exceeds 2V, GATE2 is turned on by connecting a 10µA current source from the charge pump output to the GATE2 pin and the voltage starts to ramp up with a slope dv/dt = 10µA/CGATE2. While the ON pin is below 2V but above 0.4V, a 40µA current source pulls GATE2 toward ground. If the ON pin is below 0.4V, the circuit breaker trips or the undervoltage lockout circuit trips, the GATE2 pin is immediately pulled to ground with a 12mA (typ) current source. FAULT (Pin 4/NA): Circuit Breaker Fault. FAULT is an open-drain output that pulls low when the circuit breaker function trips. The circuit breaker is reset by pulling the ON pin below 0.4V. An external pull-up is required to generate a logic high at the FAULT pin. When the ON pin is low, FAULT will release. The circuit breaker can be programmed to automatically reset by connecting the FAULT pin to the ON pin. In this circuit configuration, if a logic device is driving the ON pin, use a series resistor between the logic output and the ON pin to prevent large currents from flowing. RESET (Pin 5/NA): Open-Drain RESET Output. The RESET pin is pulled low when the voltage at the FB pin goes below 1.238V or VCC1 is below the undervoltage lockout threshold. The RESET pin goes high one timing cycle after the voltage at the FB pin goes above the FB pin threshold. The ON pin must remain above 0.8V during this timing cycle. An external pull-up is required to generate a logic high at the RESET pin. FB (Pin 6/NA): RESET Comparator Input. The FB pin is used to monitor the output supply voltage with an external resistive divider. When the voltage on the FB pin is lower than 1.238V, the RESET pin is pulled low. A glitch filter on the FB pin prevents fast transients from forcing RESET low. When the voltage on the FB pin rises above the trip point, the RESET pin goes high after one timing cycle. GND (Pin 7/Pin 4): Ground. Connect to a ground plane for optimum performance. COMP+ (Pin 8/NA): Spare Comparator Noninverting Input. When the voltage on COMP+ is lower than 1.238V, COMPOUT pulls low. COMPOUT (Pin 9/NA): Open-Drain Spare Comparator Output. COMPOUT pulls low when the voltage on COMP+ is below 1.238V or VCC1 is below the undervoltage lockout threshold. An external pull-up is required to generate a logic high at the COMPOUT pin. ON (Pin 10/Pin 5): Analog Control Input. If the ON pin voltage is below 0.4V, both GATE1 and GATE2 are immediately pulled to ground. While the voltage is between 0.4V and 0.8V, both GATE1 and GATE2 are each pulled to ground with a 40µA current source. While the voltage is between 0.8V and 2V, the GATE1 pull-up is turned on after one timing cycle, but GATE2 continues to be pulled to ground with a 40µA current source. When the voltage exceeds 2V, both the GATE1 and GATE2 pull-ups are turned on one timing cycle after the voltage exceeds 0.8V. The ON pin is also used to reset the electronic circuit breaker. If the ON pin is brought below and then above 0.4V following the trip of the circuit breaker, the circuit breaker resets, and a normal power-up sequence occurs. TIMER: (Pin 11/NA): System Timing Pin. The TIMER pin requires an external capacitor to ground to generate a timing delay. The pin is used to set the delay before the RESET pin goes high after the output supply voltage is good as sensed by the FB pin. It is also used to set the delay between the ON pin exceeding 0.8V and the GATE1 and GATE2 pins turning on (GATE2 turns on only if the ON pin exceeds 2V). 5 LTC1645 U U U PI FU CTIO S (14-Lead Package/8-Lead Package) the circuit breaker trips or the undervoltage lockout circuit trips, the GATE1 pin is immediately pulled to ground with a 12mA (typ) current source. Whenever the timer is inactive, an internal N-channel FET shorts the TIMER pin to ground. Activating the timer connects a 2µA current source from VCC1 to the TIMER pin and the voltage starts to ramp up with a slope dv/dt = 2µA/ CTIMER. When the voltage reaches the trip point (1.23V), the timer is reset by pulling the TIMER pin back to ground. The timer period is (1.23V • CTIMER)/2µA. SENSE1 (Pin 13/Pin 7): VCC1 Circuit Breaker Set Pin. With a sense resistor placed in the supply path between VCC1 and SENSE1, the circuit breaker trips when the voltage across the resistor exceeds 50mV for more than 1.5µs. If the circuit breaker trip current is set to twice the normal operating current, only 25mV is dropped across the sense resistor during normal operation. To disable the circuit breaker, short VCC1 and SENSE1 together. GATE1 (Pin 12/Pin 6): Channel 1 High Side Gate Drive. Connect to the gate of an external N-channel MOSFET. An internal charge pump guarantees at least 4.5V of gate drive. The charge pump is powered by the higher of VCC1 and VCC2. When the ON pin exceeds 0.8V, GATE1 is turned on by connecting a 10µA current source from the charge pump output to the GATE1 pin and the voltage starts to ramp up with a slope dv/dt = 10µA/CGATE1. While the ON pin is below 0.8V but above 0.4V, a 40µA current source pulls GATE1 toward ground. If the ON pin is below 0.4V, VCC1 (Pin 14/Pin 8): Positive Supply Input. VCC1 can range from 2.375V to 12V for normal operation. ICC1 is typically 1mA. An undervoltage lockout circuit disables the chip whenever the voltage at VCC1 is less than 2.23V. All internal logic is powered by VCC1. W BLOCK DIAGRA VCC1 SENSE1 VCC2 SENSE2 14 13 1 2 – + + – + 50mV + – 2V – 2.23V UVL 1.5µs FILTER 1.12V UVL 12 3 50mV – + ON 10 GATE1 GATE2 1.5µs FILTER 4× CHARGE PUMP + 0.8V – + 0.4V LOGIC 1.238V REFERENCE REF – GLITCH FILTER 2µA – + + TIMER 11 REF FB 5 RESET 7 GND 8 COMP+ 9 COMPOUT – – + FAULT 4 6 REF 1645 BD 6 LTC1645 U W U U APPLICATIO S I FOR ATIO Hot Circuit Insertion Power Supply Tracking and Sequencing When a circuit board is inserted into a live backplane, the supply bypass capacitors on the board can draw huge transient currents from the backplane power bus as they charge. These transient currents can cause permanent damage to the connector pins and produce glitches on the system supply, resetting other boards in the system. Some applications require that the potential difference between two power supplies not exceed a certain voltage. This requirement applies during power-up and powerdown as well as during steady state operation, often to prevent latch-up in a dual supply ASIC. Other systems require one supply to come up after another, for example, if a system clock needs to start before a block of logic. Typical dual supplies or backplane connections may come up at arbitrary rates depending on load current, capacitor size, soft-start rates, etc. Traditional solutions are cumbersome and require complex circuitry to meet the power supply requirements. The LTC1645 is designed to turn a board’s supply voltages on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The chip provides a system reset signal and a spare comparator to indicate when board supply voltages drop below userprogrammable voltages, and a fault signal to indicate if an overcurrent condition has occurred. The LTC1645 provides a simple solution to power supply tracking and sequencing needs. The LTC1645 guarantees supply tracking by ramping the supplies up and down together (see Figure 15). The sequencing capabilities of the LTC1645 allow nearly any combination of supply ramping (e.g., see Figure 17) to satisfy various sequencing specifications. See the Power Supply Tracking and Sequencing Applications section for more information. The LTC1645 can be located before or after the connector as shown in Figure 1. A staggered PCB connector can sequence pin connections when plugging and unplugging circuit boards. Alternatively, the control signal can be generated by processor control. BACKPLANE CONNECTOR STAGGERED PCB EDGE CONNECTOR VCC + VCC ON SENSE VOUT CLOAD GATE ON FAULT FAULT LTC1645 GND (a) Hot Swap Controller on Motherboard BACKPLANE CONNECTOR STAGGERED PCB EDGE CONNECTOR VCC + VOUT CLOAD FAULT VCC SENSE GATE ON FAULT LTC1645 GND 1645 F01 (b) Hot Swap Controller on Daughterboard Figure 1. Staggered Pins Connection 7 LTC1645 U W U U APPLICATIO S I FOR ATIO Power Supply Ramping The power supplies on a board are controlled by placing external N-channel pass transistors in the power paths as shown in Figure 2. Consult Table 1 for a selection of N-channel FETs suitable for use with the LTC1645. RSENSE1 and RSENSE2 provide current fault detection and R1 and R2 prevent high frequency oscillation. By ramping the gates of the pass transistors up and down at a controlled rate, the transient surge current (I = C • dv/dt) drawn from the main backplane supply is limited to a safe value when the board makes connection. When power is first applied to the chip, the gates of the N-channels (GATE1 and GATE2 pins) are pulled low. After the ON pin is held above 0.8V for at least one timing cycle, the voltage at GATE1 begins to rise with a slope equal to dv/dt = 10µA/C1 (Figure 3), where C1 is the external capacitor connected between the GATE1 pin and GND. If the ON pin is brought above 2V (and the ON pin has been held above 0.8V for at least one timing cycle), the voltage at GATE2 begins to rise with a slope equal to dv/dt = 10µA/C2. RSENSE1 Q1 VCC1 + VOUT1 The ramp time for each supply is t = (VCCn • Cn)/10µA. If the ON pin is pulled below 2V for GATE2 or 0.8V for GATE1 (but above 0.4V), a 40µA current source is connected from GATEn to GND, and the voltage at the GATEn pin will ramp down, as shown in Figure 4. Ringing Good engineering practice calls for bypassing the supply rail of any circuit. Bypass capacitors are often placed at the supply connection of every active device, in addition to one or more large value bulk bypass capacitors per supply rail. If power is connected abruptly, the bypass capacitors slow the rate of rise of voltage and heavily damp any parasitic resonance of lead or trace inductance working against the supply bypass capacitors. The opposite is true for LTC1645 Hot Swap circuits on a daughterboard. In most cases, on the powered side of the N-channel FET switches (VCCn) there is no supply bypass capacitor present. An abrupt connection, produced by plugging a board into a backplane connector, results in a fast rising edge applied to the VCCn line of the LTC1645. VCCn + ∆VGATE GATEn CLOAD1 R1 10Ω SLOPE = 10µA/Cn C1 RSENSE2 Q2 VCC2 + VOUT2 VOUTn VCCn CLOAD2 R2 10Ω 14 13 1 12 VCC1 SENSE1 GATE1 VCC2 SENSE2 GATE2 4 ON LTC1645 (14-LEAD) COMPOUT FAULT FB t2 Figure 3. Supply Turning On C2 3 2 COMP+ 10 t1 8 VCCn + ∆VGATE 9 GATEn 6 SLOPE = 40µA/Cn 5 TIMER 11 CTIMER GND RESET VCCn 7 VOUTn 1645 F02 t3 Figure 2. Typical Hot Swap Connection 8 t4 1645 F04 Figure 4. Supply Turning Off 1645 F03 LTC1645 U W U U APPLICATIO S I FOR ATIO No bulk capacitance is present to slow the rate of rise and heavily damp the parasitic resonance. Instead, the fast edge shock excites a resonant circuit formed by a combination of wiring harness, backplane and circuit board parasitic inductances and FET capacitance. In theory, the peak voltage should rise to 2X the input supply, but in practice the peak can reach 2.5X, owing to the effects of voltage dependent FET capacitance. The absolute maximum VCCn potential for the LTC1645 is 13.2V; any circuit with an input of 5V or greater should be scrutinized for ringing. A well-bypassed backplane should not escape suspicion: circuit board trace inductances of as little as 10nH can produce sufficient ringing to overvoltage VCC. Check ringing with a fast storage oscilloscope (such as a LECROY 9314AL DSO) by attaching coax or a probe to VCC and GND, then repeatedly inserting the circuit board into the backplane. Figures 5a and 5b show typical results in a 12V application with different VCC lead lengths. The peak amplitude reaches 22V, breaking down the ESD protection diode in the process. There are two methods for eliminating ringing: clipping and snubbing. A transient voltage suppressor is an effective means of limiting peak voltage to a safe level. Figure␣ 6 shows the effect of adding an ON Semiconductor, 1SMA12CAT3, on the waveform of Figure 5. Figures 7a and 7b show the effects of snubbing with different RC networks. The capacitor value is chosen as 10X to 100X the FET COSS under bias and R is selected for best damping—1Ω to 50Ω depending on the value of parasitic inductance. R1 0.01Ω 8' IRF7413 + 12V + – POWER LEADS VOUT CLOAD 10Ω SCOPE PROBE 0.1µF LTC1645 1645 F05 4V/DIV 24V 4V/DIV 24V 0V 0V 1µs/DIV 1µs/DIV 1645 F05a (a) Undamped VCC Waveform (48" Leads) 1645 F05b (b) Undamped VCC Waveform (8" Leads) Figure 5. Ring Experiment 9 LTC1645 U W U U APPLICATIO S I FOR ATIO R1 0.01Ω IRF7413 VOUT 12V CLOAD 10Ω D1* 2V/DIV + – PCB EDGE CONNECTOR 12V POWER LEADS BACKPLANE CONNECTOR + 0.1µF LTC1645 0V 1645 F06 1µs/DIV ON SEMICONDUCTOR * 1SMA12CAT3 1645 F06a VCC Waveform Clamped by a Transient Suppressor Figure 6. Transient Suppressor Clamp R1 0.01Ω IRF7413 + – PCB EDGE CONNECTOR 12V POWER LEADS BACKPLANE CONNECTOR + 10Ω VOUT CLOAD 10Ω 0.1µF 0.1µF LTC1645 1645 F07 12V 2V/DIV 2V/DIV 12V 0V 0V 1µs/DIV 1µs/DIV 1645 F07a (a) VCC Waveform Damped by a Snubber (15Ω, 6.8nF) (b) VCC Waveform Damped by a Snubber (10Ω, 0.1µF) Figure 7. Snubber “Fixes” 10 1645 F07b LTC1645 U W U U APPLICATIO S I FOR ATIO SUPPLY GLITCH 12V + – R1 0.01Ω If a dead short occurs after a supply connection is made (Figure 8), the sense resistor R1 and the RDS(ON) of the fully enhanced FET provide a low impedance path for IRF7413 2µH 10Ω + 100µF 0.1µF LTC1645 BOARD WITH POSSIBLE SHORT-CIRCUIT FAULT LTC1645 Hot Swap circuits on the backplane are generally used to provide power-up/down sequence at insertion/ removal as well as overload/short-circuit protection. If a short-circuit occurs at supply ramp-up, the circuit breaker trips. The partially enhanced FET is easily disconnected without any supply glitch. BACKPLANE CONNECTOR Supply Glitching 1645 F08 4V/DIV 25A/DIV GATE VCC 1µs/DIV 1µs/DIV 1645 F08a (a) VCC Short-Circuit Supply Current Glitch Without Any Limiting 1645 F08b (b) VCC Supply Glitch Without Any Limiting 4V/DIV 5A/DIV GATE 1µs/DIV VCC 1µs/DIV 1645 F08c (c) VCC Short-Circuit Supply Current Glitch with 2µH Series Inductor 1645 F08d (d) VCC Supply Glitch with 2µH Series Inductor Figure 8. Supply Glitch 11 LTC1645 U W U U APPLICATIO S I FOR ATIO nearly unlimited current flow. The LTC1645 discharges the GATE pin in a few microseconds, but during this discharge time current on the order of 150 amperes flows from the VCC power supply. This current spike glitches the power supply, causing VCC to dip (Figure 8a and 8b). On recovery from overload, some supplies may overshoot. Other devices attached to this supply may reset or malfunction and the overshoot may also damage some components. An inductor (1µH to 10µH) in series with the FET’s source limits the short-circuit di/dt, thereby limiting the peak current and the supply glitch (Figure 8c and 8d). Additional power supply bypass capacitance also reduces the magnitude of the VCC glitch. Reset The LTC1645 uses an internal 1.238V bandgap reference, a precision voltage comparator, and a resistive divider to monitor the output supply voltage (Figure 9). Whenever the voltage at the FB pin rises above its reset threshold (1.238V), the comparator output goes high, and a timing cycle starts (see Figure 10, time points 1 and 4). After a complete timing cycle, RESET is released. An external pull-up is required for the RESET pin to rise to a logic high. Glitch Filter The LTC1645 has a glitch filter to prevent RESET from generating a spurious system reset in the presence of transients on the FB pin. The filter is 20µs for large transients (greater than 150mV) and up to 80µs for smaller transients. The relationship between glitch filter time and the transient voltage is shown in Typical Performance Characteristics: Glitch Filter Time vs Feedback Transient. Timer The system timing for the LTC1645 is generated by the circuitry shown in Figure 11. The timer is used to set the turn-on delay after the ON pin goes high. It also sets the delay before the RESET pin goes high after the FB pin exceeds 1.238V. Whenever the timer is off, the internal N-channel shorts the TIMER pin to ground (Figure 11). Activating the timer connects a 2µA current from VCC1 to the TIMER pin and the 3 V1 V2 ON V2 1.23V 1.23V TIMER RESET 1645 F10 Figure 10. Supply Monitor Waveforms ON LOGIC SUPPLY MONITOR 2µA + 4 V1 VOUT When the voltage at the FB pin drops below its reset threshold, the comparator output goes low. After passing through a glitch filter, RESET is pulled low (time point 2). If the FB pin rises above the reset threshold for less than a timing cycle, the RESET output remains low (time point 3). VOUT 2 1 V2 + FB COMP LOGIC COMP 10k – 1.238V REFERENCE TIMER 1.23V – µP RESET RESET TIMER CTIMER TIMER 1645 F09 CTIMER 1645 F11 Figure 9. Supply Monitor Block Diagram 12 Figure 11. System Timing Block Diagram LTC1645 U W U U APPLICATIO S I FOR ATIO voltage on the external capacitor CTIMER starts to ramp up with a slope dv/dt = 2µA/CTIMER. When the voltage reaches the trip point (1.23V), the timer is reset by pulling the TIMER pin back to ground. The timer period is t = (1.23V • CTIMER)/2µA. For a 200ms delay, use a 0.33µF capacitor. Electronic Circuit Breaker The LTC1645 features an electronic circuit breaker function that protects against short circuits or excessive output currents. By placing sense resistors between the supply inputs and sense pins of the supplies, the circuit breaker trips whenever the voltage across either sense resistor is greater than 50mV for more than 1.5µs. If the circuit breaker trips, both GATE pins are immediately pulled to ground and the external N-channels FETs are quickly turned off (time point 6 in Figure 12). The circuit breaker resets and another timing cycle starts by taking CURRENT FAULT RAMPING UP 1 2 3 4 5 6 RESET FAULT AND RAMP UP 7 8 9 10 VCCn ON VCCn – VSENSEn the ON pin below 0.4V and then high as shown at time point 7. At the end of the timer cycle (time point 8), the charge pump turns on again. If the circuit breaker feature is not required, short the SENSEn pin to VCCn. If the 1.5µs response time is too fast to reject supply noise, add external resistors and capacitors RF and CF to the sense circuit as shown in Figure 13. The ON Pin The ON pin is used to control system operation as shown in Figure 14. At time point 1, the board makes connection and the supplies power up the chip. At time point 2, the ON pin goes high and a timer cycle starts as long as both VCC pins are higher than the undervoltage lockout trip point (2.23V for VCC1 and 1.12V for VCC2) and an overcurrent fault is not detected. At the end of the timer cycle (time point 3), the charge pump is turned on and the GATEn pin voltages start to ramp up with the output supply voltages, VOUTn, following one gate-to-source voltage drop lower. At time point 4, VOUT2 reaches its power-good trip level (this example assumes the FB pin resistive divider is connected to VOUT2) and a timing cycle starts. At the end of the timing cycle (time point 5), RESET goes high and the power-up process is complete. TIMER RAMPING UP AND DOWN TOGETHER RAMPING UP AND DOWN SEPARATELY RAMPING UP AND TURNING OFF FAST GATEn 12 VOUTn 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VCCn 2V RESET 1645 F12 Figure 12. Current Fault Timing 0.8V ON 0.4V 0V TIMER GATE1 CF RF VOUT1 GATE2 VCCn SENSEn GATEn VOUT2 LTC1645 RESET 1645 G13 1645 F14 Figure 13. Extending the Short-Circuit Protection Delay Figure 14. ON Pin Waveforms 13 LTC1645 U W U U APPLICATIO S I FOR ATIO An external hard reset is initiated at time point 6. The ON pin is forced below 0.8V but above 0.4V, and the GATEn pin voltages start to ramp down. VOUTn also starts to ramp down, and RESET goes low when VOUT2 drops below the power-good trip level at time point 7. Time points 16 to 19 show the same power-up sequence as time points 2 to 5, while time point 20 demonstrates the GATEn pins being pulled immediately to ground (instead of ramping down) by the ON pin going below 0.4V. Power Supply Tracking and Sequencing Applications Time points 8 to 15 are similar to time points 1 to 7, except the ON pin’s different voltage thresholds are used to ramp VOUT1 and VOUT2 separately. At time point 8, the ON pin goes above 0.8V but below 2V, and one timing cycle later (time point 9) GATE1 begins to ramp up with VOUT1 following one gate-to-source voltage drop lower. At time point 10, the ON pin goes above 2V and GATE2 immediately begins ramping up with VOUT2 following one gate-tosource voltage drop lower. As soon as VOUT2 reaches its power-good trip level at time point 11, a timing cycle starts. At the end of the timing cycle (time point 12), RESET goes high and the power-up process is complete. The LTC1645 is able to sequence VOUTn in a number of ways, including ramping VOUT1 up first and down last; ramping VOUT1 up first and down first; ramping VOUT1 up first and VOUT1 and VOUT2 down together; and ramping VOUT1 and VOUT2 up and down together. Figure 15 shows an application ramping VOUT1 and VOUT2 up and down together. The ON pin must reach 0.8V to ramp up VOUT1 and VOUT2. The spare comparator pulls the ON pin low until VCC2 is above 2.3V, and the ON pin cannot reach 0.8V before VCC1 is above 3V. Thus, both input supplies must be within regulation before a timing cycle can start. At the end of the timing cycle, the output voltages ramp up together. If either input supply falls out of regulation, the gates of Q1 and Q2 are pulled low together. Figure 16 shows an oscilloscope photo of the circuit in Figure 15. The ON pin is forced below 2V but above 0.8V at time point 13 and the GATE2 pin voltage starts to ramp down. VOUT2 also starts to ramp down and RESET goes low when VOUT2 drops below the power-good trip level at time point 14. When the ON pin goes below 0.8V but above 0.4V at time point 15, GATE1 and VOUT1 ramp down. BOTH CURRENT LIMITS: 5A Q1 1/2 Si4920DY 0.01Ω* VIN1 3.3V D1 1N4002 10Ω Q2 0.01Ω* 1/2 Si4920DY VIN2 2.5V D2 1N4002 + CLOAD1 D3 MBR0530T1 VOUT1 3.3V 2.5A VOUT2 2.5V 2.5A + CLOAD2 10k 10Ω 14 4.99k 1% TRIP POINT: 3V 1.37k 1% 12 VCC1 SENSE1 GATE1 10 1 VCC2 SENSE2 GATE2 COMP+ COMPOUT LTC1645 (14-LEAD) FB 8 9 1.18k 1% 6 5 FAULT TIMER 11 0.33µF GND 10k 0.1µF 25V 3 2 ON 1.82k 1% 4 1.18k 1% 13 1.37k 1% RESET 7 µP RESET 1645 F15 *WSL1206-01-1% (VISHAY DALE) Figure 15. Ramping 3.3V and 2.5V Up and Down Together 14 LTC1645 U W U U APPLICATIO S I FOR ATIO VIN2 5V/DIV VIN1 5V/DIV VOUT2 5V/DIV VOUT1 5V/DIV TIMER 2V/DIV RESET 5V/DIV Figure 16. Ramping 3.3V and 2.5V Up and Down Together This circuit guarantees that: (1) VOUT1 never exceeds VOUT2 by more than 1.2V, and (2) VOUT2 is never greater than VOUT1 by more than 0.4V. On power-up, VOUT1 and VOUT2 ramp up together. On power-down, the LTC1645 turns off Q1 and Q2 simultaneously. Charge remains stored on CLOAD1 and CLOAD2 and the output voltages will vary depending on the loads. D1 and D2 turn on at ≈ 1V (≈ 0.5V each), ensuring condition 1 is satisfied, while D3 prevents violations of condition 2. Different diodes may be necessary for different output voltage configurations. Barring an overvoltage condition at the input(s), the only time these diodes might conduct current is during a power-down event, and then only to discharge CLOAD1 or CLOAD2. In the case of an input overvoltage condition that causes excess current to flow, the circuit breaker will trip if the current limit level is set appropriately. Figure 17 shows an application circuit where VOUT1 ramps up before VOUT2. VOUT1 is initially discharged and D1 is reverse-biased, thus the voltage at the ON pin is determined only by VCC1 through the resistor divider R1 and R2. The voltage at the ON pin exceeds 0.8V if V CC1 is above 4.6V and VOUT1 begins to ramp up after a timing cycle. As VOUT1 ramps up, D1 becomes forward-biased and pulls the ON pin above 2V when VOUT1 ≈ 4.5V. This turns on GATE2 and VOUT2 ramps up. The FB comparator monitors VOUT2, and the spare comparator monitors VOUT1 with RHYST creating ≈50mV of hysteresis. Power Supply Multiplexer Using back-to-back FETs, the LTC1645 can Hot Swap two supplies to the same output, automatically selecting the primary supply if present or the secondary supply if the primary supply is not available. Referring to Figure 18, a diode-or circuit provides power to the LTC1645 if either supply is up. Schottky diodes are used to prevent the voltage at VCC1 from approaching the undervoltage lockout threshold. This application assumes that if a supply is not present, the supply input is floating. If only the 3.3V supply is present, the voltage at the COMP + pin is below the trip point and COMPOUT pulls the base of Q3 low, allowing the GATE1 pin to ramp up normally. The voltage at the ON pin exceeds 0.8V if the 3.3V supply is greater than 3V, ramping up GATE1 and turning on Q1A and Q1B. The ON pin does not exceed 2V (unless the 3.3V supply exceeds 7.5V!), keeping GATE2 low and Q2A and Q2B off. If only the 5V supply is present or if both supplies are present, the COMP + pin is above 1.238V and COMPOUT allows the base of Q3 to be pulled high by R2. This turns Q3 on, keeping GATE1 low and Q1A and Q1B off. The voltage at the ON pin is pulled above 2V by R1 and GATE2 turns Q2A and Q2B on. 15 LTC1645 U W U U APPLICATIO S I FOR ATIO 0.005Ω* BOTH CURRENT LIMITS: 10A VIN2 3.3V IRF7413 + CLOAD2 0.005Ω* VIN1 5V IRF7413 + CLOAD1 D1 1N4148 10Ω 13k 1% 10k R1 47.5k 1% 10Ω 0.01µF 25V 0.01µF 25V 14 13 12 1 VCC1 SENSE1 GATE1 10 VCC2 SENSE2 GATE2 COMP+ ON R2 10k 1% 3 2 COMPOUT FB 4 FAULT RESET FAULT TIMER 10k 28k 1% 8 14.7k 1% RHYST 681k LTC1645 (14-LEAD) 10k 10k 1% 9 µP RESET2 6 10k 1% 5 GND 11 µP RESET 7 1645 F17 0.33µF *LRF1206-01-R005-J (IRC) Figure 17. Ramping Up 5V Followed by 3.3V Q1A Q1B IRF7313 VIN1 3.3V D1 1/2 BAT54C Q2A Q2B IRF7313 10Ω VIN2 5V R1 10k 14 10k VCC1 10 10k D2 1/2 BAT54C 22.6k 1% 13 12 1 10Ω 2 0.1µF 25V 3 R2 10k SENSE1 GATE1 VCC2 SENSE2 GATE2 COMP+ ON 11.3k 1% 4 0.1µF 25V VOUT 5V OR 3.3V 5A COMPOUT LTC1645 (14-LEAD) FB FAULT TIMER GND 11 7 RESET 8 9 Q3 PN2222 6 5 0.33µF 1645 F18 Figure 18. Power Supply Multiplexer 16 VOUT2 3.3V 5A VOUT1 5V 5A LTC1645 U W U U APPLICATIO S I FOR ATIO goes high which turns on Q3. This lowers the voltage on the gate of Q2. This feedback loop is compensated by capacitors C1 and C2 and resistor R1. When power is first applied, the FB pin is low and RESET holds one side of C2 low, slowing the ramp-up of VOUT2. As VOUT2 exceeds 2.75V, RESET releases to allow improved loop transient response. Figure 20 shows the load transient response and voltage ripple of the generated supply. Using the LTC1645 as a Linear Regulator This application uses the LTC1645 to Hot Swap one primary supply and generate a secondary low dropout regulated supply. Figure 19 shows how to switch a 5V supply and create a 3.3V supply using the spare comparator and one additional transistor. The COMP+ pin is used to monitor the 3.3V output. As the voltage on the gate of Q2 increases, the 3.3V output increases. At the 3.3V threshold the spare comparator trips. The COMPOUT pin Q1 IRF7413 0.01Ω* VIN 5V VOUT1 5V 2.5A BOTH CURRENT LIMITS: 5A + CLOAD1 10Ω 0.1µF 25V 0.01Ω* 1M Q2 IRFZ24 + 10k 10Ω 14 13 VCC1 SENSE1 GATE1 10 1 12 VCC2 SENSE2 GATE2 COMP+ ON LTC1645 (14-LEAD) 4 3 2 COMPOUT FB R1 200k C2 0.1µF 25V 2.49k 1% VOUT2 3.3V 2.5A 470µF** 6V ×2 C1 0.033µF 8 9 Q3 PN2222 6 1.5k 1% 12.1k 1% 5 FAULT TIMER GND 11 7 0.33µF RESET 10k 1% *LRF1206-01-R010-J (IRC) **T510X477K006AS (KEMET) 1645 F19 Figure 19. Switching 5V and Generating 3.3V VOUT2 0.1V/DIV 2.5A IOUT2 1A/DIV 0.5A Figure 20. Load Transient Response and Voltage Ripple 17 LTC1645 U W U U APPLICATIO S I FOR ATIO Switching Regulator Supply Sequencing Switching Regulator Hot Swapping Figure 21 shows the LTC1645 sequencing two power supplies, the lower of which is generated by the LTC1430A switching regulator. Connecting the regulator’s FB pin resistor divider (R1 and R2) to the other side of the pass FET (Q1) allows the LTC1430A to compensate for the voltage drop across RSENSE1 and Q1, assuring an accurate voltage output. The spare comparator holds the LTC1645’s ON pin low until the LTC1430A’s output is at least 3V, and shuts both channels off if it drops below 3V. When the ON/OFF signal is taken high to 5V (turn-on), the voltage at the ON pin rises with an RC exponential characteristic, reaching 0.8V first. This starts a timing cycle, and GATE1 begins to rise. GATE2 starts to ramp up after the ON pin reaches 2V. As long as the timing cycle is shorter than the time for the ON pin to rise from 0.8V to 2V, VOUT2 ramps up after VOUT1. RESET goes high one timing cycle after VOUT1 exceeds 3V. When the ON/OFF signal is brought low, the voltage at the ON pin exponentially decays and GATE2 ramps down before GATE1. RESET goes low as soon as VOUT1 falls below 3V. Figure 22 shows the powerup and power-down sequences of the circuit in Figure 21. High current switching regulators usually require large bypass capacitors on both input and output for proper operation. The application in Figure 23 controls the inrush current to the LTC1649’s input bypass capacitors and ramps the two output voltages up and down together. As with the previous application, connecting the regulator’s FB pin resistor divider to the other side of the output pass FET (Q2) allows the LTC1649 to compensate for the voltage drop across Q2, assuring an accurate voltage output. The voltage at the LTC1645’s ON pin reaches 0.8V when VIN exceeds 3V, and GATE1 begins to ramp up one timing cycle later. As the regulator’s output rises, D2 pulls the ON pin above 2V and GATE2 begins to rise, ramping VOUT1 and VOUT2 up together. RESET goes high one timing cycle after VOUT1 exceeds 3V and VOUT2 exceeds 2.35V. Figure 24 shows the circuit in Figure 23 powering up. Care should be taken connecting a switching regulator’s FB or SENSE pins to a node other than its output. Depending on the regulator’s internal architecture, unusual behavior may occur as it tries in vain to raise the voltage at ON 2V/DIV VREGOUT 2V/DIV VOUT1 2V/DIV VOUT2 2V/DIV RESET 5V/DIV Figure 22. Switching Regulator Supply Sequencing 18 FAULT ON/OFF 10k 1µF 270pF 15µF 10V + 4700pF 22k 1500µF 6.3V ×3 6 5 8 7 0.1µF 51Ω COMP SHDN G2 PVCC2 GND FB G1 PVCC1 LTC1430ACS8 3 4 1 2 0.1µF + 130k 1% 162k 1% 1500µF 6.3V ×2 VREGOUT 1µF 1µF R2 16.9k 1% *LRF1206-01-R010-J (IRC) 4700pF 1Ω 2.4µH CDRH1272R4 R1 16.5k 1% 4 10 13 12 FAULT ON 7 GND LTC1645 (14-LEAD) 10Ω RESET FB COMPOUT COMP+ 3 1 2 VCC2 SENSE2 GATE2 0.047µF 25V 11 0.33µF TIMER VCC1 SENSE1 GATE1 14 10Ω RSENSE1* Q1 0.01Ω 1/2 Si4920DY Figure 21. Switching Regulator Supply Sequencing MBRS130T3 Si4410DY Si4410DY 680pF MBR0530T1 5 6 9 8 0.047µF 25V 1.87k 1% 2.67k 1% 1.15k 1% 3.16k 1% 10k + + 1645 F21 CLOAD1 CLOAD2 RESET VOUT1 3.3V 2.5A VOUT2 5V 2.5A U U W + RSENSE2* Q2 0.01Ω 1/2 Si4920DY APPLICATIO S I FOR ATIO U VIN 5V LTC1645 19 20 FAULT 10k + 0.33µF 100k 0.1µF 0.1µF 14 0.1µF 1.82k 1% 4 FAULT 4.99k VCC1 1% 10 ON 0.33µF MBR0530LT1 1500µF 6.3V ×6 VREGIN D2 MBR0530T1 10µF *LRF2010-01-R003-J (IRC) **MBRS340T (ON SEMICONDUCTOR) †ETQP6F1R2HFA (PANASONIC) GND 10Ω + 12 C– VIN SS 3 7 GND COMPOUT COMP+ RESET FB 9 8 5 6 + 18k 0.047µF 25V 100µF 0.1µF 10k 33k 0.015µF 1.87k 1% 2.67k 1% 220pF IRF7801 IRF7801 Figure 23. Switching Regulator Hot Swap 0.01µF 2 10Ω Q3 FDS6680 1µF 220Ω 1k IRF7801 VCC2 SENSE2 GATE2 1 0.003Ω* MBR0530LT1 0.01µF 25V 0.33µF 10 11 12 13 14 15 16 9 C+ CPOUT COMP IMAX LTC1645 (14-LEAD) 11 TIMER VCC PVCC2 G2 LTC1649 IFB SHDN FB GND PVCC1 G1 SENSE1 GATE1 13 8 7 6 5 4 3 2 1 IRF7801 ** R2 1k R1 1.8k 1µF + D1 1N4148 2200pF 5.1Ω 1.2µH† 0.01µF 1500µF 6.3V ×4 VREGOUT 1µF 1645 F23 10Ω Q2 FDB8030L 1.13k 1% 1.02k 1% + 3.09k 1% 3.01k 1% + RESET CLOAD1 VOUT1 3.3V 10A GND CLOAD2 VOUT2 2.5V 15A U U W Q1 0.003Ω* FDB8030L APPLICATIO S I FOR ATIO U VIN 3.3V LTC1645 LTC1645 U W U U APPLICATIO S I FOR ATIO Table 1. N-Channel Selection Guide ON 2V/DIV CURRENT LEVEL PART NUMBER MANUFACTURER DESCRIPTION 1A to 2A NDH8503N Fairchild Dual N-Channel RDS(ON) = 0.033 SuperSOT-8 1A to 2A Si6928DQ Siliconix Dual N-Channel RDS(ON) = 0.035 TSSOP-8 2A to 5A Si4920DY Siliconix Dual N-Channel RDS(ON) = 0.025 SO-8 2A to 5A IRF7313 International Rectifier Dual N-Channel RDS(ON) = 0.029 SuperSOT-8 5A to 10A Si4420 Siliconix Single N-Channel RDS(ON) = 0.009 SO-8 5A to 10A FDS6680 Fairchild Single N-Channel RDS(ON) = 0.01 SO-8 5A to 10A IRF7413 International Rectifier Single N-Channel RDS(ON) = 0.011 SO-8 5A to 10A MMSF3300 ON Semiconductor Single N-Channel RDS(ON) = 0.0125 SO-8 10A to 20A FDB8030L Fairchild Single N-Channel RDS(ON) = 0.0035 TO-263AB 10A to 20A SUD75N03-04 Siliconix Single N-Channel RDS(ON) = 0.004 D2PAK VREGIN 2V/DIV VREGOUT 2V/DIV VOUT2 2V/DIV VOUT1 2V/DIV RESET 5V/DIV Figure 24. Switching Regulator Hot Swap its FB or SENSE pin. In the case of the LTC1649, large peak currents result if the FB pin is at ground and not connected directly to the output inductor and capacitors. To keep the peak currents under control, R1, R2 and D1 hold the FB pin above ground but below its normal regulated value until VOUT2 ramps up and D1 reverse-biases. Power N-Channel Selection The RDS(ON) of the external pass transistors must be low enough so that the voltage drop across them is 100mV or less at full current. If the RDS(ON) is too high, the voltage drop across the transistor can cause the output voltage to trip the reset circuit. The transistors listed in Table 1 or other similar transistors are recommended for use with the LTC1645. Low voltage applications may require the use of logic-level FETs; ensure their maximum VGS rating is sufficient for the application. GATE voltage as a function of VCC is illustrated in the Typical Performance curves. If lower GATE drive is desired, connect a diode in series with a zener between GATE and VCC or between GATE and VOUT as shown in Figure 25. R1 Q1 VCC VOUT D1* D2 1N4148 D2 1N4148 D4* *USER SELECTED VOLTAGE CLAMP 1N4688 (5V) 1N4692 (7V): LOGIC-LEVEL MOSFET 1N4695 (9V) 1N4702 (15V): STANDARD-LEVEL MOSFET 1645 F25 Figure 25. Optional Gate Clamp 21 LTC1645 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.014 – 0.019 (0.355 – 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 22 2 3 4 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) BSC SO8 1298 LTC1645 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. S Package 14-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.337 – 0.344* (8.560 – 8.738) 14 13 12 11 10 9 8 0.228 – 0.244 (5.791 – 6.197) 0.150 – 0.157** (3.810 – 3.988) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 2 3 4 5 6 0.053 – 0.069 (1.346 – 1.752) 0.004 – 0.010 (0.101 – 0.254) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.014 – 0.019 (0.355 – 0.483) TYP 7 0.050 (1.270) BSC *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. S14 1298 23 LTC1645 U TYPICAL APPLICATIO Dual Supply Hot Swap with Tracking Outputs BOTH CURRENT LIMITS: 5A Q1 1/2 Si4920DY 0.01Ω* VIN1 3.3V D1 1N4002 D2 1N4002 10Ω Q2 0.01Ω* 1/2 Si4920DY VIN2 2.5V + CLOAD1 D3 MBR0530T1 VOUT1 3.3V 2.5A VOUT2 2.5V 2.5A + CLOAD2 10k 10Ω 14 4.99k 1% TRIP POINT: 3V 13 12 VCC1 SENSE1 GATE1 10 1 VCC2 SENSE2 GATE2 COMP+ ON 1.82k 1% COMPOUT LTC1645 (14-LEAD) 4 1.18k 1% FB 8 9 1.18k 1% 6 5 FAULT TIMER 11 0.33µF 1.37k 1% GND 10k 0.1µF 25V 3 2 1.37k 1% RESET 7 µP RESET 1645 F15 *WSL1206-01-1% (VISHAY DALE) RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1421 Hot Swap Controller Dual Supplies from 3V to 12V, Additionally – 12V LTC1422 Hot Swap Controller Single Supply Hot Swap in SO-8 from 3V to 12V LT1640L/LT1640H Negative Voltage Hot Swap Controllers Negative High Voltage Supplies from –10V to – 80V LT1641 Positive Voltage Hot Swap Controller Positive High Voltage Supplies From 9V to 80V LTC1642 Fault Protected Hot Swap Controller 3V to 15V, Overvoltage Protection Up to 33V LTC1643L/LTC1643L-1/ LTC1643H PCI-Bus Hot Swap Controllers 3.3V, 5V, 12V, –12V Supplies for PCI Bus LTC1647 Dual Hot Swap Controller Dual ON Pins for Supplies from 3V to 15V 24 Linear Technology Corporation 1645f LT/TP 0400 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 1999