LTC4210-1/LTC4210-2 Hot Swap Controller in 6-Lead SOT-23 Package U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®4210 is a 6-pin SOT-23 Hot SwapTM controller that allows a board to be safely inserted and removed from a live backplane. An internal high side switch driver controls the GATE of an external N-channel MOSFET for a supply voltage ranging from 2.7V to 16.5V. The LTC4210 provides the initial timing cycle and allows the GATE to be ramped up at an adjustable rate. Allows Safe Board Insertion and Removal from a Live Backplane Adjustable Analog Current Limit with Circuit Breaker Fast Response Limits Peak Fault Current Automatic Retry or Latch Off On Current Fault Adjustable Supply Voltage Power-Up Rate High Side Drive for External MOSFET Switch Controls Supply Voltages from 2.7V to 16.5V Undervoltage Lockout Adjustable Overvoltage Protection Low Profile (1mm) SOT-23 (ThinSOTTM) Package The LTC4210 features a fast current limit loop providing active current limiting together with a circuit breaker timer. The signal at the ON pin turns the part on and off and is also used for the reset function. U APPLICATIO S ■ ■ ■ This part is available in two options: the LTC4210-1 for automatic retry on overcurrent fault and the LTC4210-2 for latch off on an overcurrent fault. Hot Board Insertion Electronic Circuit Breaker Industrial High Side Switch/Circuit Breaker , LTC and LT are registered trademarks of Linear Technology Corporation. ThinSOT and Hot Swap are trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO Single Channel 5V Hot Swap Controller BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) VIN 5V RSENSE 0.01Ω LONG Z1 OPTIONAL + RX 10Ω CX 0.1µF VCC SHORT RON1 20k ON RON2 10k Q1 Si4410DY SENSE GATE LTC4210 TIMER VOUT 5V 470µF 4A CLOAD Power-Up Sequence CLOAD = 470µF VON (2V/DIV) RG 100Ω VTIMER (1V/DIV) RC 100Ω CC 0.01µF VOUT (5V/DIV) GND GND LONG Z1: ISMA10A OR SMAJ10A CTIMER 0.22µF IOUT (0.5A/DIV) GND 4210 TA01 10ms/DIV 4210 TA02 421012f 1 LTC4210-1/LTC4210-2 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) Supply Voltage (VCC) ............................................... 17V Input Voltage (SENSE, TIMER) .. – 0.3V to (VCC + 0.3V) Input Voltage (ON) ..................................... –0.3V to 17V Output Voltage (GATE) ........ Internally Limited (Note 3) Operating Temperature Range LTC4210-1C/LTC4210-2C ....................... 0°C to 70°C LTC4210-1I/LTC4210-2I .................... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW 6 VCC TIMER 1 5 SENSE GND 2 4 GATE ON 3 LTC4210-1CS6 LTC4210-2CS6 LTC4210-1IS6 LTC4210-2IS6 S6 PACKAGE 6-LEAD PLASTIC TSOT-23 S6 PART MARKING TJMAX = 125°C, θJA = 230°C/ W LTYW LTYX LTF5 LTF6 Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, unless otherwise noted. (Note 2) SYMBOL VCC ICC VLKOR VLKOHYST IINON IINSENSE VCB IGATEUP IGATEDN PARAMETER Supply Voltage VCC Supply Current VCC Undervoltage Lockout Release VCC Undervoltage Lockout Hysteresis ON Pin Input Current SENSE Pin Input Current Circuit Breaker Trip Voltage GATE Pin Pull-Up Current GATE Pin Pull-Down Current ∆VGATE External N-Channel Gate Drive ITIMERUP TIMER Pin Pull-Up Current ITIMERDN TIMER Pin Pull-Down Current VTIMER TIMER Pin Threshold VTMRHYST VON VONHYST TIMER Low Threshold Hysteresis ON Pin Threshold ON Pin Threshold Hysteresis CONDITIONS ● MIN 2.7 ● VCC Rising ● 2.2 ● –10 –10 44 –5 VSENSE = VCC VCB = (VCC – VSENSE) VGATE = 0V VTIMER = 1.5V, VGATE = 3V or VON = 0V, VGATE = 3V or VCC – VSENSE = 100mV, VGATE = 3V VGATE – VCC, VCC = 2.7V VGATE – VCC, VCC = 3V VGATE – VCC, VCC = 3.3V VGATE – VCC, VCC = 5V VGATE – VCC, VCC = 12V VGATE – VCC, VCC = 15V Initial Cycle, VTIMER = 1V During Current Fault Condition, VTIMER = 1V After Current Fault Disappears, VTIMER = 1V Under Normal Conditions, VTIMER = 1V High Threshold, TIMER Rising Low Threshold, TIMER Falling ● ● ● 1.22 0.15 ON Threshold, ON Rising ● 1.22 ● ● ● ● ● ● ● ● ● ● 4.0 4.5 5.0 10 9.0 6.0 –2 –25 ● TYP 0.65 2.5 100 0 5 50 – 10 25 6.5 7.5 8.5 12 12 11 –5 –60 2 100 1.3 0.2 100 1.3 80 MAX 16.5 3.5 2.65 10 10 56 –15 8 10 12 16 16 18 –8.5 –100 3.5 1.38 0.25 1.38 UNITS V mA V mV µA µA mV µA mA V V V V V V µA µA µA µA V V mV V mV 421012f 2 LTC4210-1/LTC4210-2 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, unless otherwise noted. (Note 2) SYMBOL tOFF(TMRHIGH) tOFF(ONLOW) tOFF(VCCLOW) PARAMETER Turn-Off Time (TIMER Rise to GATE Fall) Turn-Off Time (ON Fall to GATE Fall) Turn-Off Time (VCC Fall to IC Reset) CONDITIONS VTIMER = 0V to 2V Step, VCC = VON = 5V VON = 5V to 0V Step, VCC = 5V VCC = 5V to 2V Step, VON = 5V Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. MIN TYP 1 30 30 MAX UNITS µs µs µs Note 3: An internal Zener on the GATE pin clamps the charge pump voltage to a typical maximum voltage of 26V. External overdrive of the GATE pin beyond the internal Zener voltage may damage the device. Without a limiting resistor, the GATE capacitance must be <0.15µF at maximum VCC. If a lower GATE pin clamp voltage is desired, an external Zener diode may be used. U W TYPICAL PERFOR A CE CHARACTERISTICS 4.0 4.0 TA = 25°C 3.5 SUPPLY CURRENT (mA) 2.5 2.0 1.5 1.0 3.0 2.5 2.0 VCC = 15V 1.5 VCC = 12V 1.0 VCC = 5V 0.5 0.5 0 –75 –50 –25 0 0 2 4 VCC = 3V 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4210 G01 2.60 2.55 2.45 2.35 2.30 35 –8.5 30 30 TA = 25°C VGATE (V) 25 VCC = 12V 15 15 VCC = 5V 10 10 5 5 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4210 G04 75 100 125 150 0 –75 –50 –25 TA = 25°C –9.0 VCC = 15V 20 2 50 IGATEUP vs Supply Voltage 35 0 25 4210 G03 –8.0 0 0 TEMPERATURE (°C) VGATE vs Temperature 20 VCC FALLING 2.40 40 25 VCC RISING 2.50 4210 G02 VGATE vs Supply Voltage 40 VGATE (V) 2.65 2.25 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) IGATEUP (µA) SUPPLY CURRENT (mA) 3.5 3.0 Undervoltage Lockout Threshold vs Temperature Supply Current vs Temperature UNDERVOLTAGE LOCKOUT THRESHOLD (V) Supply Current vs Supply Voltage –9.5 –10.0 –10.5 –11.0 VCC = 3V –11.5 –12.0 0 25 50 75 100 125 150 TEMPERATURE (°C) 4210 G05 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4210 G06 421012f 3 LTC4210-1/LTC4210-2 U W TYPICAL PERFOR A CE CHARACTERISTICS ∆VGATE vs Supply Voltage ∆VGATE vs Temperature 18 –8.5 16 16 –9.0 14 14 12 12 VCC = 5V VCC = 15V –10.0 –10.5 –11.0 VCC = 12V –11.5 –12.0 –75 –50 –25 0 25 50 18 TA = 25°C ∆VGATE (V) VCC = 3V –9.5 ∆VGATE (V) IGATEUP (µA) IGATEUP vs Temperature –8.0 10 VCC = 12V 8 VCC = 15V 6 6 VCC = 3V 4 4 10 8 2 75 100 125 150 0 2 4 TEMPERATURE (°C) –2 –3 –3 –50 –60 –6 –8 –8 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) –90 –10 –75 –50 –25 0 25 50 75 100 125 150 3.0 VCC = 5V ITIMERDN (µA) ITIMERUP (µA) –40 –100 –75 –50 –25 3.0 2.8 2.6 2.6 2.4 2.4 ITIMERDN (µA) –30 –90 2.2 2.0 1.8 25 50 75 100 125 150 TEMPERATURE (°C) 4210 G13 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 2.0 1.8 1.6 1.4 1.4 1.2 1.2 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4210 G14 VCC = 5V 2.2 1.6 1.0 0 4 ITIMERDN (In Cool-Off Cycle) vs Temperature TA = 25°C 2.8 –80 2 4210 G12 ITIMERDN (In Cool-Off Cycle) vs Supply Voltage –20 –70 0 4210 G11 ITIMERUP (During Circuit Breaker Delay) vs Temperature –60 –100 TEMPERATURE (°C) 4210 G10 –50 –70 –80 –9 0 TA = 25°C –40 –5 –7 –10 75 100 125 150 –30 –4 –7 –9 –20 ITIMERUP (µA) –2 –6 50 ITIMERUP (During Circuit Breaker Delay) vs Supply Voltage VCC = 5V –1 ITIMERUP (µA) ITIMERUP (µA) 0 TA = 25°C –5 25 4210 G09 ITIMERUP (In Initial Cycle) vs Temperature –4 0 TEMPERATURE (°C) 4210 G08 ITIMERUP (In Initial Cycle) vs Supply Voltage 0 2 –75 –50 –25 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4210 G07 –1 VCC = 5V 1.0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 4210 G15 421012f 4 LTC4210-1/LTC4210-2 U W TYPICAL PERFOR A CE CHARACTERISTICS TIMER High Threshold vs Temperature TIMER High Threshold vs Supply Voltage 1.38 1.38 TA = 25°C 0.24 VCC = 5V 1.36 1.34 1.32 1.30 1.28 1.26 1.34 1.32 1.30 1.28 1.26 1.24 1.24 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 0 25 50 1.35 0.21 0.20 0.19 0.18 1.45 TA = 25°C VCC = 5V 1.40 HIGH THRESHOLD 1.30 1.25 LOW THRESHOLD 1.20 1.15 0 2 4 LOW THRESHOLD 1.20 1.15 0 25 50 75 100 125 150 TEMPERATURE (°C) 4210 G21 tOFF(ONLOW) vs Temperature 80 TA = 25°C 70 60 60 tOFF,ONLOW (µs) 70 50 40 30 10 4210 G22 VCC = 5V 30 10 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) VCC = 12V 40 20 0 VCC = 15V 50 20 4 1.25 4210 G20 tOFF(ONLOW) vs Supply Voltage 2 HIGH THRESHOLD 1.30 1.05 –75 –50 –25 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4210 G19 0 1.35 1.10 TEMPERATURE (°C) 80 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) ON Pin Threshold vs Temperature 1.05 75 100 125 150 4 4210 G18 1.10 0.17 2 0 ON PIN THRESHOLD (V) 0.22 ON PIN THRESHOLD (V) 1.40 tOFF,ONLOW (µs) TIMER LOW THRESHOLD (V) 0.23 50 0.18 ON Pin Threshold vs Supply Voltage 1.45 25 0.19 4210 G17 VCC = 5V 0 0.20 TEMPERATURE (°C) TIMER Low Threshold vs Temperature 0.16 –75 –50 –25 0.21 0.16 75 100 125 150 4210 G16 0.24 0.22 0.17 1.22 –75 –50 –25 1.22 TA = 25°C 0.23 TIMER LOW THRESHOLD (V) TIMER HIGH THRESHOLD (V) 1.36 TIMER HIGH THRESHOLD (V) TIMER Low Threshold vs Supply Voltage 0 –75 –50 –25 VCC = 3V 0 25 50 75 100 125 150 TEMPERATURE (°C) 4210 G23 421012f 5 LTC4210-1/LTC4210-2 U W TYPICAL PERFOR A CE CHARACTERISTICS VCB vs Supply Voltage VCB vs Temperature 58 TA = 25°C VCC = 5V 56 56 54 54 52 52 VCB (mV) VCB (mV) 58 50 50 48 48 46 46 44 44 42 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4210 G24 42 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 4210 G25 U U U PI FU CTIO S TIMER (Pin 1): Timer Input Pin. An external capacitor CTIMER sets a 272.9ms/µF initial timing delay and a 21.7ms/ µF circuit breaker delay. The GATE pin turns off whenever the TIMER pin is pulled beyond the COMP2 threshold, such as for overvoltage detection with an external zener. GND (Pin 2): Ground Pin. ON (Pin 3): ON Input Pin. The ON pin comparator has a low-to-high threshold of 1.3V with 80mV hysteresis and a glitch filter. When the ON pin is low, the LTC4210 is reset. When the ON pin goes high, the GATE turns on after the initial timing cycle. GATE (Pin 4): GATE Output Pin. This pin is the high side gate drive of an external N-channel MOSFET. An internal charge pump provides a 10µA pull-up current with Zener clamps to VCC and ground. In overload, the error amplifier (EA) controls the external MOSFET to maintain a constant load current. An external R-C compensation network should be connected to this pin for current limit loop stability. SENSE (Pin 5): Current Limit Sense Input Pin. A sense resistor between the VCC and SENSE pins sets the analog current limit. In overload, the EA controls the external MOSFET gate to maintain the SENSE pin voltage at 50mV below VCC. When the EA is maintaining current limit, the TIMER circuit breaker mode is activated. The current limit loop/circuit breaker mode can be disabled by connecting the SENSE pin to the VCC pin. VCC (Pin 6): Positive Supply Input Pin. The operating supply voltage range is between 2.7V to 16.5V. An undervoltage lockout (UVLO) circuit with a glitch filter resets the LTC4210 when a low supply voltage is detected. 421012f 6 LTC4210-1/LTC4210-2 W BLOCK DIAGRA 6 5 VCC SENSE + – – INITIAL UP/LATCH OFF UVLO CURRENT LIMIT 0.2V + EA 60µA 5µA 50mV GLITCH FILTER + COMP1 CHARGE PUMP – 1 TIMER LOGIC Z1 12V 10µA + GATE COMP2 1.3V SHUTDOWN M5 – 4 Z2 26V INITIAL DOWN/NORMAL GLITCH FILTER 2µA 2 100µA GND COOL OFF COMP3 – + ON 1.3V 3 4210 BD 421012f 7 LTC4210-1/LTC4210-2 U W U U APPLICATIO S I FOR ATIO Hot Circuit Insertion When circuit boards are inserted into live backplanes, the supply bypass capacitors can draw large transient currents from the backplane power bus as they charge. Such transient currents can cause permanent damage to connector pins, glitches on the system supply or reset other boards in the system. The LTC4210 is designed to turn a printed circuit board’s supply voltage ON and OFF in a controlled manner, allowing the circuit board to be safely inserted into or removed from a live backplane. The LTC4210 can reside either on the backplane or on the daughter board for hot circuit insertion applications. Overview The LTC4210 is designed to operate over a range of supplies from 2.7V to 16.5V. Upon insertion, an undervoltage lockout circuit determines if sufficient supply voltage is present. When the ON pin goes high an initial timing cycle assures that the board is fully seated in the backplane before the MOSFET is turned on. A single timer capacitor sets the periods for all of the timer functions. After the initial timing cycle the LTC4210 can either start up in current limit or with a lower load current. Once the external MOSFET is fully enhanced and the supply has ramped up, the LTC4210 monitors the load current through an external sense resistor. Overcurrent faults are actively limited to 50mV/RSENSE for a specified circuit breaker timer limit. The LTC4210-1 will automatically retry after a current limit fault while the LTC4210-2 latches off. The LTC4210-1 timer function limits the retry duty cycle to 3.8% for MOSFET cooling. Undervoltage Lockout An internal undervoltage lockout (UVLO) circuit resets the LTC4210 if the VCC supply is too low for normal operation. The UVLO has a low-to-high threshold of 2.5V, a 100mV hysteresis and a high-to-low glitch filter of 30µs. Above 2.5V supply voltage, the LTC4210 will start if the ON pin conditions are met. A short supply dip below 2.4V for less than 30µs is ignored to allow for bus supply transients. ON Function The ON pin is the input to a comparator which has a lowto-high threshold of 1.3V, an 80mV hysteresis and a highto-low glitch filter of 30µs. A low input on the ON pin resets the LTC4210 TIMER status and turns off the external MOSFET by pulling the GATE pin to ground. A low-to-high transition on the ON pin starts an initial cycle followed by a start-up cycle. A 10k pull-up resistor connecting the ON pin to the supply is recommended. The 10k resistor shunts any potential static charge on the backplane and reduces the overvoltage stress at the ON pin during live insertion. Alternatively, an external resistor divider at the ON pin can be used to program an undervoltage lockout value higher than the internal UVLO circuit. An RC filter can be added at the ON pin to increase the delay time at card insertion if the internal glitch filter delay is insufficient. GATE Function During hot insertion of the PCB, an abrupt application of supply voltage charges the external MOSFET drain/gate capacitance. This can cause an unwanted gate voltage spike. An internal proprietary circuit holds GATE low before the internal circuitry wakes up. This reduces the MOSFET current surges substantially at insertion. The GATE pin is held low in reset mode and during the initial timing cycle. In the start-up cycle the GATE pin is pulled up by a 10µA current source. During an overcurrent fault condition, the error amplifier servoes the GATE pin to maintain a constant current to the load until the circuit breaker trips. When the circuit breaker trips, the GATE pin shuts down abruptly. 421012f 8 LTC4210-1/LTC4210-2 U W U U APPLICATIO S I FOR ATIO Current Limit Circuit Breaker Function CURRENT FLOW TO LOAD The LTC4210 features a current limiting circuit breaker instead of a traditional comparator circuit breaker. When there is a sudden load current surge, such as a low impedance fault, the bus supply voltage can drop significantly to a point where the power to an adjacent card is affected, causing system malfunctions. The LTC4210 fast response error amplifier (EA) instantly limits current by reducing the external MOSFET GATE pin voltage. This minimizes the bus supply voltage drop and permits power budgeting and fault isolation without affecting neighboring cards. A compensation circuit should be connected to the GATE pin for current limit loop stability. Sense Resistor Consideration The nominal fault current limit is determined by a sense resistor connected between VCC and the SENSE pin as given by Equation 1. ILIMIT(NOM) = VCB(NOM) RSENSE(NOM) = 50mV RSENSE(NOM) (1) The power rating of the sense resistor should be rated at the fault current level. Table 2 in the Appendix lists some common sense resistors. For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and the LTC4210 VCC and SENSE pins are strongly recommended. The drawing in Figure 1 illustrates the connections between the LTC4210 and the sense resistor. PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. TRACK WIDTH W: 0.03" PER AMP ON 1 OZ COPPER SENSE RESISTOR CURRENT FLOW TO LOAD W 4210 F01 TO VCC TO SENSE Figure 1. Making PCB Connections to the Sense Resistor Calculating Current Limit For a selected RSENSE, the nominal load current is given by Equation 1. The minimum load current is given by Equation 2: ILIMIT(MIN) = VCB(MIN) RSENSE(MAX) = 44mV RSENSE(MAX) (2) where R RSENSE(MAX) = RSENSE • 1 + TOL 100 The maximum load current is given by Equation 3: ILIMIT(MAX) = VCB(MAX) RSENSE(MIN) = 56mV RSENSE(MIN) (3) where R RSENSE(MIN) = RSENSE • 1 – TOL 100 421012f 9 LTC4210-1/LTC4210-2 U W U U APPLICATIO S I FOR ATIO If a 7mΩ sense resistor with ±1% tolerance is used for current limiting, the nominal current limit is 7.14A. From Equations 2 and 3, ILIMIT(MIN) = 6.22A and ILIMIT(MAX) = 8.08A. For proper operation, the minimum current limit must exceed the circuit maximum operating load current with margin. The sense resistor power rating must exceed VCB(MAX)2/RSENSE(MIN). Frequency Compensation A compensation circuit should be connected to the GATE pin for current limit loop stability. Method 1 The simplest frequency compensation network consists of RC and CC (Figure 2a). The total GATE capacitance is: CGATE = CISS + CC (4) Generally, the compensation value in Figure 2a is sufficient for a pair of input wires less than a foot in length. Applications with longer input wires may require the RC or CC value to be increased for better fault transient performance. For a pair of three foot input wires, users can start with CC = 47nF and RC = 100Ω. Despite the wire length, the general rule for AC stability required is CC ≥ 8nF and RC ≤ 1kΩ. Method 2 The compensation network in Figure 2b is similar to the circuitry used in method 1 but with an additional gate resistor RG. The RG resistor helps to minimize high frequency VIN 5V RSENSE 0.007Ω Q1 Si4410DY + 6 VCC 5 GATE (2a) Method 1 Parasitic MOSFET Oscillation There are two possible parasitic oscillations when the MOSFET operates as a source follower when ramping at power-up or during current limiting. The first type of oscillation occurs at high frequencies, typically above 1MHz. This high frequency oscillation is easily damped with RG as mentioned in method 2. The second type of oscillation occurs at frequencies between 200kHz and 800kHz due to the load capacitance being between 0.2µF and 9µF, the presence of RG and RC resistance, the absence of a drain bypass capacitor, a combination of bus wiring inductance and bus supply output impedance. There are several ways to prevent this second type of oscillation. The simplest way is to avoid load capacitance below 10µF, the second choice is connecting an external CP > 1.5nF. RSENSE 0.007Ω VIN 12V VOUT RC 100Ω CC 10nF VOUT + VCC 4 Q1 Si4410DY 6 CL SENSE LTC4210* parasitic oscillations frequently associated with the power MOSFET. In some applications, the user may find that RG helps in short-circuit transient recovery as well. However, too large of an RG value will slow down the turn-off time. The recommended RG range is between 5Ω and 500Ω. Usually, method 2 is preferred when the input supply voltage is greater than 10V. RG limits the current flow into the GATE pin’s internal zener clamp during transient events. The recommended RC and CC values are the same as method 1. The parasitic compensation capacitor CP is required when 0.2µF < load capacitance CL < 9µF, otherwise it is optional. *ADDITIONAL DETAILS OMITTED FOR CLARITY **USE CP IF 0.2µF < CL < 9µF, OTHERWISE NOT REQUIRED 5 CL SENSE LTC4210* GATE (2b) Method 2 4 RG 200Ω CP** 2.2nF RC 100Ω CC 10nF 4210 F02 Figure 2. Frequency Compensation 421012f 10 LTC4210-1/LTC4210-2 U W U U APPLICATIO S I FOR ATIO Whichever method of compensation is used, board level short-circuit testing is highly recommended as board layout can affect transient performance. Beside frequency compensation, the total gate capacitance CGATE also determines the GATE start-up as in Equation 6. The C GATE should be kept below 0.15µF at high supply operation as the capacitive energy ( 0.5 • CGATE • VGATE2 ) is discharged by the LTC4210 internal pull-down transistor. This prevents the internal pull-down transistor from overheating when the GATE turns off and/or is servoing during current limiting. ends. The 100µA current source then pulls down the TIMER pin until it reaches 0.2V at time point 4. The initial cycle delay (time point 2 to time point 4) is related to CTIMER by equation: tINITIAL ≈ 272.9 • CTIMER ms/µF (5) When the initial cycle terminates, a start-up cycle is activated and the GATE pin ramps high. The TIMER pin continues to be pulled down towards ground. 1 2 3 4 5 6 7 >2.5V Timer Function The TIMER pin handles several key functions with an external capacitor, CTIMER. There are two comparator thresholds: COMP1 (0.2V) and COMP2 (1.3V). The four timing current sources are: VIN >1.3V VON COMP2 100µA COMP1 VTIMER 5µA pull-up 60µA pull-up 2µA pull-down 100µA pull-down The 100µA is a nonideal current source approximating a 7k resistor below 0.4V. Initial Timing Cycle When the card is being inserted into the bus connector, the long pins mate first which brings up the supply VIN at time point 1 of Figure 3. The LTC4210 is in reset mode as the ON pin is low. GATE is pulled low and the TIMER pin is pulled low with a 100µA source. At time point 2, the short pin makes contact and ON is pulled high. At this instant, a start-up check requires that the supply voltage be above UVLO, the ON pin be above 1.3V and the TIMER pin voltage be less than 0.2V. When these three conditions are fulfilled, the initial cycle begins and the TIMER pin is pulled high with 5µA. At time point 3, the TIMER reaches the COMP2 threshold and the first portion of the initial cycle 5µA 10µA VGATE VTH DISCHARGE BY LOAD VOUT 4210 F03 RESET MODE INITIAL CYCLE START-UP CYCLE NORMAL CYCLE Figure 3. Normal Operating Sequence Start-Up Cycle Without Current Limit The GATE is released with a 10µA pull-up at time point 4 of Figure 3. At time point 5, GATE reaches the external MOSFET threshold VTH and VOUT starts to follow the GATE ramp up. If the RSENSE current is below the current limit, the GATE ramps at a constant rate of: ∆VGATE IGATE = ∆T CGATE (6) where CGATE is the total capacitance at the GATE pin. 421012f 11 LTC4210-1/LTC4210-2 U W U U APPLICATIO S I FOR ATIO The current through RSENSE can be divided into two components; ICLOAD due to the total load capacitance (CLOAD) and ILOAD due to the noncapacitive load elements. The capacitive load typically dominates. For a successful start-up without current limit, IRSENSE < ILIMIT: 1 2 3 4 5 >1.3V VON COMP1 (7) 5µA <10µA VGATE VTH DISCHARGE BY LOAD (8) VOUT REGULATED AT 50mV/RSENSE IRSENSE 4210 F04 RESET MODE START-UP CYCLE INITIAL CYCLE NORMAL CYCLE Figure 4. Operating Sequence with Current Limiting at Start-Up Cycle If the duration of the current limit is brief during start-up (Figure 4) and it did not last beyond the circuit breaker function time out, the GATE behaves the same as in startup without current limit except for the time interval between time point 5A and time point 5B. The servo amplifier limits IRSENSE by decreasing the IGATE current (<10µA). During current limiting, the second term in Equation 10 is partly modified from CGATE • VIN/IGATE to CLOAD • VIN/ICLOAD. The start-up time is now given by: tSTARTUP = CGATE • Gate Start-Up Time The start-up time without current limit is given by: (10) VTH + CLOAD • VIN IGATE ICLOAD (11) VTH VIN = CGATE • + CLOAD • IGATE IRSENSE – ILOAD (9) Equations 8 and 9 are applicable but with a lower GATE and VOUT ramp rate. VTH + VIN IGATE V V tSTARTUP = CGATE • TH + CGATE • IN IGATE IGATE 100µA 10µA 10µA Start-Up Cycle With Current Limit tSTARTUP = CGATE • 2µA 100µA 60µA VTIMER At time point 6, VOUT is approximately VIN but GATE rampup continues until it reaches a maximum voltage. This maximum voltage is determined either by the charge pump or the internal clamp. 50mV IRSENSE = ILIMIT = RSENSE 7 COMP2 Due to the voltage follower configuration, the VOUT ramp rate approximately tracks VGATE: ∆VOUT ICLOAD ∆VGATE IGATE = ≈ = ∆T CLOAD ∆T CGATE 5B 6 VIN IRSENSE = ICLOAD + ILOAD < ILIMIT ∆V IRSENSE = C LOAD • OUT + ILOAD < ILIMIT ∆T 5A >2.5V For successful completion of current limit start-up cycle there must be a net current to charge CLOAD and the current limit duration must be less than tCBDELAY. The second term in equation 11 has to fulfill equation 12. C LOAD • VIN < tCBDELAY IRSENSE – ILOAD (12) 421012f 12 LTC4210-1/LTC4210-2 U W U U APPLICATIO S I FOR ATIO Circuit Breaker Timer Operation A When a current limit fault is encountered at time point A in Figure 5, the circuit breaker timing is activated with a 60µA pull-up. The circuit breaker trips at time point B if the fault is still present and the TIMER pin voltage reaches the COMP2 threshold and the LTC4210 shuts down. For a continuous fault, the circuit breaker delay is: CTIMER 60µA t C TIMER (s / µF ) = 1.3V • 1µF (60µA • D) – 2µA (14) When the circuit breaker trips, the GATE pin is pulled low. The TIMER enters latchoff mode with a 5µA pull-up for the LTC4210-2 (latched-off version), while an autoretry “cooloff” cycle begins with a 2µA pull-down for the LTC4210-1 (autoretry version). An autoretry cool-off delay of the LTC4210-1 between COMP2 and COMP1 thresholds takes: tCOOLOFF = 1.1V • CTIMER 2µA LATCHED OFF (5µA PULL-UP) OR RETRY (2µA PULL-DOWN) VTIMER 60µA COMP1 100µA 4210 F05 NORMAL MODE (15) FAULT MODE Figure 5. A Continuous Fault Timing (13) Intermittent overloads may exceed the current limit as in Figure 6, but if the duration is sufficiently short, the TIMER pin may not reach the COMP2 threshold and the LTC4210 will not shut down. To handle this situation, the TIMER discharges with 2µA whenever (VCC – SENSE) voltage is below the 50mV limit and the TIMER voltage is between the COMP1 and COMP2 thresholds. When the TIMER voltage falls below the COMP1 threshold, the TIMER pin is discharged with an equivalent 7k resistor (normal mode, 100µA source) when (VCC – SENSE) voltage is below the 50mV limit. If the TIMER pin does not drop below the COMP1 threshold, any intermittent overload with an aggregate duty cycle of more than 3.8% will eventually trip the circuit breaker. Figure 7 shows the circuit breaker response time in seconds normalized to 1µF. The asymmetric charging and discharging of TIMER is a fair gauge of MOSFET heating. CIRCUIT BREAKER TRIPS COMP2 A1 B1 A2 B2 A3 B3 ~50mV/RSENSE ILOAD COMP2 VTIMER 60µA 60µA 60µA VGATE 10µA 10µA CB FAULT CB FAULT CIRCUIT BREAKER TRIPS COMP1 2µA LATCHED OFF (5µA PULL-UP) OR RETRY (2µA PULL-DOWN) 2µA 4210 F06 CB FAULT Figure 6. Mulitple Intermittent Overcurrent Conditon 1 NORMALIZED RESPONSE TIME (s/µF) tCBDELAY = 1.3V • B t (s/µF) = 1.3V • 1µF CTIMER 60µA • D – 2µA 0.1 0.01 0 10 20 30 40 50 60 70 80 90 100 OVERLOAD DUTY CYCLE, D (%) 4210 F07 Figure 7. Circuit Breaker Timer Response for Intermittent Overload 421012f 13 LTC4210-1/LTC4210-2 U W U U APPLICATIO S I FOR ATIO Autoretry After Current Fault (LTC4210-1) Latch-Off After Current Fault (LTC4210-2) Figure 8 shows the waveforms of the LTC4210-1 (autoretry version) during a circuit breaker fault. At time point B1, the TIMER trips the COMP2 threshold of 1.3V. The GATE pin pulls to ground while TIMER begins a “cool-off” cycle with a 2µA pull-down to the COMP1 threshold of 0.2V. At time point C1, the TIMER pin pulls down with approximately a 7k resistor to ground and a GATE start-up cycle is initiated. If the fault persists, the fault autoretry duty cycle is approximately 3.8%. Pulling the ON pin low for more than 30µs will stop the autoretry function and put the LTC4210 in reset mode. Figure 9 shows the waveforms of the LTC4210-2 (latch-off version) during a circuit breaker fault. At time point B, the TIMER trips the COMP2 threshold. The GATE pin pulls to ground while the TIMER pin is latched high by a 5µA pullup. The TIMER pin eventually reaches the soft-clamped voltage (VCLAMP) of 2.3V. To clear the latchoff mode, the user can either pull the TIMER pin to below 0.2V externally or cycle the ON pin low for more than 30µs. A1 B1 C1 B C VCLAMP COMP2 A2 B2 2µA 2µA 60µA A COMP2 60µA VTIMER 60µA COMP1 VTIMER COMP1 100µA VGATE VGATE 0V VOUT VOUT 0V REGULATING AT 50mV/RSENSE REGULATING AT 50mV/RSENSE ILOAD ILOAD NORMAL MODE CB FAULT COOL OFF CYCLE CB FAULT COOL OFF CYCLE 4210 F08 Figure 8. Automatic Retry After Overcurrent Fault NORMAL MODE LATCHED OFF CYCLE 2410 F09 CB FAULT Figure 9. Latchoff After Overcurrent Fault 421012f 14 LTC4210-1/LTC4210-2 U W U U APPLICATIO S I FOR ATIO Normal Mode/External Timer Control Whenever the TIMER pin voltage drops below the COMP1 threshold, but is not in reset mode, the TIMER enters normal (100µA source) mode with an equivalent 7k resistive pull-down. Table 1 shows the relationship of tINITIAL, tCBDELAY, tCOOLOFF vs CTIMER. If the TIMER pin is pulled beyond the COMP2 threshold, the GATE pin is pulled to ground immediately. This allows the TIMER pin to be used for overvoltage detection, see Figure 11. section OVERVOLTAGE DETECTION USING TIMER PIN for details of the application. Power-Off Cycle The system can be reset by toggling the ON pin low for more than 30µs as shown at time point 7 of Figure 3. The GATE pin is pulled to ground. The TIMER capacitor is also discharged to ground. CLOAD discharges through the load. Alternatively, the TIMER pin can be externally driven above the COMP2 threshold to turn off the GATE pin. Externally forcing the TIMER pin below the COMP1 threshold will reset the TIMER to normal mode. During overvoltage detection, the TIMER’s 100µA pull-down current will continue to be on if (VCC – SENSE) voltage is below 50mV. If the (VCC – SENSE) voltage exceeds 50mV during the overvoltage detection, the TIMER current will be the same as described for latched-off or autoretry mode. See the POWER MOSFET SELECTION Table 1. tINITIAL, tCBDELAY, tCOOLOFF vs CTIMER In addition, the selected MOSFET should fulfill two VGS criteria: CTIMER (µF) tINITIAL (ms) tCBDELAY (ms) tCOOLOFF (ms) 0.033 9.0 0.7 18.2 0.047 12.8 1 25.9 0.068 18.6 1.5 37.4 0.082 22.4 1.8 45.1 0.1 27.3 2.2 55 0.22 60.0 4.8 121 0.33 90.1 7.2 181.5 0.47 128.3 10.2 258.5 0.68 185.6 14.7 374 0.82 223.8 17.8 451 1 272.9 21.7 550 2.2 600.5 47.7 1210 3.3 900.7 71.5 1815 Power MOSFETs can be classified by RDSON at VGS gate drive ratings of 10V, 4.5V, 2.5V and 1.8V. Use the typical curves ∆VGATE vs Supply Voltage and ∆VGATE vs Temperature to determine whether the gate drive voltage is adequate for the selected MOSFET at the operating voltage. 1. Positive VGS absolute maximum rating > LTC4210 maximum ∆VGATE, and 2. Negative VGS absolute maximum rating > supply voltage. The gate of the MOSFET can discharge faster than VOUT when shutting down the MOSFET with a large CLOAD. If one of the conditions cannot be met, an external Zener clamp shown on Figure 10a or Figure 10b can be used. The selection of RG should be within the allowed LTC4210 package dissipation when discharging VOUT via the Zener clamp. 421012f 15 LTC4210-1/LTC4210-2 U W U U APPLICATIO S I FOR ATIO RSENSE VCC RSENSE Q1 VOUT D1* VCC D1* *USER SELECTED VOLTAGE CLAMP (A LOW BIAS CURRENT ZENER DIODE IS RECOMMENDED) 1N4688 (5V) 1N4692 (7V) 1N4695 (9V) 1N4702 (15V) RS 200Ω GATE (10a) Q1 VOUT D2* RS 200Ω GATE (10b) Figure 10. Gate Protection Zener Clamp BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) VIN 5V RSENSE 0.01Ω LONG Z1 SHORT RX Z2 10Ω CX 0.1µF RON2 10k + RB 10k D1 1N4148 RTIMER 18Ω RON1 20k Q1 Si4410DY 3 1 6 VCC ON 5 SENSE GATE LTC4210 TIMER 4 VOUT 5V 4A CLOAD 470µF RG 100Ω R4 100Ω CC 10nF GND GND CTIMER 0.22µF LONG Z1: SMAJ10A 2 GND Z2: BZX84C6V2 4210 F11 Figure 11. Supply Side Overvoltage Protection 421012f 16 LTC4210-1/LTC4210-2 U W U U APPLICATIO S I FOR ATIO A MOSFET with a VGS absolute maximum rating of ±20V meets the two criteria for all the LTC4210 applications ranges from 2.7V to 16.5V. Typically most 10V gate rated MOSFETs have VGS absolute maximum ratings of ±20V or greater, so no external VGS Zener clamp is needed. There are 4.5V gate rated MOSFETs with VGS absolute maximum ratings of ±20V. In addition to the MOSFET gate drive rating and VGS absolute maximum rating, other criteria such as VBDSS, ID(MAX), RDS(ON), PD, θJA, TJ(MAX) and maximum safe operating area should also be carefully reviewed. VBDSS should exceed the maximum supply voltage inclusive of spikes and ringing. ID(MAX) should be greater than the current limit, ILIMIT. RDS(ON) determines the MOSFET VDS which together with VCB yields an error in the VOUT voltage. At 2.7V supply voltage, the total of VDS + VCB of 0.1V yields 3.7% VOUT error. The maximum power dissipated in the MOSFET is ILIMIT2 • RDS(ON) and this should be less than the maximum power dissipation, PD allowed in that package. Given power dissipation, the MOSFET junction temperature, TJ can be computed from the operating temperature (TA) and the MOSFET package thermal resistance (θJA). The operating TJ should be less than the TJ(MAX) specification. Next review the short-circuit condition under maximum supply VIN(MAX) conditions and maximum current limit, ILIMIT(MAX) during the circuit breaker time-out interval of tCBDELAY with the maximum safe operating area of the MOSFET. The operation during output short-circuit conditions must be well within the manufacturer’s recommended safe operating region with sufficient margin. To ensure a reliable design, fault tests should be evaluated in the laboratory. VIN TRANSIENT PROTECTION Unlike most circuits, Hot Swap controllers typically are not allowed the good engineering practice of supply bypass capacitors, since controlling the surge current to bypass capacitors at plug-in is the primary motivation for the Hot Swap controller. Although wire harness, backplane and PCB trace inductances are usually small, these can create large spikes when large currents are suddenly drawn, cut-off or limited. This can cause detrimental damage to board components unless measures are taken. Abrupt intervention can prevent subsequent damage caused by a catastrophic fault but it does cause a large supply transient. The energy stored in the lead/trace inductance is easily controlled with snubbers and/or transient voltage suppressors. Even when ferrite beads are used for electromagnetic interference (EMI) control, the low saturating current of ferrite will not pose a major problem if the transient voltage suppressors with adequate ratings are used. The transient associated with the GATE turn off can be controlled with a snubber and/or transient voltage suppressor. Snubbers such as RC networks are effective especially at low voltage supplies. The choice of RC is usually determined experimentally. The value of the snubber capacitor is usually chosen between 10 to 100 times the MOSFET COSS. The value of the snubber resistor is typically between 3Ω to 100Ω. When the supply exceeds 7V or EMI beads exist in the wire harness, a transient voltage suppressor and snubber are recommended to clip off large spikes and reduce the ringing. For supply voltages of 6V or below, a snubber network should be sufficient to protect against transient voltages. In many cases, a simple short-circuit test can be performed to determine the need of the transient voltage suppressor. OVERVOLTAGE DETECTION USING THE TIMER PIN Figure 11 shows a supply side overvoltage detection circuit. A Zener diode, a diode and COMP2 threshold sets the overvoltage threshold. Resistor RB biases the Zener diode voltage. Diode D1 blocks forward current in the Zener during start-up or output short-circuit. RTIMER with CTIMER sets the overload noise filter. 421012f 17 LTC4210-1/LTC4210-2 U APPE DIX Table 2 lists some current sense resistors that can be used with the circuit breaker. Table 3 lists some power MOSFETs that are available. Table 4 lists the web sites of several manufacturers. Since this information is subject to change, please verify the part numbers with the manufacturer. Table 2. Sense Resistor Selection Guide CURRENT LIMIT VALUE PART NUMBER DESCRIPTION MANUFACTURER 1A LR120601R050 0.05Ω 0.5W 1% Resistor IRC-TT 2A LR120601R025 0.025Ω 0.5W 1% Resistor IRC-TT 2.5A LR120601R020 0.02Ω 0.5W 1% Resistor IRC-TT 3.3A WSL2512R015F 0.015Ω 1W 1% Resistor Vishay-Dale 5A LR251201R010F 0.01Ω 1.5W 1% Resistor IRC-TT 10A WSR2R005F 0.005Ω 2W 1% Resistor Vishay-Dale Table 3. N-Channel Selection Guide CURRENT LEVEL (A) PART NUMBER DESCRIPTION MANUFACTURER 0 to 2 MMDF3N02HD Dual N-Channel SO-8 RDS(ON) = 0.1Ω, CISS = 455pF ON Semiconductor 2 to 5 MMSF5N02HD Single N-Channel SO-8 RDS(ON) = 0.025Ω, CISS = 1130pF ON Semiconductor 5 to 10 MTB50N06V Single N-Channel DD Pak RDS(ON) = 0.028Ω, CISS = 1570pF ON Semiconductor 10 to 20 MTB75N05HD Single N-Channel DD Pak RDS(ON) = 0.0095Ω, CISS = 2600pF ON Semiconductor Table 4. Manufacturers’ Web Sites MANUFACTURER WEB SITE TEMIC Semiconductor www.temic.com International Rectifier www.irf.com ON Semiconductor www.onsemi.com Harris Semiconductor www.semi.harris.com IRC-TT www.irctt.com Vishay-Dale www.vishay.com Vishay-Siliconix www.vishay.com Diodes, Inc. www.diodes.com 421012f 18 LTC4210-1/LTC4210-2 U PACKAGE DESCRIPTIO S6 Package 6-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1636) 0.62 MAX 2.90 BSC (NOTE 4) 0.95 REF 1.22 REF 3.85 MAX 2.62 REF 1.4 MIN 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 – 0.45 6 PLCS (NOTE 3) 0.95 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 (NOTE 3) 1.90 BSC S6 TSOT-23 0302 NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 421012f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC4210-1/LTC4210-2 U TYPICAL APPLICATIO 12V Hot Swap Application BACKPLANE PCB EDGE CONNECTOR CONNECTOR (MALE) (FEMALE) RSENSE 0.01Ω LONG VIN 12V Z1 + RX 10Ω CX 0.1µF 6 VCC SHORT RON1 62k 3 RON2 10k Q1 Si4410DY 1 ON 5 SENSE GATE LTC4210 TIMER 4 VOUT 12V 4A CLOAD 470µF RG 200Ω RC 100Ω CC 10nF GND LONG GND CTIMER 0.22µF 2 GND 4210 TA03 Z1: SMAJ12A RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1421 Two Channel, Hot Swap Controller Operates from 3V to 12V and Supports –12V LTC1422 Single Channel, Hot Swap Controller in SO-8 Operates from 2.7V to 12V, Reset Output LT1640AL/LT1640AH Negative Voltage Hot Swap Controller in SO-8 Operates from –10V to –80V LTC1642 Single Channel, Hot Swap Controller Overvoltage Protection to 33V, Foldback Current Limiting LTC1643AL/LTC1643AH PCI Hot Swap Controller 3.3V, 5V, Internal FETs for ±12V LTC1647 Dual Channel, Hot Swap Controller Operates from 2.7V to 16.5V, Separate ON pins for Sequencing LTC4211 Single Channel, Hot Swap Controller 2.5V to 16.5V, Multifunction Current Control LTC4230 Triple Channel, Hot Swap Controller 1.7V to 16.5V, Multifunction Current Control LTC4251 –48V Hot Swap Controller in SOT-23 Floating Supply, Three-Level Current Limiting LTC4252 –48V Hot Swap Controller in MSOP Floating Supply, Power Good, Three-Level Current Limiting LTC4253 –48V Hot Swap Controller with Triple Supply Sequencing Floating Supply, Three-Level Current Limiting 421012f 20 Linear Technology Corporation LT/TP 0603 1K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2002