LTC4212 Hot Swap Controller with Power-Up Timeout U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®4212 is a Hot SwapTM controller that allows a board to be safely inserted and removed from a live backplane. An internal high side switch driver controls the gate of an external N-channel MOSFET for supply voltages ranging from 2.5V to 16.5V. The LTC4212 provides softstart and inrush current limiting during the start-up period. It features a power-up timeout circuit that disconnects the system supply when the onboard supplies do not enter into regulation within an adjustable timeout period. The controller interfaces with external supply monitor ICs or directly with the PGOOD pin of a DC/DC converter. After normal power-up, a programmable power good glitch filter can be enabled to filter out short term dips in the supplies. Allows Safe Board Insertion and Removal from a Live Backplane Controls Supply Voltages from 2.5V to 16.5V Adjustable Soft-Start with Inrush Current Limiting Fast Turn-Off Time No External Gate Capacitor is Required Power Good Input with Adjustable Timer and Glitch Filter Power-Up Timeout Circuit Interfaces with External Supply Monitors Dual Level Overcurrent Fault Protection Automatic Retry or Latched Mode Operation High Side Drive for an External N-Channel FET MS10 Package Two current limit comparators provide dual level overcurrent circuit breaker protection. The slow comparator trips at VCC – 50mV and activates in 18µs. The fast comparator trips at VCC – 150mV and typically responds in 500ns. U APPLICATIO S ■ ■ ■ Electronic Circuit Breaker Hot Board Insertion and Removal Self-Isolating Hot Swap Boards The LTC4212 can be configured for both latchoff and autoretry applications and is available in a 10-pin MSOP package. , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. U TYPICAL APPLICATIO Hot Swap Controller with Power Good Function EDGE BACKPLANE CONNECTOR CONNECTOR (MALE) (FEMALE) 0.007Ω VCC 5V 5V + 10Ω Z1 10µF + VCC SENSE 10k + 10k 20k PGI 10µF PGT PGF 4.7nF LT1963-3.3 + 10µF 3.3V 1.5A 270pF VCC3 VCCA LTC1727-2.5 COMP2.5 VCC25 COMP3 COMP A GND TIMER 1V/DIV PGI 5V/DIV 4212 TA01a GND ON 5V/DIV PGT 1V/DIV 10k 2.1k 0.01µF + 10µF LTC4212 FAULT GND TIMER 2.5V 1.5A GATE ON FAULT LT1963-2.5 10µF 100nF 10k Power-Up Waveforms Si4410DY 5ms/DIV Z1 = SMAJ10A (TVS) 4212f 1 LTC4212 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) Supply Voltage (VCC) ............................................... 17V Input Voltages ON, PGI ................................................ – 0.3V to 17V SENSE .................................... – 0.3V to (VCC + 0.3V) TIMER, PGT, PGF ....................................– 0.3V to 2V Output Voltages GATE ............................... Internally Limited (Note 3) FAULT .................................................. – 0.3V to 17V Operating Temperature Range LTC4212C .............................................. 0°C to 70°C LTC4212I ........................................... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW ON TIMER PGT PGF GND 1 2 3 4 5 10 9 8 7 6 FAULT VCC SENSE GATE PGI LTC4212CMS LTC4212IMS MS PACKAGE 10-LEAD PLASTIC MSOP MS PART MARKING TJMAX = 125°C, θJA = 200°C/ W LTC5 LTC6 Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, unless otherwise noted. (Note 2) SYMBOL PARAMETER VCC VCC Supply Voltage Range ICC VCC Supply Current ON = High, TIMER = Low ● VLKO Internal VCC Undervoltage Lockout VCC Low-to-High Transition ● VLKOHST VCC Undervoltage Lockout Hysteresis IINON ON Input Current VON = VCC or GND ILEAK FAULT Leakage Current VFAULT = 15V, Pull-Down Device Off IINPGI PGI Pin Input Current VPGI = VCC or GND IINSENSE SENSE Input Current VSENSE = VCC or GND VCB(FAST) SENSE Trip Voltage (VCC – VSENSE) Fast Comparator Trips ● VCB(SLOW) SENSE Trip Voltage (VCC – VSENSE) Slow Comparator Trips ● IGATEUP GATE Pull-Up Current Charge Pump On, VGATE ≤ 0.2V ON Low IGATEDOWN Normal GATE Pull-Down Current CONDITIONS MIN ● TYP MAX UNITS 16.5 V 1 1.5 mA 2.34 2.47 2.5 2.13 110 Fast GATE Pull-Down Current FAULT Latched and Circuit Breaker Tripped or in UVLO, VGATE = 15V ∆VGATE External N-Channel Gate Drive VGATE – VCC (For VCC = 2.5V) VGATE – VCC (For VCC = 2.7V) VGATE – VCC (For VCC = 3.3V) VGATE – VCC (For VCC = 5V) VGATE – VCC (For VCC = 12V) VGATE – VCC (For VCC = 15V), (Note 3) VGATEOV V mV ±1 ±10 µA ±0.1 ±2.5 µA ±1 ±10 µA ±1 ±10 µA 130 150 170 mV 40 50 60 mV ● – 12.5 – 10 – 7.5 µA ● 130 200 270 ● 50 ● ● ● ● ● ● 4.0 4.5 5.0 10 10 8 GATE Overvoltage Lockout Threshold ● 0.08 VONHI ON Threshold High ● VONLO ON Threshold Low ● VPGI Power Good Input Threshold ● VPGIHST Power Good Input Hysterisis µA mA 8 8 10 16 18 15 V V V V V V 0.2 0.3 V 1.23 1.316 1.39 V 0.4 0.455 0.5 V 1.20 1.236 1.26 V 28 mV 4212f 2 LTC4212 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS VPGFHI Power Good Glitch Filter High Threshold VPGFHST Power Good Glitch Filter Hysterisis VPGTHI Power Good Timer High Threshold ● 0.928 0.952 0.976 V VPGTLO Power Good Timer Low Threshold ● 0.640 0.657 0.680 V VPGT∆V Power Good Timer Delta Threshold ● 0.283 0.295 0.304 V IPGT Power Good Timer Pin Current Power Good Timer On, CPGT Charging, PGT = 0.65V Power Good Timer On, CPGT Discharging, PGT = 0.95V Power Good Timer Off, PGT = 1.5V ● ● – 5.61 4.63 – 5.1 5.2 5 – 4.59 5.77 µA µA mA IPGF Power Good Glitch Filter Pin Current Power Good Glitch Filter On, CPGF Charging Power Good Timer Off, PGF = 1.5V ● – 5.61 -5.1 5 – 4.49 µA mA ITMR TIMER Current Timer On, VTIMER = 1V Timer Off, TIMER = 1.5V ● – 2.5 –2 5 – 1.5 µA mA VTMR TIMER Threshold TIMER Low to High TIMER High to Low ● ● 1.20 0.15 1.236 0.200 1.26 0.40 V V VFAULT FAULT Threshold Latched Off Threshold, FAULT High to Low ● 1.20 1.236 1.26 V VFAULTHST FAULT Threshold Hysteresis VOLFAULT Output Low Voltage IFAULT = 1.6mA ● tTO Power Good Time-Out CPGT =10nF, PGT = 0.1V to FAULT Low ● tFAULTLO Power Good Input Low at Time-Out to GATE Discharging End of 14th PGT Cycle tFAULTVG Valid Power Good Glitch to GATE Discharging PGF > 1.26V tFAULTFC FAST COMP Trip to GATE Discharging VCB = 0mV to 200mV Step ● 500 700 ns tFAULTSC SLOW COMP Trip to GATE Discharging VCB = 0mV to 100mV Step ● 10 18 30 µs tEXTFAULT FAULT Low to GATE Discharging VFAULT = 5V to 0V ● 1 3 5 µs tRESET Circuit Breaker Reset Delay Time ON Low to FAULT High ● 120 250 tOFF Turn-Off Time ON Low to GATE Off ● MIN TYP MAX 1.20 1.236 1.26 (Note 4) 40 Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All current into device pins are positive; all current out of device pins are negative; all voltages are referenced to ground unless otherwise specified. V mV 50 16.3 UNITS mV 0.14 0.4 V 18.16 20 ms 1 µs 1.5 µs 10 µs µs Note 3: An internal clamp limits the GATE pin to a minimum of 10V above VCC. Driving this pin to voltages beyond the clamp may damage the part. If a lower GATE pin voltage is desired, use an external zener diode. The GATE capacitance must be < 0.15µF at maximum VCC. Note 4: Guaranteed by design and not tested in production. 4212f 3 LTC4212 U W TYPICAL PERFOR A CE CHARACTERISTICS Specifications are TA = 25°C. VCC = 5V, unless otherwise noted. 4.0 3.5 3.5 2.5 2.0 1.5 1.0 0.5 3.0 2.5 VCC = 16.5V 2.0 1.5 VCC = 5V 1.0 VCC = 2.5V 0.5 0 0 2 4 0 –50 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) UNDERVOLTAGE LOCKOUT THRESHOLD (V) 4.0 3.0 Undervoltage Lockout Threshold vs Temperature Supply Current vs Temperature SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) Supply Current vs Supply Voltage 75 0 25 50 TEMPERATURE (°C) –25 4212 G01 100 2.5 2.4 RISING EDGE 2.3 FALLING EDGE 2.2 2.1 2.0 –50 125 0 50 75 25 TEMPERATURE (°C) –25 100 4212 G03 4212 G02 GATE Voltage vs Supply Voltage GATE Voltage vs Temperature 30 30 25 25 125 VGATE – VCC vs Supply Voltage 18 16 VCC = 16.5V 15 10 20 VGATE – VCC (V) GATE VOLTAGE (V) GATE VOLTAGE (V) 14 20 VCC = 5V 15 10 5 0 0 –50 10 8 6 4 VCC = 2.5V 5 12 2 0 2 4 6 8 10 12 14 SUPPLY VOLTAGE (V) 16 18 0 –25 4212 G06 125 0 12 VCC = 15V 10 VCC = 5V 8 VCC = 3.3V 6 4 2 12 11 10 9 8 7 –25 0 25 50 75 TEMPERATURE (°C) 100 125 4212 G09 6 8 10 12 14 SUPPLY VOLTAGE (V) 16 18 13 GATE OUTPUT SOURCE CURRENT (µA) GATE OUTPUT SOURCE CURRENT (µA) VCC = 12V 14 4 GATE Output Source Current vs Temperature 13 16 2 4212 G08 GATE Output Source Current vs Supply Voltage 18 VGATE – VCC (V) 100 4212 G07 VGATE – VCC vs Temperature 0 –50 75 0 25 50 TEMPERATURE (°C) 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4212 G10 12 11 VCC = 16.5V 10 9 VCC = 2.5V VCC = 5V 8 7 –50 –25 0 50 75 25 TEMPERATURE (°C) 100 125 4212 G11 4212f 4 LTC4212 U W TYPICAL PERFOR A CE CHARACTERISTICS Specifications are TA = 25°C. VCC = 5V, unless otherwise noted. Fast GATE Pull-Down Current vs Supply Voltage Fast GATE Pull-Down Current vs Temperature 60 80 70 60 50 40 30 20 0 2 4 6 8 10 12 14 SUPPLY VOLTAGE (V) 16 58 70 56 VCB (SLOW COMP) (mV) FAST GATE PULL-DOWN CURRENT (mA) 60 50 40 50 48 46 40 100 0 50 75 25 TEMPERATURE (°C) –25 4212 G14 125 SLOW COMP Trips to GATE Discharging Delay vs Supply Voltage 24 24 160 155 150 145 140 135 SLOW COMP TRIPS TO GATE DISCHARGING DELAY (µs) 165 SLOW COMP TRIPS TO GATE DISCHARGING DELAY (µs) 26 22 20 18 16 14 12 130 6 8 10 12 14 SUPPLY VOLTAGE (V) 16 18 2 0 4 6 8 10 12 14 SUPPLY VOLTAGE (V) 4212 G28 700 VCB = 0mV TO 200mV STEP FAST COMP TRIPS TO GATE DISCHARGING DELAY (ns) FAST COMP TRIPS TO GATE DISCHARGING DELAY (ns) 16 400 300 200 100 4 6 8 10 12 14 SUPPLY VOLTAGE (V) 16 VCC = 15V VCC = 5V 18 VCC = 3V 16 14 25 50 0 75 TEMPERATURE (°C) –25 18 500 4212 G32 VCC = 5V 400 VCC = 12V 300 0 –50 125 Power Good Timeout vs Supply Voltage 21 VCC = 3V VCC = 16.5V 200 100 4212 G31 VCB = 0mV TO 200mV STEP 100 0 18 20 10 –50 18 600 500 16 VCC = 16.5V 22 FAST COMP Trips to GATE Discharging Delay vs Temperature 600 2 VCC = 12V 4212 G30 FAST COMP Trips to GATE Discharging Delay vs Supply Voltage 0 6 8 10 12 14 SUPPLY VOLTAGE (V) 12 10 4 4 SLOW COMP Trips to GATE Discharging Delay vs Temperature 26 2 2 4212 G26 170 0 0 4212 G15 VCB (FAST COMP) vs Supply Voltage VCB (FAST COMP) (mV) 52 42 20 –50 18 54 44 30 VCC = 15V POWER GOOD TIME-OUT (ms) FAST GATE PULL-DOWN CURRENT (mA) 80 VCB (SLOW COMP) vs Supply Voltage 20 19 18 17 16 15 –25 25 50 0 75 TEMPERATURE (°C) 100 125 4212 G33 0 2 4 6 8 10 12 14 SUPPLY VOLTAGE (V) 16 18 4212 G40 4212f 5 LTC4212 U W TYPICAL PERFOR A CE CHARACTERISTICS Specifications are TA = 25°C. VCC = 5V, unless PGI Low at Timeout to GATE Discharging vs Supply Voltage 20.0 POWER GOOD TIME-OUT (ms) 19.5 19.0 18.5 18.0 17.5 17.0 16.5 16.0 15.5 15.0 –50 –25 0 50 25 75 TEMPERATURE (°C) 100 125 PGI LOW AT TIME-OUT TO GATE DISCHARGING (V) Power Good Timeout vs Temperature 1.8 1.5 1.2 0.9 0.6 0.3 0 2 4 16 6 8 10 12 14 SUPPLY VOLTAGE (V) 4212 G41 7 6 5 4 3 2 1 0 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 –50 PGF and PGT Pin Current (Timer or Filter Off) vs Temperature 10 9 8 7 PGF 6 PGT 5 4 3 2 1 0 –50 –25 0 50 25 75 TEMPERATURE (°C) 100 1.60 1.55 1.50 1.45 1.40 1.35 1.30 125 0 2.3 1.6 0.35 2.1 1.4 0.5 –50 0.8 0 50 25 75 TEMPERATURE (°C) 100 125 4212 G53 0.20 0.10 IOL = 1mA 0.05 0 –25 18 0.15 0.6 0.2 0.7 16 0.25 1.0 0.4 0.9 8 10 12 14 6 SUPPLY VOLTAGE (V) 0.30 IOL = 5mA VOL (V) FAULT VOL (V) 1.1 4 FAULT VOL vs Temperature 0.40 1.3 2 4212 G52 FAULT VOL vs Supply Voltage 1.2 125 1.65 1.8 1.9 100 1.70 2.5 1.5 50 0 25 75 TEMPERATURE (°C) 4212 G51 Valid Glitch to GATE Discharging vs Temperature 1.7 –25 Valid Glitch to GATE Discharging vs Supply Voltage 4212 G50 VALID GLITCH TO GATE DISCHARGING (µs) 2.0 4212 G45 VALID GLITCH TO GATE DISCHARGING (µs) 8 PGI Low at Timeout to GATE Discharging vs Temperature 4212 G44 PGF AND PGT CURRENT (TIMER OR FILTER OFF) (mA) PGF AND PGT PIN CURRENT (TIMER OR FILTER OFF) (mA) PGF and PGT Pin Current (Timer or Filter Off) vs Supply Voltage 18 PGI LOW AT TIME-OUT TO GATE DISCHARGING (µs) otherwise noted. 0 2 4 6 8 10 12 14 SUPPLY VOLTAGE (V) 16 18 4212 G54 0 –50 –25 75 0 25 50 TEMPERATURE (°C) 100 125 4212 G55 4212f 6 LTC4212 U W TYPICAL PERFOR A CE CHARACTERISTICS Specifications are TA = 25°C. VCC = 5V, unless otherwise noted. FAULT Pin Low to GATE Discharging Time vs Temperature 4.0 3.5 3.0 2.5 2.0 1.5 0 2 4 6 8 10 12 14 SUPPLY VOLTAGE (V) 16 18 200 4.5 4.0 3.5 3.0 2.5 2.0 1.5 –50 180 160 140 120 100 80 0 50 75 25 TEMPERATURE (°C) –25 4212 G58 100 0 125 2 4 6 8 10 12 14 SUPPLY VOLTAGE (V) 16 Turn-Off Time vs Supply Voltage 200 11 180 10 18 4212 G60 4212 G59 Circuit Breaker RESET Time vs Temperature Turn-Off Time vs Temperature 13.0 12.5 160 140 120 12.0 TURN-OFF TIME (µs) TURN-OFF TIME (µs) CIRCUIT BREAKER RESET TIME (µA) Circuit Breaker RESET Time vs Supply Voltage CIRCUIT BREAKER RESET TIME (µs) 4.5 FAULT PIN LOW TO GATE DISCHARGING TIME (µs) FAULT PIN LOW TO GATE DISCHARGING TIME (µs) FAULT Pin Low to GATE Discharging Time vs Supply Voltage 9 8 7 11.0 10.5 10.0 9.5 9.0 6 100 11.5 8.5 80 –50 5 –25 0 50 75 25 TEMPERATURE (°C) 100 125 4212 G61 0 2 4 6 8 10 12 14 SUPPLY VOLTAGE (V) 16 18 4212 G62 8.0 –50 –25 0 50 75 25 TEMPERATURE (°C) 100 125 4212 G63 4212f 7 LTC4212 U U U PI FU CTIO S ON (Pin 1): On/Off Control Input. The ON pin is used to enable and disable LTC4212 operation and reset internal logic and the electronic circuit breaker (ECB). It must be pulled high (>1.316V) to start the first system timing cycle. If the ON pin is pulled low (<0.455V typical) for more than 10µs, the internal logic is reset and the GATE pin is pulled down by a 200µA current to turn off the external FET. If the ON pin is pulled low for more than 120µs, the electronic circuit breaker is reset. This pin is tied to a resistive divider in latch-off applications or to the FAULT pin and an external RC circuit in auto-retry applications. TIMER (Pin 2): System Timer Input. An external capacitor (CTIMER) connected from this pin to ground determines the duration of the first and second system timing cycles. The first timing cycle allows time for the board to be inserted properly. During the second timing cycle, a soft-start circuit controls the gate of the external N-channel FET to limit inrush currents from the backplane supply. PGT (Pin 3): Power Good Timer Input. An external capacitor (CPGT) connected from this pin to ground sets the power good time-out period. This is the maximum time allowed for externally monitored DC/DC converters to power-up into regulation and pull the PGI pin high. The nominal time-out cycle is 1.81s/µF and begins from the end of the second system timing cycle. This pin is pulled to ground by an internal switch when the power good timer is disabled or when the ECB is tripped. PGF (Pin 4): Power Good Glitch Filter Input. An external capacitor (CPGF) connected from this pin to ground determines the power good glitch filter delay. The glitch filter is enabled if the externally monitored DC/DC converters are powered up within the power good time-out period (see Pin␣ 3). If the PGI pin goes low for longer than the filter delay, the ECB is tripped. GND (Pin 5): Device Ground Connection. Connect this pin to the system’s analog ground plane. PGI (Pin 6): Power Good Input Pin. This pin is used by the power good circuit to sense the open drain RST output or comparator outputs of an external supply monitor IC or the PGOOD output of a DC/DC converter. It requires an external pull-up resistor to a voltage above the VFAULT threshold 1.236V. When the power good timer times out (see Pin 3), PGI must be high to avoid tripping the ECB and to enable the power good glitch filter. GATE (Pin 7): Gate Output Pin. The output signal at this pin is the high side gate drive for the external N-channel FET pass transistor. As shown in the Block Diagram, an internal charge pump supplies a 10µA gate current and sufficient gate voltage to drive the external FET for supply voltages from 2.5V to 16.5V. The internal charge pump and zener clamps at the charge pump output determine the gate drive voltage (∆VGATE = VGATE – VCC). The charge pump produces a minimum 4V of ∆VGATE for supplies in the range of 2.5V < VCC < 4.75V. For VCC > 4.75V, the ∆VGATE is limited by zener clamp Z1 connected between the charge pump output and the VCC pin. The ∆VGATE is typically at 12V and with guaranteed minimum value of 10V. For VCC > 15V, the zener clamp Z2 sets the limitation for ∆VGATE. Z2 clamps the gate voltage to ground to 28V typically. The minimum Z2’s clamp voltage is 23V. This effectively sets ∆VGATE to 8V minimum. SENSE (Pin 8): Circuit Breaker Set Pin. With a sense resistor placed in the power path between VCC and SENSE, the LTC4212’s electronic circuit breaker trips if the voltage across the sense resistor exceeds the thresholds set internally for the SLOW COMP and the FAST COMP, as shown in the Block Diagram. The threshold for the SLOW COMP is VCB(SLOW) = 50mV, and the electronic circuit breaker trips if the voltage across the sense resistor exceeds 50mV for 18µs. Under transient conditions where large step current changes can and do occur over shorter periods of time, a second (fast) comparator instead trips the electronic circuit breaker. The threshold for the FAST COMP is set at VCB(FAST) = 150mV, and the circuit breaker trips if the voltage across the sense resistor exceeds 150mV for more than 500ns. To disable the electronic circuit breaker, connect the VCC and SENSE pins together. VCC (Pin 9): This is the positive supply input to the LTC4212. The LTC4212 operates from 2.5V < VCC < 16.5V, and the supply current is typically 1mA. An internal undervoltage lockout circuit disables the device until the voltage at VCC exceeds 2.34V. 4212f 8 LTC4212 U U U PI FU CTIO S FAULT (Pin 10): Open Drain FAULT Output or External FAULT Input. If the FAST COMP, SLOW COMP or the power good circuit trips the ECB, the FAULT pin is latched low. The FAULT pin is an open drain output and is typically connected by a 10k pull-up resistor to VCC. An external circuit can also trip the ECB by driving FAULT below 1.236V (typical). W BLOCK DIAGRA VCC 9 SENSE 8 GATE 7 – COMP7 VCC + UVLO – + – + 50mV Z2 VZ (TYP) = 28V Z1 VZ (TYP) = 12V 0.2V CHARGE PUMP 10µA 150mV tTIMER + 0.2V SLOW COMP + 2µA + – VCC – M3 FAST COMP 200µA COMP3 10µA – 18µS GLITCH FILTER TIMER CB TRIPS OR UVLO 500ns DELAY 2 M6 START-UP CURRENT REGULATOR ON LOW >10µs GATE CHARGING + + COMP4 VREF VREF COMP6 – – FAULT NORMAL 10 1.316V CB TRIPS – ON M2 LOGIC 1.5µs DELAY COMP1 GND + RESET ECB VALID GLITCH DISABLE GLITCH FILTER 5µA COMP5 DISABLE TIMER COMP8 + + – + 120µs VREF VREF 5µA COMP9 – 10µs COMP2 0.455V – – 5 200µA GATE PULLDOWN M5 0.95V 0.65V + 1 M9 M10 M12 M1 5µA M8 VREF = 1.236V 0.2V 4 PGF 6 PGI 3 PGT 0.95V BG 0.65V 4212 BD 4212f 9 LTC4212 U OPERATIO Hot Circuit Insertion When circuit boards are inserted into or removed from live backplanes, the supply bypass capacitors can draw huge transient currents from the backplane power bus as they charge. The transient current can cause permanent damage to the connector pins as well as cause glitches on the system supply, causing other boards in the system to reset. The LTC4212 is designed to turn a printed circuit board’s supply voltages ON and OFF in a controlled manner, allowing the circuit board to be safely inserted or removed from a live backplane. Output Voltage Monitor Unlike other LTC Hot Swap controller products, the LTC4212 does not have an FB pin and monitors onboard DC/DC converters via an external power supply monitor IC such as the LTC1326-2.5 or the LTC1727. This allows several DC/DC converters to be monitored at the same time. The LTC4212’s PGI or power good input pin is used to monitor the RST or comparator outputs of the monitor IC and it can also be tied directly to the PGOOD pin of a DC/DC converter. Undervoltage Lockout The LTC4212’s internal power-on reset circuit initializes the start-up procedure and ensures the IC is in the proper state if the input supply voltage exceeds 2.34V. If the supply voltage falls below 2.23V, the LTC4212 is in undervoltage lockout (UVLO) mode, and the GATE pin is pulled low. Since the UVLO circuitry uses hysteresis, the LTC4212 restarts after the supply voltage rises above 2.34V and the ON pin goes high. In addition, users can utilize the ON comparator (COMP1) or the FAULT comparator (COMP6) to effectively set up a higher undervoltage lockout level. Figure 1 shows the external resistive divider for the ON pin to adjust the system’s undervoltage lockout voltage. The system will enter the plug-in cycle after the ON pin rises above 1.316V. The resistive divider sets the circuit to turn on when VCC reaches around 79% of its final value. If a different turn on VCC voltage is desired change the resistive divider ratio accordingly. The FAULT comparator can also be used to set a higher undervoltage lockout voltage. If the FAULT comparator is used for this purpose, the system will wait for the input voltage to increase above the level set by the user before starting the second timing cycle. Also, if the input voltage drops below the set level in normal operating mode, the electronic circuit breaker (ECB) trips and the user must cycle the ON pin or VCC to restart the system. 3.3V 5V R1 10k 12V R1 20k ON PIN R1 61.9k ON PIN ON PIN R2 10k R2 10k R2 10k (a) VCC = 3.3V (b) VCC = 5V (c) VCC = 12V 4212 F01 Figure 1. ON Pin Sets the Undervoltage Lockout Voltage Externally System Timing System timing for the LTC4212 is generated by the TIMER circuitry (see the Block Diagram). If the LTC4212’s internal timing circuit is off, an internal N-channel FET connects the TIMER pin to GND. If the timing circuit is enabled, an internal 2µA current source is then connected to the TIMER pin to charge CTIMER at a rate given by Equation 1: C TIMER Charge -Up Rate = 2µA C TIMER (1) When the TIMER pin voltage reaches COMP4’s threshold of 1.236V, the TIMER pin is reset to GND. Equation 2 gives an expression for the timer period: tTIMER = 1.236V • C TIMER 2µA (2) As a design aid, the LTC4212’s timer period as a function of the CTIMER using standard values from 3.3nF to 0.33µF is shown in Table 1. The CTIMER value is vital to ensure a proper start-up and reliable operation. This timing period should not be excessive as an output short can occur at start-up causing the external MOSFET to overheat. A good starting point is to 4212f 10 LTC4212 U OPERATIO set CTIMER␣ = 10nF and adjust its value accordingly to suit the specific applications. Table 1. tTIMER vs CTIMER CTIMER tTIMER 0.0033µF 2.0ms 0.0047µF 2.9ms 0.0068µF 4.2ms 0.0082µF 5.1ms 0.01µF 6.2ms 0.015µF 9.3ms 0.022µF 13.6ms 0.033µF 20.4ms 0.047µF 29.0ms 0.068µF 42.0ms 0.082µF 50.7ms 0.1µF 61.8ms 0.15µF 92.7ms 0.22µF 136ms 0.33µF 204ms Power-Up Timeout Circuit The power-up timeout circuit has two functions. During power-up, it trips the circuit breaker if the DC/DC converters on the board do not power-up and do not enter regulation on time. After normal power-up, it is configured to trip the circuit breaker if any of the converters exit regulation for longer than a programmable delay. Once the circuit breaker is tripped, the LTC4212 is latched off and the board is disconnected from the system supply. The ON pin must be taken low for 120µs to reset the circuit breaker and then high to reconnect the board to the backplane supply. The power-up timeout circuit uses three pins: PGI or power good input pin, PGT or power good timer pin and PGF or power good filter pin. It is enabled at the end of the second system timing cycle, provided that the FAULT pin is high. Prior to being enabled or if FAULT is low, the PGT and PGF pins are pulled to GND by internal N-channel FETs, M5 and M12 respectively. When enabled, the power-up timeout circuit starts the power good timer, which generates a time-out period before the PGI pin is sampled. Power Good Timer The timer consists of COMP9, M8-M12, two 5µA current sources and 0.65V and 0.95V threshold voltages for COMP9. The PGI pin is normally connected to the RST output pin or comparator outputs of an external supply monitor IC or to the PGOOD pin of a DC/DC converter and drives a comparator, COMP8 which has a threshold voltage of 1.236V and 28mV of hysterisis. The RST and PGOOD pins are typically open drain pins and require an external pullup resistor. The upper end of the resistor must be connected to a voltage greater than the upper threshold of the PGI comparator (1.236V). A capacitor, CPGT, connected from the PGT pin to ground programs the time-out period generated by the power good timer according to Equation 3. Table 2 shows the power good time-out periods for a list of standard capacitor values. tTIMEOUT = 1.81Ω • CPGT (3) Two 5µA current sources are switched in and out to charge and discharge CPGT between 0.65V and 0.95V for 14 cycles. Table 2. tTIMEOUT vs CPGT CPGT tTIMEOUT 3.3nF 5.97ms 4.7nF 8.51ms 6.8nF 12.3ms 8.2nF 14.8ms 0.01µF 18.1ms 0.022µF 39.8ms 0.033µF 59.7ms 0.047µF 85.1ms 0.068µF 123ms 0.082µF 148ms 0.1µF 181ms 0.22µF 136ms 0.33µF 398ms 0.47µF 851ms 0.68µF 1230ms 0.82µF 1480ms 1µF 1810ms 4212f 11 LTC4212 U OPERATIO Since the PGT is pulled to GND by M12 before the power good circuit is enabled, the first positive ramp at the PGT pin starts from 0V instead of the 0.65V for the subsequent 13 cycles. Power Good Time-Out At the end of the time-out period, the PGI pin is sampled. M12 is turned on to discharge CPGT to ground. If the PGI pin is low when sampled, the DC/DC converters have not entered into regulation on time and the power good circuit trips the circuit breaker to latch off the board. If PGI is high when sampled, the converters powered up into regulation on time and the board is left powered up. The power good glitch filter is enabled and it monitors the PGI pin for a low, an indication that at least one DC/DC converter has dropped out of regulation. The glitch filter rejects low pulses shorter than a programmable period. Table 3. tPGF vs CPGF CPGF tPGF — 5µs 10pF 7.5µs 22pF 10.4µs 33pF 13.2µs 47pF 16.6µs 68pF 21.8µs 82pF 25.2µs 100pF 29.7µs 220pF 59.3µs 330pF 86.6µs 470pF 121.2µs 680pF 173µs 820pF 208µs 1nF 252µs Power Good Glitch Filter Soft-Start or Inrush Current Control A glitch filter consisting of COMP5, M5 and a 5µA current source rejects PGI low pulses that are shorter than the duration programmed by an external capacitor, CPGF, connected from the PGF pin to GND. The LTC4212 monitors the load current by sensing the voltage (VCC – VSENSE) developed across an external sense resistor (RSENSE) connected between the VCC and SENSE pins. During the second timing cycle (see Normal Operating Sequence) a soft-start circuit turns on the external N-channel FET gradually to keep inrush currents in check. The soft-start circuit monitors and servos the voltage across RSENSE to 50mV by either connecting a 10µA pull-up current source to the GATE pin when the voltage across RSENSE is less than 50mV or discharging it with a 10µA pull-down current source when the voltage rises above 50mV. Therefore, the inrush current from the backplane supply is limited to: Once the glitch filter is enabled, M5 is switched off whenever PGI goes low. This allows an internal 5µA current source to charge the capacitor at the PGF pin. If PGI stays low for long enough, the voltage at the PGF pin rises above the upper threshold of COMP5 (1.236V) and causes the power good circuit to trip the circuit breaker. For a given CPGF capacitance connected between PGF and GND, the minimum low PGI pulse width needed to trip the circuit breaker is given by: tPGF = 1.236V • (CPGF)/5µA + 5µs (4) An internal 5pF capacitor and stray MSOP-10 package capacitance sets tPGF to 5µs nominal when CPGF is omitted. Table 3 shows tPGF values for various standard capacitors. Tying the PGF pin to ground prevents the power good glitch filter from tripping the circuit breaker after normal power-up. ILIMIT(SOFTSTART) = 50mV/RSENSE (5) For example, ILIMIT(SOFTSTART) = 5A when RSENSE = 0.01Ω. Assuming that the voltage across the sense resistor does not exceed 50mV, the voltage at the GATE pin rises at rate given by: VGATE Slew Rate = dVGATE/dt =10µA/CGATE (6) where, CGATE = Power MOSFET gate input capacitance (CISS). For example, an Si4410DY (a 30V N-channel power MOSFET) exhibits an approximate CGATE of 3300pF at 4212f 12 LTC4212 U OPERATIO VGS␣ = 10V. From Equation 6, the slew rate is calculated to be 3.03V/ms. The inrush current being delivered to the load while the GATE pin is ramping depends on CLOAD and CGATE. The external N-channel MOSFET acts as a source follower so that its source (load) voltage ramps up at the same rate as the GATE pin. The output current component for capacitor charging is given by Equation 7: IINRUSH = CLOAD • dVGATE/dt =10µA • CLOAD/CGATE (7) where, CLOAD is the total capacitance at the load side of the MOSFET. For example, if C GATE = 3300pF and CLOAD␣ =␣ 2000µF, the inrush current charging CLOAD is 6.06A. Note that the soft-start circuit will servo the inrush to ILIMIT(SOFTSTART) or 5A in this example and dVGATE/dt will be lower than calculated from Equation 6. Frequency Compensation at Soft-Start If the external MOSFET’s gate input capacitance (CISS) is greater than 600pF, no external gate capacitor is required at GATE to stabilize the internal current-limiting loop during soft-start. Otherwise, connect a gate capacitor between the GATE pin and ground to increase the total gate capacitance to be equal to or above 600pF. The servo loop that controls the external MOSFET during current limiting has a unity-gain frequency of about 105kHz and phase margin of 80° for external MOSFET gate input capacitances of up to 2.5nF. Electronic Circuit Breaker The LTC4212 features an electronic circuit breaker function that protects against supply overvoltage, externallygenerated fault conditions, shorts or excessive load current conditions and power good faults. If the circuit breaker trips, the GATE pin is immediately pulled to ground, the external N-channel MOSFET is quickly turned OFF and FAULT is latched low. The circuit breaker trips whenever the voltage across the sense resistor exceeds two different levels, set by the LTC4212’s SLOW COMP and FAST COMP thresholds (see Block Diagram). The SLOW COMP trips the circuit breaker if the voltage across the SENSE resistor (VCC – VSENSE = VCB) is greater than 50mV for 18µs. The FAST COMP trips the circuit breaker to protect against fast load overcurrents if the transient voltage across the sense resistor is greater than 150mV for 500ns. The timing diagram of Figure 2 illustrates when the LTC4212’s electronic circuit breaker is armed. After the first timing cycle, the LTC4212’s FAST COMP is armed at Time Point 6. This ensures that the system is protected against a short-circuit condition during the second timing cycle after CLOAD has been fully charged. At Time Point 8, SLOW COMP is armed when the internal control loop is disengaged. The timing diagram in Figure 4 illustrates the operation of the LTC4212 when the load current conditions exceed the threshold of SLOW COMP (VCB(SLOW) > 50mV). Circuit Breaker Reset Referring to the Block Diagram, the ON pin drives two internal comparators, COMP1 and COMP2. COMP1 is referenced to 1.236V and has a hysterisis of 80mV. COMP2 is referenced to 0.5V and has a hysterisis of 45mV. The outputs of the two comparators drive an internal flipflop to generate a typical high and low ON pin threshold of 1.31V and 0.455V respectively. If the voltage at the ON pin is driven below 0.455V for more than 10µs, all internal control logic except the circuit breaker is reset. A 200µA pull-down current source is connected to the GATE pin to pull it down gradually. Holding the ON pin below 0.455V for 120µs or longer, resets the circuit breaker. Following reset, the ON pin must be taken above 1.316V to start a power-up sequence. Normal Operating Sequence Figure 2 illustrates the normal power-up sequence for two different applications. The PGI (RST) and PGF (RST) waveforms are valid for applications which use the PGI pin to monitor the RST output of a supply monitor IC. The PGI (PGOOD) and PGF (PGOOD) waveforms refer to applications that tie the PGI pin to the PGOOD output of a DC/DC converter. All other waveforms in Figure 2 are common to both applications. The PGI and PGF waveforms for applications that connect PGI pin to the 4212f 13 LTC4212 U OPERATIO CHECK FOR GATE < 0.2V CHECK FOR FAULT HIGH FAST COMP ARMED SLOW COMP & POWER GOOD CIRCUIT ARMED PGI SAMPLED 12 3 4 5 6 7 8 9 10 11 12 13 14 GLITCH FILTER TRIPS BREAKER ON GOES LOW LOGIC RESET (200µA GATE PULLDOWN) CIRCUIT BREAKER RESET 15 16 18 17 19 20 21 2V TO 34V VCC ON VREF VREF TIMER 1ST TIMING CYCLE (CTIMER) 2ND TIMING CYCLE (CTIMER) 1ST TIMING CYCLE (CTIMER) GATE SOFT-START ACTIVE DC/DC CONVERTER OUTPUT VCC FAULT 0.95V PGT 0.65V POWER GOOD TIME-OUT CYCLE (CPGT) PGI (RST) 200ms MONITOR DELAY PGF (RST) 1.236V PGI (PGOOD) 1.236V PGF (PGOOD) NORMAL POWER-UP SEQUENCE POWER GOOD GLITCH FILTER SEQUENCE ECB RESET SEQUENCE 4212 F02 Figure 2. Normal Power-Up, Power Good Glitch Filter and ECB Reset Sequences 4212f 14 LTC4212 U OPERATIO comparator outputs of a supply monitor such as the LTC1727 are similar to PGI (PGOOD) and PGF (PGOOD). First Timing Cycle When the PC board makes contact with the backplane (Time Point 1), VCC starts to rise. While VCC < 2.23V, the LTC4212 is in UVLO mode. The GATE pin is pulled to ground by a 200µA current source to shut off the external N-channel MOSFET and the TIMER, PGT and PGF pins are all pulled low by internal N-channel FETs M6, M5 and M12. When VCC rises above the UVLO threshold of 2.34V (Time Point 2), the LTC4212 waits for the ON pin to go high ( > 1.316V) and checks that the GATE is low (VGATE < 0.2V) before initiating the first timing cycle (Time Point 3). The first timing cycle begins with the TIMER pin up at a rate given by Equation 1. At Time Point 4 (the timing period programmed by CTIMER), the TIMER pin voltage equals VTMR = 1.236V. Next the TIMER pin is pulled down by M6 to Time Point 5 where VTMR = 0.2V. At Time Point 5, the LTC4212 checks that the FAULT pin voltage is high (VFAULT > 1.236V) before initiating the second timing cycle. If FAULT is forced low externally, the second timing cycle will not start and the external N-channel FET stays OFF. applications where PGI monitors the RST output of a supply monitor like the LTC1326-2.5, the RST and therefore the PGI pins are held low for another 200ms until Time Point 11 (see PGI (RST) waveform). At Time Point 12, the power good circuit samples the PGI pin. During normal power-up, PGI will go high before Time Point␣ 12. The power good circuit disables and resets the power good timer and M12 is turned ON to pull PGT to ground. The power good glitch filter is then enabled to monitor the PGI pin. Power Good Glitch Filter Sequence The power good glitch filter sequence is also shown in Figure 2 from Time Points 12 through 16. When the glitch filter is enabled, M5, the internal N-channel FET that shorts the PGF pin to GND is switched OFF whenever PGI is low. This allows the CPGF capacitor to be charged by an internal 5µA current source towards 1.236V. If the PGF pin voltage exceeds 1.236V, the power good circuit trips the circuit breaker to latch the part off. Tying PGF to GND disables the glitch filter and prevents the power good from tripping the circuit breaker after Time Point 12. At the beginning of the second timing cycle (Time Point 6), the LTC4212 FAST COMP is armed and the soft-start circuit is enabled. The GATE pin is ramped up at a rate given by Equation 6. If the inrush current from the backplane supply (Equation 7) is large enough to cause the voltage drop across the sense resistor to exceed 50mV, the softstart circuit activates to regulate the inrush current (Equation 5). The soft-start circuit continues to operate until Time Point 8 when the TIMER pin voltage equals VTMR = 1.236V again. At Time Point 8, SLOW COMP is armed and the power good circuit is enabled. For supply monitors such as the LTC1326-2.5, the glitch filter is less useful. The comparators in the LTC1326-2.5 that monitor the DC/DC converters have a typical propagation delay of 13µs. If any of the monitored supplies leave regulation for more than 13µs, the RST signal will be pulled low until 200ms after all the supplies re-enter regulation. The net effect is that the LTC1326-2.5 performs the glitch filtering and rejects pulses shorter than 13µs. The PGOOD output of a DC/DC converter does not have the 200ms delay of the LTC1326-2.5. Thus any low PGOOD pulse will immediately cause CPGF to be charged towards 1.236V (Time Points 13 and 14). CPGF values can be selected to reject low pulses that are shorter than some desired pulse width. When the power good circuit is enabled, M12, the internal N-channel FET shorting the PGT pin to ground is switched OFF and the power good timer started. The DC/DC converters enter regulation at Time Point 10. In applications where the PGI pin is connected to the PGOOD pin of a DC/ DC converter, PGI is pulled high shortly after the converter enters into regulation (see PGI (PGOOD) waveform). In Some supply monitor ICs such as the LTC1727 provide access to the outputs of comparators monitoring the DC/DC converters as well as the RST output. The comparator outputs track the converter output voltages. If the LTC4212 PGI pin is used to monitor the output of a comparator rather than the RST output of the LTC1727, CPGF can be selected to reject low pulses shorter than a desired pulse width. Second Timing Cycle 4212f 15 LTC4212 U OPERATIO Electronic Circuit Breaker (ECB) Reset Sequence The ECB reset sequence is shown in Figure 2 from Time Points 17 through 19. At Time Point 17, the ON pin is taken low. Ten microseconds later at Time Point 18, the internal logic is reset and a 200µA source is connected to the GATE pin to pull the pin to ground. 120µs after ON goes low (Time Point 19), the ECB is reset. When the ON pin is taken high at Time Point 20 a new first timing cycle is started. If the time from Time Point 17 to Time Point 18 is less than 120µs, the ECB is not reset and taking the ON pin high at Time Point 20 will not start a new first timing cycle. 150mV, SLOW COMP trips the ECB (Time Point 10). If the voltage across RSENSE jumps above 150mV for 500ns or more, FAST COMP will trip the ECB. When the ECB trips, the GATE pin is driven to GND immediately to shut off the external N-channel FET and disconnect the board from the backplane supply. The FAULT pin is latched to a low state and the power good circuit is reset. The PGT and PGF pins are shorted to ground by internal N-channel FETs. In order to reset the fault latch, the ON pin must be taken low for more than 120µs (Time Points 12 to 14). After that, taking the ON pin high (Time Point 15) starts a new power-up sequence. Power Good Timeout Fault Sequence Figure 3 shows a power-up sequence in which the DC/DC converters do not enter regulation on time and the power good trips the ECB. The sequence is the same as for the normal power-up in Figure 2 until Time Point 12 when the power good timer times out and the PGI pin is sampled. Since PGI is low, the power good circuit trips the ECB. The GATE pin is pulled to ground immediately to disconnect power to the board and the FAULT pin is latched to a low state. The PGT and PGF pins are pulled to GND internally by N-channel FETs. To reconnect the board to the backplane supply, the ON pin must be taken low for at least 120µs to reset the ECB and then high again to start a new first timing cycle. Overcurrent Fault Sequence Figure 4 shows a power-up sequence with SLOW COMP tripping the ECB. At the beginning of the second timing cycle (Time Point 6), the GATE pin is connected to the softstart circuit and FAST COMP is armed but it does not usually trip the ECB due to the action of the soft-start circuit on the GATE pin. The soft-start circuit regulates the voltage across the RSENSE resistor to 50mV. At Time Point␣ 8, the soft-start circuit is disconnected. A 10µA current source pulls the GATE pin up and SLOW COMP is armed. If a short occurs and the voltage across RSENSE jumps above 50mV for more than 18µs but is less than Autoretry Sequence Once the circuit breaker trips, the LTC4212 can be configured to autoretry that is attempt to reconnect the backplane supply automatically. Both FAULT and ON pins are tied together to an external pull-up resistor to VCC (RAUTO) and to a delay capacitor (CAUTO) as shown in Figure 5. Figure 6 shows two autoretry sequences caused by a persistent short. When the circuit breaker trips (Time Point 9), an internal N-channel FET at the FAULT pin is turned on to pull the pin low. This discharges the autoretry capacitor, CAUTO towards ground. When the ON pin voltage drops below 0.455V for 10µs (from Time Point 10), internal logic is reset and a 200µA current source is connected to the GATE pin. The GATE pin is already pulled down to ground at Time Point 9. The circuit breaker is not reset so that the FAULT pin continues to discharge CAUTO. After the ON pin has dropped below 0.455V for more than 120µs (Time Point 11), the circuit breaker is reset. The N-channel FET at the FAULT pin is switched off and the pull-up resistor at the ON pin starts to charge CAUTO towards the upper 1.316V threshold of the ON pin. Once the ON pin voltage rises above 1.316V, the first timing cycle is started. The total cooling off period for the external N-channel FET starts at Time Point 9 when the circuit breaker trips to Time Point 15 when the second timing cycle is started. 4212f 16 LTC4212 U OPERATIO 12 CHECK FOR GATE < 0.2V CHECK FOR FAULT HIGH FAST COMP ARMED SLOW COMP & POWER GOOD CIRCUIT ARMED PGI SAMPLED ON GOES LOW LOGIC RESET (200µA GATE PULLDOWN) 3 15 14 4 5 6 7 8 9 10 11 12 13 CIRCUIT BREAKER RESET 16 17 19 2.34V VCC ON VREF VREF VREF TIMER 2ND TIMING CYCLE (CTIMER) 1ST TIMING CYCLE (CTIMER) GATE SOFT-START ACTIVE VOUT DC/DC CONVERTER OUTPUT (RST) < 200ms VOUT DC/DC CONVERTER OUTPUT (PGOOD) VCC FAULT 0.95V PGT 0.65V POWER GOOD TIME-OUT CYCLE (CPGT) PGI PGF POWER GOOD TIMEOUT FAULT SEQUENCE ECB RESET SEQUENCE 4212 F03 Figure 3. Power Good Time-Out Fault and ECB Reset Sequence 4212f 17 LTC4212 U OPERATIO It consists of the time the FAULT pin takes to discharge CAUTO (Time Points 9 to 10), the 120µs needed to reset the circuit breaker (Time Points 9 to 11), the time it takes the pull-up resistor at the ON pin to charge CAUTO above 1.316V (Time Points 11 to 12) and the elapsed time before the external N-channel starts to conduct during the second timing cycle (Time Points 12 to 16). 1 VCC 2 3 4 5 6 Sense Resistor Considerations The fault current level at which the LTC4212’s internal electronic circuit breaker trips is determined by a sense resistor connected between the LTC4212’s VCC and SENSE pins and two separate trip points. The first trip point is set 7 8 9 10 11 12 13 1415 16 2.34V ON VREF VREF VREF TIMER 1ST TIMING CYCLE (CTIMER) 2ND TIMING CYCLE (CTIMER) 1ST TIMING CYCLE (CTIMER) GATE SOFT-START ACTIVE > 50mV, >18µs VCC – VSENSE = 50mV VCC – VSENSE DC/DC CONVERTER OUTPUT VCC FAULT PGT 0.95V 0.65V POWER GOOD TIMER ENABLED (CPGT) PGI PGF 4212 F04 Figure 4. Power-Up with Overcurrent, Slow Comparator Trips the Circuit Breaker 4212f 18 LTC4212 U OPERATIO BACKPLANE EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) RSENSE 0.007Ω VCC 5V RX 10Ω CX 10nF Z1 RAUTO 1M 1 CAUTO 2µF 10 5 M1 Si4410DY 9 8 VCC RG 100Ω SENSE 1 10µF + 1 LTC4212 PGT 3 R5 10k 6 PGI 2 2.5V 1.5A + 10µF 2 + R4 10k FAULT GND TIMER 3 LT1963-2.5 10µF 7 GATE ON CTIMER 0.01µF 5V + PGF CPGT 180nF 4 3 R6 2.1k 3 LT1963-3.3 3.3V 1.5A + 10µF 2 10µF VCC3 VCCA 1 LTC1326-2.5 6 CPGF 18pF RST VCC25 2 GND 4 GND Z1 = SMAJ10A (TVS) 4212 F05 Figure 5. LTC4212 Autoretry Application 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 2.34V VCC 1.316V 1.31V ON 0.455V VREF VREF 0.455V VREF VREF TIMER GATE 1ST TIMING CYCLE (CTIMER) 2ND TIMING CYCLE (CTIMER) 1ST TIMING CYCLE (CTIMER) SOFT-START ACTIVE VCC – VSENSE VCC – VSENSE = 50mV 2ND TIMING CYCLE (CTIMER) SOFT-START ACTIVE > 50mV, > 18µs VCC – VSENSE = 50mV > 50mV, > 18µs DC/DC CONVERTER OUTPUT FAULT PGT PGI 0.95V 0.65V 0.95V 0.65V POWER GOOD TIMER ENABLED (CPGT) POWER GOOD TIMER ENABLED (CPGT) PGF 4212 F06 Figure 6. Autoretry Sequence 4212f 19 LTC4212 U OPERATIO by the SLOW COMP’s threshold, VCB(SLOW) = 50mV, and occurs should a load current fault condition exist for more than 18µs. The current level at which the electronic circuit breaker trips is given by Equation 8: ITRIP(SLOW) = VCB(SLOW) RSENSE = 50mV RSENSE VCB(FAST ) RSENSE = 150mV RSENSE (9) Table 4. ITRIP(SLOW) and ITRIP(FAST) vs RSENSE ITRIP(SLOW) CURRENT FLOW TO LOAD TRACK WIDTH W: 0.03" PER AMP ON 1 OZ COPPER IRC-TT SENSE RESISTOR LR251201R010F OR EQUIVALENT 0.01Ω, 1%, 1W CURRENT FLOW TO LOAD W 4212 F07 TO TO VCC SENSE As a design aid, the currents at which electronic circuit breaker trips for common values for RSENSE are shown in Table 4. RSENSE For a selected RSENSE value, the nominal load current that trips the circuit breaker is given by Equation 10: (8) The second trip point is set by the FAST COMP’s threshold, VCB(FAST) = 150mV, and occurs during fast load current transients that exist for 500ns or longer. The current level at which the circuit breaker trips in this case is given by Equation 9: ITRIP(FAST ) = Calculating Circuit Breaker Trip Current ITRIP(FAST) 0.005Ω 10A 30A 0.006Ω 8.3A 25A 0.007Ω 7.1A 21A 0.008Ω 6.3A 19A 0.009Ω 5.6A 17A 0.01Ω 5A 15A For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and the LTC4212’s VCC and SENSE pins are strongly recommended. The drawing in Figure 7 illustrates the correct way of making connections between the LTC4212 and the sense resistor. PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. The power rating of the sense resistor should accommodate steady-state fault current levels so that the component is not damaged before the circuit breaker trips. Table␣ 5 in the Appendix lists sense resistors that can be used with the LTC4212’s circuit breaker. Figure 7. Making PCB Connections to the Sense Resistor ITRIP(NOM) = VCB(NOM) = RSENSE(NOM) 50mV RSENSE(NOM) (10) The minimum load current that trips the circuit breaker is given by Equation 11. ITRIP(MIN) = VCB(MIN) RSENSE(MAX) = 40mV RSENSE(MAX) (11) where R RSENSE(MAX) = RSENSE(NOM) • 1 + TOL 100 The maximum load current that trips the circuit breaker is given in Equation 12. ITRIP(MAX) = VCB(MAX) RSENSE(MIN) = 60mV RSENSE(MIN) (12) where R RSENSE(MIN) = RSENSE(NOM) • 1 – TOL 100 4212f 20 LTC4212 U OPERATIO For example: If a sense resistor with 7mΩ ±5% RTOL is used for current limiting, the nominal trip current ITRIP(NOM) = 7.1A. From Equations 11 and 12, ITRIP(MIN) = 5.4A and ITRIP(MAX) = 9.02A respectively. For proper operation and to avoid the circuit breaker tripping unnecessarily, the minimum trip current (ITRIP(MIN)) must exceed the circuit’s maximum operating load current. For reliability purposes, the operation at the maximum trip current (ITRIP(MAX)) must be evaluated carefully. If necessary, two resistors with the same RTOL can be connected in parallel to yield an RSENSE(NOM) value that fits the circuit requirements. Power MOSFET Selection Criteria To start the power MOSFET selection process, choose the maximum drain-to-source voltage, VDS(MAX), and the maximum drain current, ID(MAX) of the MOSFET. The VDS(MAX) rating must exceed the maximum input supply voltage (including surges, spikes, ringing, etc.) and the ID(MAX) rating must exceed the maximum short-circuit current in the system during a fault condition. In addition, consider three other key parameters: 1) the required gatesource (VGS) voltage drive, 2) the voltage drop across the drain-to-source on resistance, RDS(ON) and 3) the maximum junction temperature rating of the MOSFET. Power MOSFETs are classified into two categories: standard MOSFETs (RDS(ON) specified at VGS = 10V) and logic-level MOSFETs (RDS(ON) specified at VGS = 5V). The absolute maximum rating for VGS is typically ±20V for standard MOSFETs. However, the VGS maximum rating for logic-level MOSFETs ranges from ±8V to ±20V depending upon the manufacturer and the specific part number. The LTC4212’s GATE overdrive as a function of VCC is illustrated in the Typical Performance curves. Logiclevel MOSFETs are recommended for low supply voltage applications and standard MOSFETs can be used for applications where supply voltage is greater than 4.75V. Note that in some applications, the gate of the external MOSFET can discharge faster than the output voltage when the circuit breaker is tripped. This causes a negative VGS voltage on the external MOSFET. Usually, the selected external MOSFET should have a ±VGS(MAX) rating that is higher than the operating input supply voltage to ensure that the external MOSFET is not destroyed by a negative VGS voltage. In addition, the ±VGS(MAX) rating of the MOSFET must be higher than the gate overdrive voltage. Lower ±VGS(MAX) rating MOSFETs can be used with the LTC4212 if the GATE overdrive is clamped to a lower voltage. The circuit in Figure 8 illustrates the use of zener diodes to clamp the LTC4212’s GATE overdrive signal if lower voltage MOSFETs are used. RSENSE Q1 VCC VOUT D1* D2* RG 200Ω GATE 4212 F08 *USER SELECTED VOLTAGE CLAMP (A LOW BIAS CURRENT ZENER DIODE IS RECOMMENDED) 1N4688 (5V) 1N4692 (7V): LOGIC-LEVEL MOSFET 1N4695 (9V) 1N4702 (15V): STANDARD-LEVEL MOSFET Figure 8. Optional Gate Clamp for Lower VGS(MAX) MOSFETs The RDS(ON) of the external pass transistor should be low to make its drain-source voltage (VDS) a small percentage of VCC. At a VCC = 2.5V, VDS + VRSENSE = 0.1V yields 4% error at the output voltage. This restricts the choice of MOSFETs to very low RDS(ON). At higher VCC voltages, the VDS requirement can be relaxed in which case MOSFET package dissipation (PD and TJ) may limit the value of RDS(ON). Table 6 lists some power MOSFETs that can be used with the LTC4212. For reliable circuit operation, the maximum junction temperature (TJ(MAX)) for a power MOSFET should not exceed the manufacturer’s recommended value. This includes normal mode operation, start-up, current-limit and autoretry mode in a fault condition. Under normal conditions the junction temperature of a power MOSFET is given by Equation 13: MOSFET Junction Temperature, TJ(MAX) ≤ TA(MAX) + θJA • PD (13) 4212f 21 LTC4212 U OPERATIO where PD = (ILOAD )2 • R DS(ON) θJA = junction-to-ambient thermal resistance TA(MAX) = maximum ambient temperature If a short circuit happens during start-up, the external MOSFET can experience a big single pulse energy. This is especially true if the applications only employed a small gate capacitor or no gate capacitor at all. Consult the safe operating area (SOA) curve of the selected MOSFET to ensure that the TJ(MAX) is not exceeded during start-up. Using Staggered Pin Connectors The LTC4212 can be used on either a printed circuit board or on the backplane side of the connector. Printed circuit board edge connectors with staggered pins are recommended as the insertion and removal of circuit boards do sequence the pin connections. Supply voltage and ground connections on the printed circuit board should be wired to the edge connector’s long pins or blades. Control and status signals (like FAULT and ON) passing through the card’s edge connector should be wired to short length pins or blades. PCB Connection Sense There are a number of ways to use the LTC4212’s ON pin to detect whether the printed circuit board has been fully seated in the backplane before the LTC4212 commences a start-up cycle. An example is shown in the schematic on the front page of this data sheet. In this case, the LTC4212 is mounted on the PCB and a 20k/10k resistive divider is connected to the ON pin. On the edge connector, R1 is wired to a short pin. Until the connectors are fully mated, the ON pin is held low, keeping the LTC4212 in an off state. Once the connectors are mated, the resistive divider is connected to VCC, VON > 1.316V and the LTC4212 begins a start-up cycle. PCB Layout Considerations For proper operation of the LTC4212’s circuit breaker function, a 4-wire Kelvin connection to the sense resistors is highly recommended. In Hot Swap applications where load currents can reach 10A or more, narrow PCB tracks exhibit more resistance than wider tracks and operate at more elevated temperatures. Since the sheet resistance of 1 ounce copper foil is approximately 0.54mΩ/square, track resistances add up quickly in high current applications. Thus, to keep PCB track resistance and temperature rise to a minimum, PCB track width must be appropriately sized. Consult Appendix A of LTC Application Note 69 for details on sizing and calculating trace resistances as a function of copper thickness. In the majority of applications, it will be necessary to use plated-through vias to make circuit connections from component layers to power and ground layers internal to the PC board. For 1 ounce copper foil plating, a good starting point is 1A of DC current per via, making sure the via is properly dimensioned so that solder completely fills any void. For other plating thicknesses, check with your PCB fabrication facility. U APPE DIX Table 5 lists some current sense resistors that can be used with the circuit breaker. Table 6 lists some power MOSFETs that are available. Table 7 lists the web sites of several manufacturers. Since this information is subject to change, please verify the part numbers with the manufacturer. Table 5. Sense Resistor Selection Guide CURRENT LIMIT VALUE PART NUMBER DESCRIPTION MANUFACTURER 1A LR120601R050 0.05Ω 0.5W 1% Resistor IRC-TT 2A LR120601R025 0.025Ω 0.5W 1% Resistor IRC-TT 2.5A LR120601R020 0.02Ω 0.5W 1% Resistor IRC-TT 3.3A WSL2512R015F 0.015Ω 1W 1% Resistor Vishay-Dale 5A LR251201R010F 0.01Ω 1.5W 1% Resistor IRC-TT 10A WSR2R005F 0.005Ω 2W 1% Resistor Vishay-Dale 4212f 22 LTC4212 U APPE DIX Table 6. N-Channel Selection Guide CURRENT LEVEL (A) PART NUMBER DESCRIPTION MANUFACTURER 0 to 2 MMDF3N02HD Dual N-Channel SO-8 RDS(ON) = 0.1Ω, CISS = 455pF ON Semiconductor 2 to 5 MMSF5N02HD Single N-Channel SO-8 RDS(ON) = 0.025Ω, CISS = 1130pF ON Semiconductor 5 to 10 MTB50N06V Single N-Channel DD Pak RDS(ON) = 0.028Ω, CISS = 1570pF ON Semiconductor 10 to 20 MTB75N05HD Single N-Channel DD Pak RDS(ON) = 0.0095Ω, CISS = 2600pF ON Semiconductor Table 7. Manufacturers’ Web Sites MANUFACTURER WEB SITE TEMIC Semiconductor www.temic.com International Rectifier www.irf.com ON Semiconductor www.onsemi.com Harris Semiconductor www.semi.harris.com IRC-TT www.irctt.com Vishay-Dale www.vishay.com Vishay-Siliconix www.vishay.com Diodes, Inc. www.diodes.com U PACKAGE DESCRIPTIO MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 10 9 8 7 6 3.20 – 3.45 (.126 – .136) 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 3.00 ± 0.102 (.118 ± .004) (NOTE 4) 4.90 ± 0.152 (.193 ± .006) DETAIL “A” 0.497 ± 0.076 (.0196 ± .003) REF 0° – 6° TYP GAUGE PLANE 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 1 2 3 4 5 0.86 (.034) REF 1.10 (.043) MAX 0.18 (.007) NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX SEATING PLANE 0.17 – 0.27 (.007 – .011) TYP 0.50 (.0197) BSC 0.127 ± 0.076 (.005 ± .003) MSOP (MS) 0603 4212f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC4212 U TYPICAL APPLICATIO Monitoring DC/DC Converters with the LTC1326-2.5 Supply Monitor BACKPLANE EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) RSENSE 0.007Ω VCC 5V R1 10k 1 R3 10k R2 20k FAULT 5V + RX 10Ω CX 100nF Z1 M1 Si4410DY 1 10µF 9 VCC 8 GATE SENSE 2 10µF 2 1 + R4 10k 10 FAULT 5 GND TIMER LT1963-2.5 2.5V 1.5A + 10µF 7 ON CTIMER 0.01µF + 3 LTC4212 PGI PGT PGF 3 4 CPGT 180nF 6 R5 10k R6 2.1k CPGF 18pF LT1963-3.3 10µF 2 3 3 3.3V 1.5A + 10µF VCC3 VCCA 1 LTC1326-2.5 6 RST VCC25 2 GND 4 GND Z1 = SMAJ10A (TVS) 4212 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1421 Two Channels, Hot Swap Controller Operates from 3V to 12V and Supports – 12V LTC1422 Single Channel, Hot Swap Controller Operates from 2.7V to 12V LT1640AL/LT1640AH Negative Voltage Hot Swap Controller Operates from –10V to –80V LTC1642 Single Channel, Hot Swap Controller Overvoltage Protection and Foldback Current Limit LTC1643AL/LTC1643AH PCI-Bus Hot Swap Controller 3.3V, 5V and ±12V for PCI and CPCI LTC1647 Dual Channel, Hot Swap Controller Operates from 2.7V to 16.5V LTC4210-1/LTC4210-2 Single Channel, Hot Swap Controller Hot Swap Controller with Active Current Limiting LTC4211 Single Channel, Hot Swap Controller Overvoltage and Overcurrent Protection LTC4230 Triple Channel, Hot Swap Controller Triple Hot Swap Controller with Multifunction Current Control LTC4241 PCI-Bus Hot Swap Controller With 3.3V Auxiliary Standby Channel LTC4251/LTC4251-1/ LTC4251-2 –48V Voltage Hot Swap Controller Negative Voltage Hot Swap Controller in SOT-23 LTC4252 –48V Hot Swap Controller –48V Hot Swap Controller in 8-Pin or 10-Pin MSOP LTC4253 Triple Power Supply Sequenced –48V Hot Swap Controller –48V Hot Swap Controller with Triple Supply Sequencing in 16-Pin SSOP LT4256-1/LT4256-2 Positive Voltage Hot Swap Controller Operates from 10.8V to 80V, Autoretry/Latch Off 4212f 24 Linear Technology Corporation LT/TP 0304 1K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2003