Final Electrical Specifications LTC1642 Hot Swap Controller May 1999 U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC®1642 is a 16-pin Hot SwapTM controller that allows a board to be safely inserted and removed from a live backplane. Using an external N-channel pass transistor, the board supply voltage can be ramped up at a programmable rate. A high side switch driver controls the N-channel gate for supply voltages ranging from 2.97V to 16.5V. Single Channel Positive NFET Driver Programmable Undervoltage and Overvoltage Protection Foldback Current Limit Adjustable Current Limit Time-Out Latch Off or Automatic Retry on Current Fault Driver for SCR Crowbar on Overvoltage Programmable Reset Timer Reference Output with Uncommitted Comparator VCC: 2.97V to 16.5V Normal Operation, Protected Against Surges to 33V. 16-Pin SSOP Package The SENSE pin allows foldback limiting of the load current, with circuit breaker action after a programmable delay time. The delay allows the part to power-up in current limit. The CRWBR output can be used to trigger an SCR for crowbar load protection after a programmable delay if the input supply exceeds a programmable voltage. The RESET output can be used to generate a system reset with programmable delay when the supply voltage falls below a programmable voltage. The ON pin can be used to cycle the board power. The LTC1642 is available in the 16-pin SSOP package. U APPLICATIO S ■ ■ Hot Board Insertion Electronic Circuit Breaker , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. U TYPICAL APPLICATIO R1 0.010Ω 5% Q1 FDR9410A 12V + C7 0.1µF R5 110k 1% LATCH OFF: FLOAT FAULT AUTOMATIC RETRY: TIE FAULT TO ON 16 VCC 15 14 SENSE GATE 4 UNDERVOLTAGE = 10.8V R6 2.87k 1% OVERVOLTAGE = 13.2V RESET TIME = 200ms CURRENT LIMIT TIME = 20ms CROWBAR TIME = 90µs R7 11.3k 1% D1 1N4148 6 9 FB COMPOUT ON CRWBR LTC1642 COMP– FAULT 5 OV REF BRK TMR 8 2 C3 0.33µF POWER-GOOD = 11.4V 7 1 12 11 COMP+ GND R3 107k 1% C1 0.047µF RESET 10 CLOAD R8 330Ω 5% R2 100Ω 5% Q2 2N2222 13 RST TMR 3 12V AT 2.5A C5 C2 0.1µF 0.33µF C6 0.01µF R9 220Ω 5% Q3 MCR 12DC R4 13k 1% 1642 TA01 R9 REQUIRED ONLY WITH SENSITIVE GATE SCRs, NOT NEEDED WITH MCR12 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 1 LTC1642 U W W W ABSOLUTE AXI U RATI GS U W U PACKAGE/ORDER I FOR ATIO (Note 1) Supply Voltage (VCC) .................................– 0.3V to 33V SENSE Pin ................................... – 0.3V to (VCC + 0.3V) GATE Pin ...................................................– 0.3V to 27V All Other Pins ..........................................– 0.3V to 16.5V Operating Temperature Range LTC1642C ............................................... 0°C to 70°C LTC1642I ............................................ – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C ORDER PART NUMBER TOP VIEW CRWBR 1 16 VCC BRK TMR 2 15 SENSE RST TMR 3 14 GATE ON 4 LTC1642CGN LTC1642IGN 13 REF RESET 5 12 COMP – FAULT 6 11 COMP + FB 7 10 COMPOUT GND 8 9 OV GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 150°C, θJA = 130°C/W Consult factory for Military grade parts. DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V unless otherwise specified. SYMBOL PARAMETER CONDITIONS ICC VCC Supply Current ON = VCC VLKHI VCC Undervoltage Lockout (Low to High) ● VLKLO VCC Undervoltage Lockout (High to Low) ● VLKHYST VCC Undervoltage Lockout Hysteresis VCC Operating Voltage Range VFB FB Pin Voltage Threshold (FB Falling) ∆VFB FB Pin Threshold Line Regulation VFBHST FB Pin Voltage Threshold Hysteresis VOV OV Pin Voltage Threshold (OV Rising) ∆VOV OV Pin Threshold Line Regulation VOVHYST OV Pin Voltage Theshold Hysteresis VRST RST TMR Pin Voltage Threshold (RST TMR Rising) ∆VRST RST TMR Pin Threshold Line Regulation 2.97V ≤ VCC ≤ 16.5V ● IRST RST TMR Pin Current Timer On Timer Off, VRSTTMR = 1.5V ● VBRK BRK TMR Pin Voltage Threshold (BRK TMR Rising) ● ∆VBRK BRK TMR Pin Threshold Line Regulation 2.97V ≤ VCC ≤ 16.5V ● IBRK BRK TMR Pin Current Timer On Timer Off, VBRKTMR = 1.5V ● VCR CRWBR Pin Voltage Theshold ● ∆VCR CRWBR Pin Threshold Line Regulation 2.97V ≤ VCC ≤ 16.5V ● ICR CRWBR Pin Current CRWBR On, VCRWBR = 0V CRWBR On, VCRWBR = 2.1V CRWBR Off, VCRWBR = 1.5V ● ● 2 MIN TYP MAX 1.25 3.0 mA 2.55 2.73 2.95 V 2.35 2.50 2.80 ● 230 2.97 ● 2.97V ≤ VCC ≤ 16.5V 1.208 ● ● 1.208 ● 16.5 1.220 1.232 5 15 1.200 V V mV mV 1.220 1.232 5 15 3 ● V mV 3 2.97V ≤ VCC ≤ 16.5V UNITS V mV mV 1.220 1.250 5 15 mV V – 2.5 –2.0 10 –1.5 µA mA 1.200 1.220 1.250 V 5 15 mV – 30 –20 10 –15 µA mA 375 410 425 mV 4 15 mV – 60 – 45 –1500 2.3 – 30 –1000 µA µA mA LTC1642 DC ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 5V unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP MAX VCB Circuit Breaker Trip Voltage VCB = (VCC – VSENSE), VFB = GND VCB = (VCC – VSENSE), VFB = 1V ● ● 15 45 25 52.5 36 60 mV mV ICP GATE Pin Output Current Charge Pump On, VGATE = GND Charge Pump Off, VGATE = 5V ● – 30 – 25 10 – 20 µA mA ∆VGATE External N-Channel Gate Drive VGATE – VCC, VCC = 3V VGATE – VCC, VCC = 5V VGATE – VCC, VCC = 15V ● ● ● 4.5 10 4.5 5.9 11.5 8.5 8.0 14 18 V V V VONHI ON Pin Threshold (Low to High) 1.30 1.34 1.38 V VONLO ON Pin Threshold (High to Low) 1.20 1.22 1.26 V VONHYST ON Pin Hysteresis VOL Output Low Voltage RESET, FAULT, COMPOUT IO = 1.5mA IPU Logic Output Pull-Up Current RESET, FAULT = GND VREF Reference Output Voltage No Load ● 1.220 1.232 ∆VLNR Reference Line Regulation 2.97V ≤ VCC ≤ 16.5V, No Load ● 5 15 mV ∆VLDR Reference Load Regulation IO = 0mA to –1mA, Sourcing Only ● 2.5 7.5 mV IRSC Reference Short-Circuit Current VREF = 0V VCOS Comparator Offset Voltage VCM = VREF ±10 mV VCHYST Comparator Hysteresis VCM = VREF ● 110 mV 0.4 ● 4.5 ● 3 V µA – 15 1.208 UNITS V mA mV Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. U U U PI FU CTIO S CRWBR (Pin 1): Combination Overvoltage Timer and Crowbar Circuit Trigger. The timer sets the overvoltage time needed to trigger the crowbar circuit. To use the timer connect a capacitor C to ground; the trigger time is 9ms•C(µF). When the timer is off an internal N-channel pulls the pin to ground. The timer is started when the OV comparator trips. A 45µA current source is connected from VCC to the CRWBR pin, and the voltage increases at a rate of 45/C(µF) Volts/second. When the voltage reaches 410mV the current sourced by the pin increases to 1.5mA. Boost this current with an NPN emitter follower to trigger a crowbar SCR. BRK TMR (Pin 2): Analog Timer which Limits the Time the Part Remains In Current Limit. To use the timer connect a capacitor from BRK TMR to ground. BRK TMR is pulled to ground until the sense resistor current reaches its limit, when the pin begins sourcing 20µA and the pin voltage increases at a rate of 20/C(µF) Volts/second. When the pin reaches 1.23V the GATE pin is pulled to ground and the FAULT output is asserted until the chip is reset. To allow the part to remain in current limit indefinitely ground BRK TMR. RST TMR (Pin 3): Analog System Timer. To use the timer connect a capacitor from RST TMR to ground. This timer sets the delay from the ON pin going high to the start of the GATE pin’s ramp; it also sets the delay from output voltage good, as sensed by the FB pin, to RESET going high. When the timer is off, an internal N-channel shorts RST TMR to ground. When the timer is turned on a 2µA current from VCC is connected and the RST TMR pin voltage starts to ramp up at a rate of 2/C(µF) Volts/second. The timer trips when the voltage reaches 1.23V. 3 LTC1642 U U U PI FU CTIO S ON (Pin 4): Control. When ON is low the GATE pin is grounded and FAULT goes high. The GATE pin voltage starts ramping up one RST TMR timing cycle after ON goes high. Pulsing the ON pin low for at least 2µs also resets the chip when it latches off after a sustained overvoltage or current limit. The threshold on a low to high transition is 1.34V with 110mV of hysteresis. RESET (Pin 5): Open Drain Output. RESET is pulled low if the voltage at the FB pin is below its trip point and goes high one timing cycle after the FB voltage exceeds its trip point plus 3mV of hysteresis. RESET has a weak pull-up to one diode drop below VCC; an external resistor can pull the pin above VCC. FAULT (Pin 6): Open Drain Output. FAULT is pulled low when the part latches itself off following a sustained overvoltage or current limit. It goes high 2µs after the ON pin goes low. FAULT has a weak pull-up to one diode drop below VCC; an external resistor can pull the pin above VCC. FB (Pin 7): Noninverting Input to An Analog Comparator; the inverting input is tied to the 1.23V internal reference. The FB comparator can be used with an external resistive divider to monitor the output supply voltage. When the FB voltage is lower than 1.23V the RESET pin is pulled low. RESET goes high one system timing cycle after the voltage at FB exceeds its threshold by 3mV of hysteresis. A low pass filter at the comparator’s output prevents negative voltage glitches from triggering a false reset. GND (Pin 8): Chip Ground. OV (Pin 9): Analog Input Used to Monitor Overvoltages. When the voltage on OV exceeds its trip point the GATE pin is pulled low immediately and the CRWBR timer starts. If OV remains above its trip point (minus 3mV of hysteresis) long enough for CRWBR to reach its trip point the part latches off until reset by pulsing the ON pin low; otherwise, the GATE pin begins ramping up one RST TMR timing cycle after OV goes below its trip point. COMPOUT (Pin 10): Uncommitted Comparator’s Open Drain Output. COMP + (Pin 11): Uncommitted Comparator’s Noninverting Input. 4 COMP – (Pin 12): Uncommitted Comparator’s Inverting Input. REF (Pin 13): The Reference Voltage Output, 1.232V ±2%. To ensure stability the pin should be bypassed with a 0.1µF compensation capacitor. For VCC = 5V it can source 1mA. GATE (Pin 14): High Side Gate Drive for the External N-Channel. An internal charge pump provides at least 4.5V of gate drive, but can only source 25µA. The pin requires an external series RC network to ground to compensate the current limit loop, and to limit the maximum voltage ramp which is dV/dt (V/s) = 25/C(µF). GATE is immediately pulled to ground when the overvoltage comparator trips or the input supply is below the undervoltage lockout trip point. During current limit the GATE voltage is adjusted to maintain constant load current until the BRK TMR pin trips, when the pin is pulled to ground until the chip is reset. SENSE (Pin 15): Current Limit Set. To use the current limit place a sense resistor in the supply path between VCC and SENSE. Should the drop across the resistor exceed a threshold voltage the GATE pin is adjusted to maintain a constant load current and the timer at the BRK TMR pin is started. To protect the external FET from thermal damage the circuit breaker trips after the BRK TMR timing cycle. A foldback feature makes the current limit decrease as the voltage at FB approaches ground. Figure 3 quantifies the relationship. To disable the current limit short SENSE to VCC. VCC (Pin 16): Positive Supply Voltage; between 2.97V and 16.5V in normal operation. An internal undervoltage lockout circuit holds the GATE pin at ground until VCC exceeds 2.73V. If VCC exceeds 16.5V an internal shunt regulator protects the chip from VCC and SENSE pin voltages up to 33V. When the internal shunt regulator is active and the charge pump is on the GATE pin voltage will usually be low but this is not guaranteed; use the OV pin to ensure that the pass device is off. The VCC pin also provides a Kelvin connection to the high side of the SENSE resistor. LTC1642 U U W U APPLICATIO S I FOR ATIO When a circuit board is inserted into a live backplane its supply bypass capacitors can draw large currents from the backplane power bus as they charge. These currents can permanently damage connector pins and can glitch the backplane supply, resetting other boards in the system. The LTC1642 limits the charging currents drawn by a board’s capacitors, allowing safe insertion in a live backplane. Power Supply Ramping In the circuit shown in Figure 1 the LTC1642 and the external N-channel pass transistor Q1 work together to limit charging currents. When power is first applied to VCC the chip holds Q1’s gate at ground. After a programmable delay a 25µA current source begins to charge the external capacitor C2, generating a voltage ramp of 25µA/C2 V/s at the GATE pin. Because Q1 acts as a source follower while its gate ramps, the current charging the board’s bypass capacitance CLOAD is limited to 25µA•CLOAD/C2. An internal charge pump supplies the 25µA gate current, ensuring sufficient gate drive to Q1. At 3V VCC the minimum gate drive is 4.5V; at 5V VCC the minimum is 10V; at 15V VCC the minimum is again 4.5V, due to a Zener clamp from the GATE pin to ground. Resistor R3 limits this Zener’s transient current during board insertion and removal and protects against high frequency FET oscillations. R2 Q1 0.010Ω VIN 12V 2.5A C7 0.1µF 16 VCC R1 10k 4 FDR9410A + 15 SENSE ON GATE R3 100Ω C4 0.33µF R4 330Ω C2 0.047µF BRK TMR RESET RST TMR GND C1 0.33µF 3 CLOAD 14 LTC1642 2 VOUT The delay before the GATE pin voltage begins ramping is determined by the system timer. It comprises an external capacitor C1 from the RST TMR pin to ground; an internal 2µA current source feeding RST TMR from VCC; an internal comparator, with the positive input tied to RST TMR and the negative input tied to the 1.23V reference; and an NMOS pull-down. In standby, the NMOS holds RST TMR at ground; when the timer starts the NMOS turns off and the RST TMR voltage ramps up as the current source charges the capacitor. When RST TMR reaches 1.23V the timer comparator trips; the GATE voltage begins ramping and RST TMR returns to ground. The ramp time ∆t needed to trip the comparator is : ∆t(ms) = 615•C1(µF). VIN RST TMR VOLTS Hot Circuit Insertion GATE SLOPE = 25µA/C(V/s) VOUT TIME 1642 F02 Figure 2. Supply Control Timing Powering-Up In Current Limit Ramping the GATE pin voltage indirectly limits the charging current to I = 25µA•CLOAD/C2, where C2 is the external capacitor connected to the GATE and CLOAD is the load capacitance. If the value of CLOAD is uncertain, then a worst-case design can often result in needlessly long ramp times, and it may be better to limit the charging current directly. 5 Current Limiting and Solid-State Circuit Breaker 8 1642 F01 ALL RESISTORS ±5% UNLESS NOTED RESET DELAY = 200ms SHORT-CIRCUIT DURATION = 20ms Figure 1. Supply Control Circuitry The board current can be limited by connecting a sense resistor between the LTC1642’s VCC and SENSE pins. An internal servo loop adjusts the GATE pin voltage such that Q1 acts as a constant current source if the voltage drop across the sense resistor reaches a limit. The voltage limit across the sense resistor increases as the output charges 5 LTC1642 U W U U APPLICATIO S I FOR ATIO up; this “foldback” limiting tends to keep the power dissipation in the N-channel pass transistor constant. The output voltage is sensed at the FB pin. The limiting sense resistor voltage is 23mV when FB is grounded, but increases gradually to 53mV when FB exceeds 1V; Figure 3 shows the full dependence. When the sense resistor voltage reaches its limit, a circuit breaker timer starts. This timer uses the BRK TMR pin and has a 1.23V threshold. If BRK TMR reaches 1.23V the timer comparator trips, tripping the circuit breaker; if the sense resistor voltage falls below its limit before the comparator trips the GATE voltage begins ramping back up immediately. The ramp time ∆t needed to trip the comparator is ∆t(ms) = 62•C(µF), where C is the external capacitance. Once the circuit breaker trips, GATE and FAULT remain at ground until the chip is restarted. To restart, hold the ON pin low for at least 2µs and FAULT will go high. Then take ON high again and the GATE will ramp up after a system timing cycle. Or, configure the LTC1642 to restart itself after the circuit breaker trips by connecting FAULT to the ON pin. The servo loop controlling Q1 during current limit has a unity-gain frequency of about 125kHz; in Figure 1 R4, together with C2, provide compensation. To ensure stability the product 1/(2•π•R4•C2) should be kept below the unity-gain frequency, and C2 should be more than Q1’s gate-source capacitance. The values shown in Figure 1, 0.047µF and 330Ω, are a starting point. Typical waveforms during a load short to ground are shown in Figure 4. The load is shorted to ground at time 1. The GATE voltage drops until the load current equals its maximum limit, and the circuit breaker timer starts. The short is cleared at time 2, before the timer trips. The BRK TMR pin returns to ground, and the GATE voltage begins ramping up. At time 3 the load is shorted again and at time 4 the timer trips, pulling the GATE to ground and asserting FAULT. Although the short is cleared at time 5, FAULT doesn’t go high until the ON pin is pulled low at time 6. At time 7 ON goes high and the system timer starts. When it trips at time 8 the GATE voltage begins ramping. 6 MAXIMUM SENSE RESISTOR VOLTAGE (mV) 1 70 3 45 7 8 ILIMIT 0A 60 GATE GATE 50 VOUT 40 30 BRK TMR 1.23V 20 FAULT 10 ON 0 0 100 200 300 400 500 600 700 800 900 1000 FB PIN VOLTAGE (mV) 1642 F03 Figure 3. Maximum Sense Resistor Voltage vs FB Voltage 6 ILOAD 2 RST TMR 1.23V 1642 F04 Figure 4. Current Limit and Circuit Breaker Timing LTC1642 U U W U APPLICATIO S I FOR ATIO Automatic Restart After a Current Fault node. The external pull-up resistor at the ON pin may be omitted because FAULT provides a weak pull-up. The LTC1642 will automatically attempt to restart itself after the circuit breaker opens if the FAULT output is tied to the ON pin. The circuit is shown in Figure 5, and the waveforms during a load short in Figure 6. Undervoltage Lockout An internal undervoltage lockout circuit holds the charge pump off until VCC exceeds 2.73V. If VCC falls below 2.5V, it turns off the charge pump and clears overvoltage and current limit faults. During a continuous current limit such as a load short, the N-channel pass transistor’s duty cycle is equal to the circuit breaker timer period, divided by the sum of the circuit breaker and system timer periods. If FAULT is tied to ON then open drain logic should be used to drive the Q1 FDR9410A R2 0.010Ω VIN 12V 2.5A C7 0.1µF 16 VCC R1 4 GATE 14 C4 0.33µF BRK TMR CRWBR RST TMR GND 3 C1 0.33µF 1 R4 330Ω C2 0.047µF FAULT LTC1642 9 OV R5 CLOAD R3 100Ω 6 2 VOUT + 15 SENSE ON For higher lockout thresholds tie the ON pin to a resistor divider driven from VCC, as shown in Figure 7. This circuit keeps the charge pump off until VCC exceeds (1+R1/R5)•1.34V, and also turns it off if VCC falls below (1+R1/R5)•1.23V. 2 3 4 5 6 GATE Q3 MCR 12DC 1 Q2 2N2222 VOUT 8 1.23V BRK TMR C5 1642 F05 ON/FAULT ALL RESISTORS ±5% UNLESS NOTED C4 SHORT-CIRCUIT DUTY CYCLE = = 9% C4 + 10 • C1 1642 F06 Figure 5. Automatic Restart Circuit VIN 12V 2.5A 1.23V RST TMR Figure 6. Automatic Retry Following a Load Short R2 0.010Ω C7 0.1µF 16 VCC R1 464k 1% Q1 FDR9410A VOUT + 15 SENSE CLOAD R3 100Ω LTC1642 UNDERVOLTAGE LOCKOUT THRESHOLD = 10.7V 4 GATE ON 14 C2 0.047µF R5 60.4k 1% RST TMR 3 C1 0.33µF GND 8 R4 330Ω 1642 F07 ALL RESISTORS ±5% UNLESS NOTED Figure 7. Setting a Higher Undervoltage Lockout 7 LTC1642 U W U U APPLICATIO S I FOR ATIO Overvoltage Protection The LTC1642 can protect a load from overvoltages by turning off the pass transistor if the supply voltage exceeds a programmable limit, and by triggering a crowbar SCR if the overvoltage lasts longer than a programmable time. The part can also be configured to automatically restart when the overvoltage clears. The overvoltage protection circuitry is shown in Figure 8. The external components comprise a resistor divider driving the OV pin, timing capacitor C5, NPN emitter follower Q2, and crowbar SCR Q3. Because the MCR12DC is not a sensitive-gate device, the optional resistor shunting the SCR gate to ground is omitted. The internal components comprise a comparator, 1.23V bandgap reference, two current sources, and a timer at the CRWBR pin. When VCC exceeds (1+R1/R5)•1.23V the comparator’s output is high and internal logic pulls the GATE down and starts the timer. This timer has a 0.410V threshold and uses the CRWBR pin; when CRWBR reaches 0.410V the timer comparator trips, and the current sourced from VCC increases to 1.5mA. Emitter follower Q2 boosts this current to trigger crowbar SCR Q3. The ramp time ∆t needed to trip the comparator is : ∆t(ms) = 9.1•C5(µF). Once the CRWBR timer trips the LTC1642 latches off: after the overvoltage clears GATE and FAULT remain at ground and CRWBR continues sourcing 1.5mA. To restart the part after the overvoltage clears, hold the ON pin low for at least 2µs and then bring it high. The GATE voltage will begin ramping up one system timing cycle later. The part will restart itself if FAULT and ON are connected: GATE begins ramping up one system timing cycle after the overvoltage clears. Figure 9 shows typical waveforms when the divider is driven from VCC. The OV comparator goes high at time 1, causing the chip to pull the GATE pin to ground and start the CRWBR timer. At time 2, before the timer’s comparator trips, OV falls below its threshold; the timer resets and GATE begins charging one system timing cycle later at time 3. Another overvoltage begins at time 4, and at time 5 the CRWBR timer trips; FAULT goes low and the CRWBR pin begins sourcing 1.5mA. Even after OV falls below 1.23V at time 6, GATE and FAULT stay low, and CRWBR continues to source 1.5mA. FAULT goes high when ON 8 R2 0.010Ω VIN 12V 2.5A C7 0.1µF R1 127k 1% 9 16 VCC GATE 6 14 R4 330Ω C2 0.047µF Q2 2N2222 ON CRWBR RST TMR 3 CLOAD R3 100Ω LTC1642 FAULT VOUT + 15 SENSE OV R5 12.4k 1% 4 Q1 FDR9410A GND 8 C1 0.33µF 1 Q3 MCR12DC C5 0.01µF ALL RESISTORS ±5% UNLESS NOTED OV COMPARATOR TRIPS AT VIN = 13.85V RESET TIME = 200ms CROWBAR DELAY TIME = 90µs 1642 F08 Figure 8. Overvoltage Protection Circuitry 1 2 3 4 567 8 VCC 0V OV 1.23V 0V GATE 0V VOUT VCC 0.41V CRWBR 1.23V RST TMR ON FAULT 1642 F09 Figure 9. Overvoltage Timing (High Side) LTC1642 U U W U APPLICATIO S I FOR ATIO goes low at time 7, and GATE begins charging at time 8, one RST TMR cycle after FAULT goes high. Figure 10 shows typical waveforms when the OV divider is driven from the N-channel’s low side. Because the voltage driving the divider collapses after the OV comparator trips, FAULT stays high and CRWBR stays near ground, which prevents the pin from triggering an SCR. The GATE voltage begins ramping up after a RST TMR timing cycle. The OV and FB Comparators The propagation delay through the OV and FB comparators on low to high transitions depends strongly on the differential input voltage. The relationship is shown in Figure 11. The minimum propagation delay for large overdrives is about 20µs. In addition the comparators have 3mV of hysteresis. Internal Voltage Clamp Protection Automatic Restart If there is an overvoltage, and the resistor divider feeding OV is connected to the output of the N-channel pass transistor, the LTC1642 will automatically restart even if FAULT is not tied to ON. If the divider is connected to the input side, the LTC1642 will restart itself only if FAULT is tied to ON, and only after the overvoltage clears. 2 3 4 5 67 VCC 0V 1.23V OV 0V GATE VOUT 0.41V CRWBR 1.23V RST TMR FAULT 1642 F10 0V Figure 10. Overvoltage Timing (Low Side) OV COMPARATOR PROPAGATION DELAY (µs) 1 The LTC1642 includes a shunt regulator to protect itself from VCC and SENSE pin voltages up to 33V. The regulator turns on when VCC exceeds 16.5V and limits most of the chip’s circuitry to 15V. When it is on the chip functions normally with one exception: if the charge pump is on, the GATE voltage is usually near ground but this is not guaranteed. Use the OV pin to ensure that GATE is grounded. The pull-up voltage on the RESET and FAULT pins follows VCC until the shunt regulator turns on. When the regulator is on the pull-up voltage is 14.4V. 70 60 50 40 30 20 10 0 0 40 80 120 160 OV OVERDRIVE (mV) 200 240 1642 F11 Figure 11. OV Comparator Propagation Delay vs Overdrive Voltage 9 LTC1642 U W U U APPLICATIO S I FOR ATIO Undervoltage Monitor The LTC1642 will assert RESET if a monitored voltage falls below a programmable minimum. When the monitored voltage has exceeded its minimum for at least one system timing cycle, RESET goes high. The monitoring circuitry comprises an internal 1.23V bandgap reference, an internal precision voltage comparator and an external resistive divider to monitor the output supply voltage. The circuit is shown in Figure 12, and typical waveforms in Figure 13. When the voltage at the FB pin rises above its reset threshold (1.23V), the comparator output goes low and a timing cycle starts (times 1 and 5). Following the cycle RESET is pulled high. At time 2 the voltage at FB drops below the comparator’s threshold and RESET is pulled low. If the FB pin rises above the reset threshold for less than a timing cycle the RESET output will remain low (time 3 to time 4). The 15µA pull-up current source to VCC on RESET has a series diode so the pin can be pulled above VCC by an external pull-up resistor without forcing current back into the supply. R2 0.010Ω VIN 12V 2.5A 16 VCC 4 15 SENSE ON VOUT + CLOAD R3 100Ω GATE 14 R7 95.3k 1% R4 330Ω C2 0.047µF LTC1642 FB RESET 7 R6 12.4k 1% 5 RST TMR GND 3 C1 0.33µF 8 1642 F12 ALL RESISTORS ±5% UNLESS NOTED. FB COMPARATOR TRIPS AT VOUT = 10.7V Figure 12. Undervoltage Monitoring Circuitry 1 V1 Reference The LTC1642’s internal voltage reference is buffered and brought out to the REF pin. The buffer amplifier should be compensated with a capacitor connected between REF and ground. If no DC current is drawn from REF, 0.1µF ensures an adequate phase margin, but the minimum compensation increases if REF sources a substantial DC current, as shown in Figure 14. Q1 FDR9410A 2 V2 3 V1 4 5 V2 VOUT V1 RST TMR RESET 1642 F13 Figure 13. Supply Monitor Waveforms The uncommitted comparator has an open drain output. The comparator has 3mV of hysteresis: the output goes high when the differential input voltage exceeds 1.5mV and goes low when the differential input is less than –1.5mV. MINIMUM REF COMPENSATION (µF) 10.0 Uncommitted Comparator 4.0 2.0 1.0 0.4 0.2 0.1 100µA 1mA REFERENCE CURRENT 10mA 1642 F14 Figure 14. Minimum REF Compensation vs REF Current 10 LTC1642 U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. GN Package 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) 0.189 – 0.196* (4.801 – 4.978) 16 15 14 13 12 11 10 9 0.229 – 0.244 (5.817 – 6.198) 0.150 – 0.157** (3.810 – 3.988) 1 0.015 ± 0.004 × 45° (0.38 ± 0.10) 0.007 – 0.0098 (0.178 – 0.249) 0.009 (0.229) REF 0.053 – 0.068 (1.351 – 1.727) 2 3 4 5 6 7 8 0.004 – 0.0098 (0.102 – 0.249) 0° – 8° TYP 0.016 – 0.050 (0.406 – 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0.008 – 0.012 (0.203 – 0.305) 0.025 (0.635) BSC GN16 (SSOP) 0398 11 LTC1642 U TYPICAL APPLICATIO 5V To 3.3V Hot Swap Supply Using the LTC1430 R9 51Ω 4 Q4 Si4412DY U2 LTC1430CS 7 8 5 6 R10 12k C9 270pF C8 15µF 10V KEMET TANT PVCC2 PVCC1 G2 G1 SHDN FB COMP GND C16 330µF 6.3V KEMET TANT 5 6 7 8 D2 MBR0530T1 C17 330µF 6.3V KEMET TANT + C13 1µF 2 1 L1 3.5µH CDRH1273R5 1 2 3 C15 0.1µF 4 3 5 6 7 8 + 4 Q5 Si4412DY 3.3V OUT AT 5A R11 16.5k 1% D1 MBRS130T3 C18 680pF C7 0.1µF C14 2200pF + C10 330µF 6.3V KEMET TANT 1 2 3 R13 17.4k 1% + C11 330µF 6.3V KEMET TANT + C12 330µF 6.3V KEMET TANT + R12 10.2k 1% R14 12.1k 1% Q1 MTB50N06V R1, 0.005Ω 5V R5 36.5k 1% LATCH OFF: FLOAT FAULT AUTOMATIC RETRY: TIE FAULT TO ON R2 100Ω C6 0.1µF 16 VCC 15 14 SENSE GATE C1 47nF RESET 10 3.3V POWER-GOOD = 3.00V 4 UNDERVOLTAGE = 4.49V R6 2.55k 1% D3 1N4148 U1 LTC1642 ON 6 FAULT 9 OVERVOLTAGE = 5.47V FB COMPOUT R7 11.3k 1% CRWBR GND BRK TMR 8 2 C3 0.33µF 5 5V POWER-GOOD = 4.75V 7 1 12 COMP– COMP OV R3 32.4k 1% R8 330Ω + 11 13 REF RST TMR C4 3 C2 0.1µF 0.33µF Q2 2N2222 Q3 MCR 12DC R4 13k 1% C5 0.01µF 1642 TA02 ALL RESISTORS 5% UNLESS OTHERWISE NOTED RESET TIME = 200ms CURRENT LIMIT TIME =20ms CROWBAR TIME = 90µs RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1421 Hot Swap Controller Multiple Supplies LTC1422 Hot Swap Controller Single Supply in SO-8 LT1640 Negative Voltage Hot Swap Controller Negative High Voltage Supplies LTC1643 PCI-Bus Hot Swap Controller 3.3V, 5V, 12V, –12V Supplies for PCI Bus 12 Linear Technology Corporation 1642is, sn1642 LT/TP 0599 4K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 1999