LTC4211 Hot Swap Controller with Multifunction Current Control U FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DESCRIPTIO The LTC®4211 is a Hot SwapTM controller that allows a board to be safely inserted and removed from a live backplane. An internal high side switch driver controls the gate of an external N-channel MOSFET for supply voltages ranging from 2.5V to 16.5V. The LTC4211 provides softstart and inrush current limiting during the start-up period which has a programmable duration. Allows Safe Board Insertion and Removal from a Live Backplane Controls Supply Voltages from 2.5V to 16.5V Programmable Soft-Start with Inrush Current Limiting, No External Gate Capacitor Required Faster Turn-Off Time Because No External Gate Capacitor is Required Dual Level Overcurrent Fault Protection Programmable Response Time for Overcurrent Protection (MS) Programmable Overvoltage Protection (MS) Automatic Retry or Latched Mode Operation (MS) High Side Drive for an External N-Channel FET User-Programmable Supply Voltage Power-Up Rate FB Pin Monitors VOUT and Signals RESET Glitch Filter Protects Against Spurious RESET Signal Two on-chip current limit comparators provide dual level overcurrent circuit breaker protection. The slow comparator trips at VCC – 50mV and activates in 20µs (or programmed by an external filter capacitor, MS only). The fast comparator trips at VCC – 150mV and typically responds in 300ns. The FB pin monitors the output supply voltage and signals the RESET output pin. The ON pin signal turns the chip on and off and can also be used for the reset function. The MS package has FAULT and FILTER pins to provide additional functions like fault indication, autoretry or latch-off modes, programmable current limit response time and programmable overvoltage protection using an external Zener diode clamp. U APPLICATIO S ■ ■ ■ Electronic Circuit Breaker Hot Board Insertion and Removal (Either On Backplane or On Removable Card) Industrial High Side Switch/Circuit Breaker , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. U TYPICAL APPLICATIO Single Channel 5V Hot Swap Controller BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) VCC 5V Power-Up Sequence RSENSE 0.007Ω LONG Z1* CLOAD 8 7 6 SENSE GATE FB R1 20k 2 LTC4211 ON RESET TIMER PCB CONNECTION SENSE LONG Z1 = 1SMA10A OR SMAJ10A * OPTIONAL 5 3 R3 36k R4 15k R2 10k GND VOUT 5V 5A + RX 10Ω CX 100nF VCC SHORT M1 Si4410DY 1 NO CLOAD VGATE 5V/DIV R5 10k VRESET 5V/DIV µP LOGIC VON 1V/DIV RESET GND CTIMER 10nF VTIMER 1V/DIV 4 GND 4211 TA01A 2.5ms/DIV 4211 TA01b 4211f 1 LTC4211 W W W AXI U U ABSOLUTE RATI GS (Note 1) Supply Voltage (VCC) ............................................... 17V Input Voltage FB, ON .................................................. – 0.3V to 17V SENSE, FILTER .......................... – 0.3V to VCC + 0.3V TIMER .....................................................– 0.3V to 2V Output Voltage GATE ............................... Internally Limited (Note 3) RESET, FAULT ...................................... – 0.3V to 17V Operating Temperature Range LTC4211C .............................................. 0°C to 70°C LTC4211I ........................................... – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C U U W PACKAGE/ORDER I FOR ATIO TOP VIEW RESET 1 8 VCC ON 2 7 SENSE TIMER 3 6 GATE GND 4 5 FB TOP VIEW TOP VIEW RESET ON TIMER GND S8 PACKAGE 8-LEAD PLASTIC SO 8 7 6 5 1 2 3 4 VCC SENSE GATE FB 10 9 8 7 6 1 2 3 4 5 RESET ON FILTER TIMER GND MS8 PACKAGE 8-LEAD PLASTIC MSOP MS PACKAGE 10-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 200°C/ W TJMAX = 125°C, θJA = 200°C/ W TJMAX = 125°C, θJA = 150°C/ W FAULT VCC SENSE GATE FB ORDER PART NUMBER S8 PART MARKING ORDER PART NUMBER MS8 PART MARKING ORDER PART NUMBER MS PART MARKING LTC4211CS8 LTC4211IS8 4211 4211I LTC4211CMS8 LTC4211IMS8 LTSC LTSD LTC4211CMS LTC4211IMS LTSU LTSV Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, unless otherwise noted. (Note 2) SYMBOL PARAMETER VCC VCC Supply Voltage Range ICC VCC Supply Current FB = High, ON = High, TIMER = Low ● VLKO Internal VCC Undervoltage Lockout VCC Low-to-High Transition ● VLKOHST VCC Undervoltage Lockout Hysteresis IINFB FB Input Current VFB = VCC or GND ±1 ±10 µA IINON ON Input Current VON = VCC or GND ±1 ±10 µA ILEAK RESET, FAULT Leakage Current VRESET = VFAULT = 15V, Pull-Down Device Off ±0.1 ±2.5 µA IINSENSE SENSE Input Current VSENSE = VCC or GND ±1 ±10 µA VCB(FAST) SENSE Trip Voltage (VCC – VSENSE) Fast Comparator Trips ● 130 150 170 mV VCB(SLOW) SENSE Trip Voltage (VCC – VSENSE) Slow Comparator Trips ● 40 50 60 mV IGATEUP GATE Pull-Up Current Charge Pump On, VGATE ≤ 0.2V ● –12.5 – 10 –7.5 µA ON Low ● 130 200 270 µA IGATEDOWN Normal GATE Pull-Down Current Fast GATE Pull-Down Current CONDITIONS MIN ● TYP MAX UNITS 16.5 V 1 1.5 mA 2.3 2.47 V 2.5 2.13 120 FAULT Latched and Circuit Breaker Tripped or in UVLO ● 50 mV mA 4211f 2 LTC4211 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are TA = 25°C. VCC = 5V, unless otherwise noted. (Note 2) SYMBOL PARAMETER CONDITIONS MIN ∆VGATE External N-Channel Gate Drive VGATE – VCC (For VCC = 2.5V) VGATE – VCC (For VCC = 2.7V) VGATE – VCC (For VCC = 3.3V) VGATE – VCC (For VCC = 5V) VGATE – VCC (For VCC = 12V) VGATE – VCC (For VCC = 15V) VGATEOV GATE Overvoltage Lockout Threshold VFB FB Voltage Threshold ∆VFB FB Threshold Line Regulation VFBHST FB Voltage Threshold Hysteresis VONHI ON Threshold High ● 1.23 1.316 1.39 VONLO ON Threshold Low ● 1.20 1.236 1.26 VONHST ON Hysteresis IFILTER FILTER Current VFILTER FILTER Threshold ● ● ● ● ● ● 4.0 4.5 5.0 10 10 8 ● 0.08 FB High to Low ● 1.223 2.5V ≤ VCC ≤ 16.5V ● TIMER Current MAX V V V V V V 0.2 0.3 V 1.236 1.248 V 0.5 5 ● –2.5 During Normal and Reset Conditions ● 7 Latched Off Threshold, FILTER Low to High ● 1.20 Timer On, VTIMER = 1V ● – 2.5 V V mV –1.5 µA 10 13 µA 1.236 1.26 V –2 80 Timer Off, TIMER = 1.5V mV mV 80 During Slow Fault Condition UNITS 8 8 10 16 18 18 3 VFILTERHST FILTER Threshold Hysteresis ITMR TYP –2 mV – 1.5 3 µA mA VTMR TIMER Threshold TIMER Low to High ● 1.20 1.236 1.26 V VFAULT FAULT Threshold TIMER High to Low ● 0.15 0.200 0.40 V Latched Off Threshold, FAULT High to Low ● 1.20 1.236 1.26 V VFAULTHST FAULT Threshold Hysteresis VOLFAULT Output Low Voltage IFAULT = 1.6mA ● 0.14 0.4 V VOLRESET Output Low Voltage IRESET = 1.6mA ● 0.14 0.4 V tFAULTFC FAST COMP Trip to GATE Discharging VCB = 0mV to 200mV Step ● 300 700 ns tFAULTSC SLOW COMP Trip to GATE Discharging VCB = 0mV to 100mV Step, 8-Pin Version or FILTER Floating 50 mV ● 10 20 30 µs VCB = 0mV to 100mV Step, 10nF at FILTER Pin to GND ● 4 6 8 ms tEXTFAULT FAULT Low to GATE Discharging VFAULT = 5V to 0V ● 1 3 5 µs tFILTER FILTER High to FAULT Latched VFILTER = 0V to 5V ● 2 4.5 7 µs tRESET Circuit Breaker Reset Delay Time ON Low to FAULT High ● 150 250 tOFF Turn-Off Time ON Low to GATE Off Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All current into device pins are positive; all current out of device pins are negative; all voltages are referenced to ground unless otherwise specified. 8 µs µs Note 3: An internal Zener at the GATE pin clamps the charge pump voltage to a typical maximum operating voltage of 26V. External voltage applied to the GATE pin beyond the internal Zener voltage may damage the part. If a lower GATE pin voltage is desired, use an external Zener diode. The GATE capacitance must be < 0.15µF at maximum VCC. 4211f 3 LTC4211 U W TYPICAL PERFOR A CE CHARACTERISTICS Supply Current vs Supply Voltage 4.0 TA = 25°C 3.5 3.0 SUPPLY CURRENT (mA) 2.5 2.0 1.5 1.0 0.5 3.0 2.5 VCC = 15V 2.0 VCC = 12V 1.5 VCC = 5V 1.0 VCC = 3V 0.5 0 0 2 4 0 –75 –50 –25 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) TA = 25°C LOW THRESHOLD 1.20 1.15 1.10 2 4 25 HIGH THRESHOLD 1.30 LOW THRESHOLD 1.25 1.20 18 25 VGATE – VCC (V) GATE VOLTAGE (V) VCC = 12V 10 0 0 0 25 50 75 100 125 150 TEMPERATURE (°C) 2 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4 4211 G06 VGATE – VCC vs Temperature 18 TA = 25°C 16 16 14 14 12 12 VGATE – VCC (V) VCC = 15V VCC = 3V 10 VGATE – VCC vs Supply Voltage GATE Voltage vs Temperature 15 15 4211 G05 30 VCC = 5V 20 5 1.10 –75 –50 –25 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) TA = 25°C VCC = 5V 4211 G04 20 0 25 50 75 100 125 150 TEMPERATURE (°C) GATE Voltage vs Supply Voltage 1.15 0 2.1 4211 G03 1.35 ON PIN THRESHOLD (V) ON PIN THRESHOLD (V) 1.35 1.30 FALLING EDGE 2.2 30 1.40 HIGH THRESHOLD RISING EDGE 2.3 ON Pin Threshold vs Temperature ON Pin Threshold vs Supply Voltage 1.25 2.4 4211 G02 4211 G01 1.40 2.5 2.0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) GATE VOLTAGE (V) SUPPLY CURRENT (mA) 3.5 UNDERVOLTAGE LOCKOUT THRESHOLD (V) 4.0 Undervoltage Lockout Threshold vs Temperature Supply Current vs Temperature 10 8 6 10 VCC = 12V VCC = 15V 8 VCC = 5V VCC = 3V 6 4 4 2 2 5 0 –75 –50 –25 0 0 25 50 75 100 125 150 TEMPERATURE (°C) 4211 G07 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4211 G08 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 4211 G09 4211f 4 LTC4211 U W TYPICAL PERFOR A CE CHARACTERISTICS GATE Output Source Current vs Supply Voltage 11 10 9 8 7 4 12 11 VCC = 15V 10 VCC = 12V 9 VCC = 3V 8 200 180 160 140 –75 –50 –25 60 50 40 30 20 0 0 25 50 75 100 125 150 TEMPERATURE (°C) FEEDBACK THRESHOLD (V) FEEDBACK THRESHOLD (V) 1.250 HIGH THRESHOLD LOW THRESHOLD 1.235 1.230 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4211 G16 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 2 4 VCC = 5V 60 50 40 30 20 –75 –50 –25 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 0 25 50 75 100 125 150 TEMPERATURE (°C) 4211 G14 TA = 25°C 1.240 4 70 4211 G15 Feedback Threshold vs Temperature 1.245 2 4211 G12 80 70 Feedback Threshold vs Supply Voltage 1.225 160 Fast GATE Pull-Down Current vs Temperature TA = 25°C 4211 G13 1.250 180 0 FAST GATE PULL-DOWN CURRENT (mA) FAST GATE PULL-DOWN CURRENT (mA) NORMAL GATE PULL-DOWN CURRENT (µA) 220 200 Fast GATE Pull-Down Current vs Supply Voltage 80 240 220 4211 G11 Normal GATE Pull-Down Current vs Temperature VCC = 5V TA = 25°C 240 0 25 50 75 100 125 150 TEMPERATURE (°C) 4211 G10 260 260 140 7 –75 –50 –25 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) VCC = 5V FILTER Threshold vs Supply Voltage 1.40 VCC = 5V HIGH THRESHOLD 1.240 1.235 LOW THRESHOLD 1.230 1.225 –75 –50 –25 TA = 25°C 1.35 1.245 FILTER THRESHOLD (V) 2 NORMAL GATE PULL-DOWN CURRENT (µA) 12 0 Normal GATE Pull-Down Current vs Supply Voltage 13 TA = 25°C GATE OUTPUT SOURCE CURRENT (µA) GATE OUTPUT SOURCE CURRENT (µA) 13 GATE Output Source Current vs Temperature 1.30 HIGH THRESHOLD 1.25 1.20 LOW THRESHOLD 1.15 1.10 0 25 50 75 100 125 150 TEMPERATURE (°C) 4211 G17 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4211 G18 4211f 5 LTC4211 U W TYPICAL PERFOR A CE CHARACTERISTICS FILTER Pull-Up Current vs Supply Voltage FILTER Threshold vs Temperature 2.3 VCC = 5V FILTER PULL-UP CURRENT (µA) FILTER THRESHOLD (V) 1.35 1.30 HIGH THRESHOLD 1.25 1.20 LOW THRESHOLD 1.15 1.10 –75 –50 –25 2.3 TA = 25°C 2.2 FILTER PULL-UP CURRENT (µA) 1.40 2.1 2.0 1.9 1.8 1.7 0 0 25 50 75 100 125 150 TEMPERATURE (°C) 2 4 10.0 9.5 9.0 8.5 8.0 11.0 10.5 10.0 9.5 9.0 1.24 1.23 1.22 1.21 1.20 0 0 25 50 75 100 125 150 TEMPERATURE (°C) 1.0 1.25 1.21 0 25 50 75 100 125 150 TEMPERATURE (°C) 4211 G25 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4211 G24 TIMER Low Threshold vs Temperature 1.0 TA = 25°C 0.8 TIMER LOW THRESHOLD (V) VCC = 5V 1.22 2 4211 G23 TIMER LOW THRESHOLD (V) TIMER HIGH THRESHOLD (V) 1.25 TIMER Low Threshold vs Supply Voltage 1.23 TA = 25°C 8.5 8.0 –75 –50 –25 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 1.24 0 25 50 75 100 125 150 TEMPERATURE (°C) TIMER High Threshold vs Supply Voltage 11.5 TIMER High Threshold vs Temperature 1.20 –75 –50 –25 1.8 VCC = 5V 4211 G22 1.26 1.9 4211 G21 TIMER HIGH THRESHOLD (V) FILTER PULL-DOWN CURRENT (µA) FILTER PULL-DOWN CURRENT (µA) 10.5 4 2.0 1.26 12.0 11.0 2 2.1 FILTER Pull-Down Current vs Temperature TA = 25°C 0 2.2 4211 G20 FILTER Pull-Down Current vs Supply Voltage 11.5 VCC = 5V 1.7 –75 –50 –25 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4211 G19 12.0 FILTER Pull-Up Current vs Temperature 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4211 G26 VCC = 5V 0.8 0.6 0.4 0.2 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 4211 G27 4211f 6 LTC4211 U W TYPICAL PERFOR A CE CHARACTERISTICS TIMER Pull-Up Current vs Supply Voltage 2.3 2.20 2.10 2.00 1.90 1.80 1.70 0 2 4 6 VCC = 5V 2.2 2.1 2.0 1.9 1.8 1.7 –75 –50 –25 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 2 1 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) VOL vs Temperature 1.6 VCC = 5V 1.4 RESET OR FAULT 1.2 1.2 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 IOL = 5mA 0.2 0 2 4 IOL = 5mA 0.2 IOL = 1mA 0 0 25 50 75 100 125 150 TEMPERATURE (°C) IOL = 1mA 0 –75 –50 –25 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 0 25 50 75 100 125 150 TEMPERATURE (°C) 4211 G32 4211 G33 VCB (SLOW COMP) vs Temperature VCB (SLOW COMP) vs Supply Voltage 60 TA = 25°C 58 VCB (FAST COMP) vs Supply Voltage 170 VCC = 5V TA = 25°C 165 VCB (SLOW COMP) (mV) 54 52 50 48 46 54 52 50 48 46 44 44 42 42 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4211 G34 VCB (FAST COMP) (mV) 56 56 VCB (SLOW COMP) (mV) 2 4211 G30 TA = 25°C RESET OR FAULT 4211 G31 40 1 0 VOL (V) 4 VOL (V) TIMER PULL-DOWN CURRENT (mA) 5 58 2 VOL vs Supply Voltage 1.4 60 3 0 1.6 VCC = 5V 0 –75 –50 –25 4 4211 G29 TIMER Pull-Down Current vs Temperature 3 TA = 25°C 5 0 25 50 75 100 125 150 TEMPERATURE (°C) 4211 G28 6 TIMER Pull-Down Current vs Supply Voltage TIMER PULL-DOWN CURRENT (mA) TA = 25°C TIMER PULL-UP CURRENT (µA) TIMER PULL-UP CURRENT (µA) 2.30 TIMER Pull-Up Current vs Temperature 40 –75 –50 –25 160 155 150 145 140 135 0 25 50 75 100 125 150 TEMPERATURE (°C) 4211 G35 130 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4211 G36 4211f 7 LTC4211 U W TYPICAL PERFOR A CE CHARACTERISTICS SLOW COMP Response Time vs Supply Voltage 26 SLOW COMP RESPONSE TIME (µs) VCB (FAST COMP) (mV) 165 160 155 150 145 140 135 130 –75 – 50 –25 26 TA = 25°C 8-PIN VERSION OR FILTER FLOATING VCC = 5V 24 22 20 18 16 14 12 10 0 0 25 50 75 100 125 150 TEMPERATURE (°C) 2 800 FAST COMP RESPONSE TIME (ns) FAST COMP RESPONSE TIME (ns) 700 600 500 400 300 200 100 0 0 2 4 VCB = 0mV TO 200mV STEP 700 600 500 VCC = 3V VCC = 12V 400 VCC = 5V 300 200 VCC = 15V 100 0 –75 –50 –25 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4.0 3.5 3.0 –75 –50 –25 4211 G43 12 0 25 50 75 100 125 150 TEMPERATURE (°C) FILTER High to FAULT Activation Time vs Supply Voltage 6.0 TA = 25°C 5.5 5.0 4.5 4.0 3.5 3.0 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4211 G42 Circuit Breaker RESET Time vs Temperature 200 TA = 25°C 180 160 140 120 100 80 0 25 50 75 100 125 150 TEMPERATURE (°C) 14 4211 G39 CIRCUIT BREAKER RESET TIME (µs) CIRCUIT BREAKER RESET TIME (µs) FILTER HIGH TO FAULT ACTIVATION TIME (µs) 200 4.5 16 Circuit Breaker RESET Time vs Supply Voltage VCC = 5V 5.0 VCC = 3V 4211 G41 FILTER High to FAULT Activation Time vs Temperature 5.5 VCC = 5V 18 0 25 50 75 100 125 150 TEMPERATURE (°C) 4211 G40 6.0 VCC = 15V 20 FAST COMP Response Time vs Temperature FAST COMP Response Time vs Supply Voltage TA = 25°C VCB = 0mV TO 200mV STEP VCC = 12V 22 4211 G38 4211 G37 800 8-PIN VERSION OR FILTER FLOATING 24 10 –75 –50 –25 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4 FILTER HIGH TO FAULT ACTIVATION TIME (µs) 170 SLOW COMP Response Time vs Temperature SLOW COMP RESPONSE TIME (µs) VCB (FAST COMP) vs Temperature 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4211 G44 VCC = 5V 180 160 140 120 100 80 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 4211 G45 4211f 8 LTC4211 U W TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C 4.0 3.5 3.0 2.5 2.0 1.5 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4.5 1.50 VCC = 5V 4.0 3.5 3.0 2.5 2.0 1.5 –75 –50 –25 1.25 LOW THRESHOLD 1.20 1.15 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4211 G48 Turn Off Time vs Temperature 11 10 TURN OFF TIME (µs) TURN OFF TIME (µs) VCC = 5V 9 8 7 9 8 7 1.20 6 6 1.15 5 0 25 50 75 100 125 150 TEMPERATURE (°C) 0 2 4 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) GATE Overvoltage Lockout Threshold vs Supply Voltage 0.5 TA = 25°C 0.4 0.3 0.2 0.1 0 0 2 4 5 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 4211 G50 4211 G49 6 8 10 12 14 16 18 20 SUPPLY VOLTAGE (V) 4211 G52 4211 G51 GATE Overvoltage Lockout Threshold vs Temperature GATE OVERVOLTAGE LOCKOUT THRESHOLD (V) 1.10 –75 – 50 –25 GATE OVERVOLTAGE LOCKOUT THRESHOLD (V) FAULT THRESHOLD VOLTAGE (V) 1.35 LOW THRESHOLD HIGH THRESHOLD 0 10 1.25 1.30 1.10 TA = 25°C VCC = 5V 1.45 HIGH THRESHOLD 1.35 Turn Off Time vs Supply Voltage 11 1.30 1.40 4211 G47 FAULT Threshold Voltage vs Temperature 1.40 TA = 25°C 1.45 0 25 50 75 100 125 150 TEMPERATURE (°C) 4211 G46 1.50 FAULT Threshold Voltage vs Supply Voltage FAULT THRESHOLD VOLTAGE (V) 4.5 FAULT Pin Low to GATE Discharging Time vs Temperature FAULT PIN LOW TO GATE DISCHARGING TIME (µs) FAULT PIN LOW TO GATE DISCHARGING TIME (µs) FAULT Pin Low to GATE Discharging Time vs Supply Voltage 0.5 VCC = 5V 0.4 0.3 0.2 0.1 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 4211 G53 4211f 9 LTC4211 U U U PI FU CTIO S (8-Lead Package/10-Lead Package) RESET (Pin 1/Pin 1): An open-drain N-channel MOSFET whose source connects to GND (Pin 4/Pin 5). This pin pulls low if the voltage at the FB pin (Pin 5/Pin 6) falls below the FB pin threshold (1.236V). During the start-up cycle, the RESET pin goes high impedance at the end of the second timing cycle after the FB pin goes above the FB threshold. This pin requires an external pull-up resistor to VCC. If an undervoltage lockout condition occurs, the RESET pin pulls low independently of the FB pin to prevent false glitches. ON (Pin 2/Pin 2): An active high signal used to enable or disable LTC4211 operation. COMP1’s threshold is set at 1.236V and its hysteresis is set at 80mV. If a logic high signal is applied to the ON pin (VON > 1.316V), the first timing cycle begins if an overvoltage condition does not exist on the GATE pin (Pin 6/Pin 7). If a logic low signal is applied to the ON pin (VON < 1.236V), the GATE pin is pulled low by an internal 200µA current sink. The ON pin can also be used to reset the electronic circuit breaker. If the ON pin is cycled low and then high following a circuit breaker trip, the internal circuit breaker is reset, and the LTC4211 begins a new start-up cycle. TIMER (Pin 3/Pin 4): A capacitor connected from this pin to GND sets the LTC4211’s system timing. The LTC4211’s initial and second start-up timing cycles and its internal “power good” delay time are defined by this capacitor. GND (Pin 4/Pin 5): Device Ground Connection. Connect this pin to the system’s analog ground plane. FB (Pin 5/Pin 6): The FB (Feedback) pin is an input to the COMP2 comparator and monitors the output supply voltage through an external resistor divider. If VFB < 1.236V, the RESET pin pulls low. An internal glitch filter at COMP2’s output helps prevent negative voltage transients from triggering a reset condition. If VFB > 1.239V, the RESET pin goes high after one timing cycle. GATE (Pin 6/Pin 7): The output signal at this pin is the high side gate drive for the external N-channel FET pass transistor. As shown in the Block Diagram, an internal charge pump supplies a 10µA gate current and sufficient gate voltage drive to the external FET for supply voltages from 2.5V to 16.5V. The internal charge-pump and zener clamps at the GATE pin determine the gate drive voltage (∆VGATE = VGATE – VCC). The charge pump produces a minimum 4V of ∆VGATE for supplies in the range of 2.5V < VCC < 4.75V. For VCC > 4.75V, the ∆VGATE is limited by zener clamp Z1 connecting between GATE and VCC pins. The ∆VGATE is typically at 12V and with guaranteed minimum value of 10V. For VCC > 15V, the zener clamp Z2 sets the limitation for ∆VGATE. Z2 clamps the gate voltage to ground to 26V typically. The minimum Z2’s clamp voltage is 23V. This effectively sets ∆VGATE to 8V minimum. SENSE (Pin 7/Pin 8): Circuit Breaker Set Pin. With a sense resistor placed in the power path between VCC and SENSE, the LTC4211’s electronic circuit breaker trips if the voltage across the sense resistor exceeds the thresholds set internally for the SLOW COMP and the FAST COMP, as shown in the Block Diagram. The threshold for the SLOW COMP is VCB(SLOW) = 50mV, and the electronic circuit breaker trips if the voltage across the sense resistor exceeds 50mV for 20µs. The SLOW COMP delay is fixed in the S8/MS8 version and adjustable in the MS version of the LTC4211. To adjust the SLOW COMP’s delay, please refer to the section on Adjusting SLOW COMP’s Response Time. Under transient conditions where large step current changes can and do occur over shorter periods of time, a second (fast) comparator instead trips the electronic circuit breaker. The threshold for the FAST COMP is set at VCB(FAST) = 150mV, and the circuit breaker trips if the voltage across the sense resistor exceeds 150mV for more than 300ns. The FAST COMP’s delay is fixed in the LTC4211 and cannot be adjusted. To disable the electronic circuit breaker, connect the VCC and SENSE pins together. VCC (Pin 8/Pin 9): This is the positive supply input to the LTC4211. The LTC4211 operates from 2.5V < VCC < 16.5V, and the supply current is typically 1mA. An internal undervoltage lockout circuit disables the device until the voltage at VCC exceeds 2.3V. 4211f 10 LTC4211 U U U PI FU CTIO S (8-Lead Package/10-Lead Package) FAULT (Not available on S8/MS8, Pin 10 MS): FAULT is both an input and an output. Connected to this pin are an analog comparator (COMP6) and an open-drain N-channel FET. During normal operation, if COMP6 is driven below 1.236V, the electronic circuit breaker trips and the GATE pin pulls low. Typically, a 10k pull-up resistor connects to the FAULT pin. This allows the LTC4211 to begin a second timing cycle (VFAULT > 1.286) and start-up properly. This also allows the use of the FAULT pin as a status output. Under normal operating conditions, the FAULT output is a logic high. Two conditions cause an active low on FAULT: (1) the LTC4211’s electronic circuit breaker trips because of an output short circuit (VOUT = 0V) or because of a fast output overcurrent transient (FAST COMP trips circuit breaker); or (2) VFILTER > 1.236V. The FAULT output is driven to logic low and is latched logic low until the ON pin is driven to logic low for 150µs (the tRESET duration). FILTER (Not available S8/MS8, Pin 3 MS): Overcurrent Fault Timing Pin and Overvoltage Fault Set pin. With a capacitor connected from this pin to ground, the SLOW COMP’s response time can be adjusted. In the S8/MS8 version of the LTC4211, the FILTER pin is not available and the delay time from overcurrent detect to GATE OFF is fixed at 20µs. W BLOCK DIAGRA VCC 8 (9) SENSE 7 (8) GATE 6 (7) – COMP7 VCC + UVLO – + – + 50mV Z2 VZ (TYP) = 26V Z1 VZ (TYP) = 12V 0.2V 10µA CHARGE PUMP 150mV tTIMER RESET + VCC 0.2V SLOW COMP + 2µA – + – 1 M3 FAST COMP M1 200µA COMP3 10µA – GLITCH FILTER (SEE NOTE 1) TIMER CB TRIPS OR UVLO 300ns DELAY 3 (4) M6 ON LOW START-UP CURRENT REGULATOR GATE CHARGING + POWER BAD COMP4 VREF – VCC + NORMAL LOGIC – 2µA FAULT M5 FAULT CB TRIPS FILTER + VREF 10µA M2 COMP5 M4 (10) MS ONLY GLITCH FILTER 150µs – GLITCH FILTER FUNCTION OF OVERDRIVE NORMAL, RESET GND VREF 4 (5) BG 0.2V COMP2 COMP1 – + + – (3) MS ONLY VREF COMP6 VREF NOTE 1: SET BY FILTER CAPACITOR FOR MS 20µs DEFAULT FOR MS8, S8 PIN NUMBERS FOR S8/MS8 (MS) 2 ON VREF 5 (6) FB 4211 BD 4211f 11 LTC4211 U OPERATIO COMP2 output goes high. After passing through a glitch filter, RESET is pulled low (Time Point N2). When the voltage at the FB pin rises above its reset threshold (1.239V), COMP2’s output goes low and a timing cycle starts (Time Point N4). After a complete timing cycle, RESET is pulled high by the external pull-up resistor. If the FB pin rises above the reset threshold for less than a timing cycle, the RESET output remains low (Time Point N3). HOT CIRCUIT INSERTION When circuit boards are inserted into or removed from live backplanes, the supply bypass capacitors can draw huge transient currents from the backplane power bus as they charge. The transient current can cause permanent damage to the connector pins as well as cause glitches on the system supply, causing other boards in the system to reset. As shown in Figure 5, the LTC4211’s RESET pin is logic low during any undervoltage lockout condition and during the initial insertion of a PC board. Under normal operation, RESET goes to logic high at the end of the soft-start cycle only after the FB pin voltage rises above its reset threshold of 1.239V. The LTC4211 is designed to turn a printed circuit board’s supply voltages ON and OFF in a controlled manner, allowing the circuit board to be safely inserted or removed from a live backplane. The device provides a system reset signal to indicate when board supply voltage drops below a predetermined level, as well as a dual function fault monitor. N1 N2 N3 V1 OUTPUT VOLTAGE MONITOR V2 N4 V1 V2 VOUT 1.236V The LTC4211 uses a 1.236V bandgap reference, precision voltage comparator and an external resistor divider to monitor the output supply voltage as shown in Figure 1. TIMER RESET The operation of the supply monitor in normal mode is illustrated in Figure␣ 2. When the supply voltage at the FB pin drops below its reset threshold (1.236V), the comparator POWER GOOD DELAY 4211 F02 Figure 2. Supply Monitor Waveforms in Normal Mode BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) VCC RSENSE LONG Q1 + VOUT CLOAD 8 LTC4211 VCC 6 7 SENSE GATE R1 ON/RESET SHORT 2 ON FB 5 – R2 COMP2 LOGIC R3 10k + µP 1.236V REFERENCE TIMER RESET TIMER Q2 GND 3 4 CTIMER GND 1 RESET 4211 F01 LONG Figure 1. Supply Voltage Monitor Block Diagram 4211f 12 LTC4211 U OPERATIO The LTC4211’s power-on reset circuit initializes the startup procedure and ensures the chip is in the proper state if the input supply voltage is too low. If the supply voltage falls below 2.18V, the LTC4211 is in undervoltage lockout (UVLO) mode, and the GATE pin is pulled low. Since the UVLO circuitry uses hysteresis, the chip restarts after the supply voltage rises above 2.3V and the ON pin goes high. In addition, users can utilize the ON comparator (COMP1) or the FAULT comparator (COMP6) to effectively program a higher undervoltage lockout level. Figure 3 shows the external resistor divider at the ON pin programs the system’s undervoltage lockout voltage. The system will enter the plug-in cycle after the ON pin rises above 1.316V. The resistor divider sets the circuit to turn on when VCC reaches around 79% of its final value. If a different turn on VCC voltage is desired change the resistor divider value accordingly. The FAULT comparator can be the alternative for external undervoltage lockout setting. If the FAULT comparator is used for this purpose, the system will wait for the input voltage to increase above the level set by the user before starting the second timing cycle. Also, if the input voltage drops below the set level in normal operating mode, the user must cycle the ON pin or VCC to restart the system. VIN 3.3V VIN 5V R1 10k ON PIN R1 61.9k ON PIN R2 10k TA = 25°C 200 150 100 50 0 0 20 40 60 80 100 120 140 160 180 200 FEEDBACK TRANSIENT (mV) 4211 F03 Figure 4. FB Comparator Glitch Filter Time vs Feedback Transient Voltage SYSTEM TIMING System timing for the LTC4211 is generated at the TIMER pin (see the Block Diagram). If the LTC4211’s internal timing circuit is off, an internal N-channel FET connects the TIMER pin to GND. If the timing circuit is enabled, an internal 2µA current source is then connected to the TIMER pin to charge CTIMER at a rate given by Equation 1: (b) 5VIN C TIMER Charge -Up Rate = ON PIN R2 10k 4211 F04 (a) 3.3VIN 250 VIN 12V R1 20k R2 10k pin. The relationship between glitch filter time and the feedback transient voltage is shown in Figure 4. GLITCH FILTER TIME (µs) UNDERVOLTAGE LOCKOUT (c) 12VIN Figure 3. ON Pin Sets the Undervoltage Lockout Voltage Externally GLITCH FILTER FOR RESET The LTC4211 has a glitch filter to prevent RESET from generating a system reset if there are transients on the FB 2µA C TIMER (1) When the TIMER pin voltage reaches COMP4’s threshold of 1.236V, the TIMER pin is reset to GND. Equation 2 gives an expression for the timer period: tTIMER = 1.236V • C TIMER 2µA (2) As a design aid, the LTC4211’s timer period as a function of the CTIMER using standard values from 3.3nF to 0.33µF is shown in Table 1. 4211f 13 LTC4211 U OPERATIO The CTIMER value is vital to ensure a proper start-up and reliable operation. A system may not get started if a timing period is set too short in relation to the time needed for the output voltage to ramp up from zero to its rated value. Conversely, this timing period should not be excessive as an output short can occur at start-up allowing the external MOSFET to overheat. A good starting point is to set CTIMER = 10nF and adjust its value accordingly to suit the specific applications. Table 1. tTIMER vs CTIMER CTIMER tTIMER 0.0033µF 2.0ms 0.0047µF 2.9ms 0.0068µF 4.2ms 0.0082µF 5.1ms 0.01µF 6.2ms 0.015µF 9.3ms 0.022µF 13.6ms 0.033µF 20.4ms 0.047µF 29.0ms 0.068µF 42.0ms 0.082µF 50.7ms 0.1µF 61.8ms 0.15µF 92.7ms 0.22µF 136ms 0.33µF 204ms OPERATING SEQUENCE Power-Up, Start-Up Check and Plug-In Timing Cycle The sequence of operations for the LTC4211 is illustrated in the timing diagram of Figure 5. When a PC board is first inserted into a live backplane, the LTC4211 first performs CHECK FOR FILTER LOW (<VREF – 80mV) CHECK FOR FAULT HIGH (>VREF + 50mV) FAST COMPARATOR ARMED CHECK FOR GATE < 0.2V 1 2 ON GOES LOW SLOW COMPARATOR ARMED 3 45 6 7 8 RESET PULLED LOW DUE TO POWER BAD 9 10 VCC ON VTMR = VREF TIMER 2µA GATE 2µA 10µA 200µA POWER GOOD (VFB > VREF) VOUT POWER BAD (VFB < VREF) RESET 4211 F05 PLUG-IN CYCLE FIRST TIMING CYCLE SOFT-START CYCLE SECOND TIMING CYCLE Figure 5. Normal Power-Up Sequence 4211f 14 LTC4211 U OPERATIO a start-up check to make sure the supply voltage is above its 2.3V UVLO threshold (see Time Point 1). If the input supply voltage is valid, the gate of the external pass transistor is pulled to ground by the internal 200µA current source connected at the GATE pin. The TIMER pin is held low by an internal N-channel pull-down transistor (see M6, LTC4211 Block Diagram) and the FILTER pin voltage is pulled to ground by an internal 10µA current source. Once VCC and ON (the ON pin is >1.316) are valid, the LTC4211 checks to make sure that GATE is OFF (VGATE < 0.2V) at Time Point 2. An internal timing circuit is enabled and the TIMER pin voltage ramps up at the rate described by Equation 1. At Time Point 3 (the timing period programmed by CTIMER), the TIMER pin voltage equals VTMR (1.236V). Next, the TIMER pin voltage ramps down to Time Point 4 where the LTC4211 performs two checks: (1) FILTER pin voltage is low (VFILTER < 1.156V) and (2) FAULT pin voltage is high (VFAULT > 1.286V). If both conditions are met, the LTC4211 begins a second timing (soft-start) cycle. Second Timing (Soft-Start) Cycle At the beginning of the second timing cycle (Time Point␣ 5), the LTC4211’s FAST COMP is armed and an internal 10µA current source working with an internal charge pump provides the gate drive to the external pass transistor. An expression for the GATE voltage slew rate is given by Equation 3: VGATE Slew Rate, dVGATE 10µA = dt C GATE (3) where CGATE = Power MOSFET gate input capacitance (CISS). For example, a Si4410DY (a 30V N-channel power MOSFET) exhibits an approximate CGATE of 3300pF at VGS = 10V. The LTC4211’s GATE voltage rate-of-change (slew rate) for this example would be: dV 10µA V VGATE Slew Rate, GATE = = 3.03 dt 3300pF ms The inrush current being delivered to the load while the GATE is ramping is dependent on CLOAD and CGATE. Equation 4 gives an expression for the inrush current during the second timing cycle: IINRUSH = dVGATE C • C LOAD = 10µA • LOAD dt C GATE (4) For example, if CGATE = 3300pF and CLOAD = 2000µF, the inrush current charging CLOAD is: IINRUSH = 10µA • 2000µF = 6.06A 0.0033µF (5) At Time Point 6, the output voltage trips COMP2’s threshold, signaling an output voltage “power good” condition. At Time Point 7, RESET is asserted high, SLOW COMP is armed and the LTC4211 enters a fault monitor mode. The TIMER voltage then ramps down to Time Point 8. Power-Off Cycle As shown at Time Point 9, an external hard reset is initiated by pulling the ON pin low (VON < 1.236V). The GATE pin voltage is ramped to ground by the internal 200µA current source, discharging CGATE and turning off the pass transistor. As CLOAD discharges, the output voltage crosses COMP2’s threshold, signaling a “power bad” condition at Time Point 10. At this point, RESET is asserted low. SOFT-START WITH CURRENT LIMITING During the second timing cycle, the inrush current was described by Equation 4. Note that there is a one-to-one correspondence in the inrush current to CLOAD. If the inrush current is large enough to cause a voltage drop greater than 50mV across the sense resistor, an internal servo loop controls the operation of the 10µA current source at the GATE pin to regulate the load current to: ILIMIT (SOFTSTART) = 50mV RSENSE (6) For example, the inrush current is limited to 5A when RSENSE = 0.01Ω. 4211f 15 LTC4211 U OPERATIO In this fashion, the inrush current is controlled and CLOAD is charged up slowly during the soft-start cycle. The timing diagram in Figure 6 illustrates the operation of the LTC4211 in a normal power-up sequence with limited inrush current as described by Equation 6. At Time Point␣ 5, the GATE pin voltage begins to ramp indicating that the power MOSFET is beginning to charge CLOAD. At Time Point 5A, the inrush current causes a 50mV voltage drop across RSENSE and the internal servo loop engages, limiting the inrush current to a fixed level. At Time Point 6, the GATE pin voltage continues to ramp as CLOAD charges until VOUT reaches its final value. The charging current reduces, and the internal servo loop disengages. At the end of the soft-start cycle (Time Point 7), RESET is high and SLOW COMP is armed. FREQUENCY COMPENSATION AT SOFT-START If the external gate input capacitance (CISS) is greater than 600pF, no external gate capacitor is required at GATE to stabilize the internal current-limiting loop during softstart. Otherwise, connect a gate capacitor between the GATE pin and ground to increase the total gate capacitance to be equal to or above 600pF. The servo loop that controls the external MOSFET during current limiting has a unitygain frequency of about 105kHz and phase margin of 80° for external MOSFET gate input capacitances to 2.5nF. USING AN EXTERNAL GATE CAPACITOR The LTC4211 automatically limits the inrush current in one of two ways: by controlling the GATE pin voltage slew rate CHECK FOR FILTER LOW (<VREF – 80mV) CHECK FOR FAULT HIGH (>VREF + 50mV) FAST COMPARATOR ARMED CHECK FOR GATE < 0.2V 1 2 ON GOES LOW SLOW COMPARATOR ARMED 3 4 5 5A 6 7 8 RESET PULLED LOW DUE TO POWER BAD 9 10 VCC ON VREF TIMER 2µA 2µA GATE GATE VOUT 10µA POWER GOOD VFB > VREF VOUT POWER BAD VFB < VREF 200µA LOAD CURRENT IS REGULATING AT 50mV/RSENSE ILOAD RESET 4211 F06 PLUG-IN CYCLE FIRST TIMING CYCLE SOFT-START CYCLE SECOND TIMING CYCLE Figure 6. Normal Power-Up Sequence (With Current Limiting in Second Timing Cycle) 4211f 16 LTC4211 U OPERATIO or by actively limiting the inrush current. The LTC4211 uses GATE voltage slew rate limiting when CLOAD is small and/or the inrush current limit is set high. If GATE voltage slew rate control is preferred with large CLOAD, an external capacitor (CGX) can be used from GATE to ground, as shown in Figure 7. According to Equation 3, adding CGX slows the GATE voltage slew rate at the expense of slower system turn-on and turn-off time. Should this technique be used, values for CGX less than 150nF are recommended. VIN 5V RSENSE 0.007Ω M1 Si4410DY CGX* R1 36k VCC SENSE LTC4211** VOUT 5V 5A + CLOAD GATE FB R2 15k 4211 F07 *VALUES ≤150nF SUGGESTED **ADDITIONAL DETAILS OMITTED FOR CLARITY VGATE SLEW RATE CONTROL ( 10µA dVGATE = dt CGATE + CGX ) Figure 7. Using an External Capacitor at GATE for GATE Voltage Slew Rate Control and Large CLOAD An external gate capacitor may also be useful to decrease or eliminate current spikes through the MOSFET when power is first applied. At power-up, the instantaneous input voltage step attempts to pull the MOSFET gate up through the MOSFET’s drain-to-gate capacitance. If the MOSFET’s CGS is small, the gate can be pulled up high enough to turn on the MOSFET, thereby allowing a current spike to the output. This event occurs during the time that the LTC4211 is coming out of UVLO and getting its intelligence to hold the GATE pin low. An external capacitor attenuates the voltage to which the GATE is pulled up and eliminates the current spike. The value required is dependent on the MOSFET capacitance specifications. In typical applications, this capacitor is not required. ELECTRONIC CIRCUIT BREAKER The LTC4211 features an electronic circuit breaker function that protects against supply overvoltage, externallygenerated fault conditions and shorts or excessive load current conditions on the supply. If the circuit breaker trips, the GATE pin is immediately pulled to ground, the external N-channel MOSFET is quickly turned OFF and FAULT is latched low. The circuit breaker trips whenever the voltage across the sense resistor exceeds two different levels, set by the LTC4211’s SLOW COMP and FAST COMP thresholds (see Block Diagram). The SLOW COMP trips the circuit breaker if the voltage across the SENSE resistor (VCC – VSENSE = VCB) is greater than 50mV for 20µs. There may be applications where this comparator’s response time is not long enough, for example, because of excessive supply voltage noise. To adjust the response time of the SLOW COMP, the MS version of the LTC4211 is chosen and a capacitor is used at the LTC4211’s FILTER pin (see section on Adjusting SLOW Comp’s Response Time). The FAST COMP trips the circuit breaker to protect against fast load overcurrents if the transient voltage across the sense resistor is greater than 150mV for 300ns. The response time of the LTC4211’s FAST COMP is fixed. The timing diagram of Figure 6 illustrates when the LTC4211’s electronic circuit breaker is armed. After the first timing cycle, the LTC4211’s FAST COMP is armed at Time Point 5. Arming FAST COMP at Time Point 5 ensures that the system is protected against a short-circuit condition during the second timing cycle after CLOAD has been fully charged. At Time Point 7, SLOW COMP is armed when the internal control loop is disengaged. The timing diagrams in Figures 8 and 9 illustrate the operation of the LTC4211 when the load current conditions exceed the thresholds of the FAST COMP (VCB(FAST) > 150mV) and SLOW COMP (VCB(SLOW) > 50mV), respectively. RESETTING THE ELECTRONIC CIRCUIT BREAKER Once the LTC4211’s circuit breaker is tripped, FAULT is asserted low and the GATE pin is pulled to ground. The LTC4211 remains latched OFF in this fault state until the external fault is cleared. To clear the internal fault detect circuitry and to restart the LTC4211, its ON pin must be driven low (VON < 1.236V) for at least 150µs, after which time FAULT goes high. Toggling the ON pin from low to high (VON > 1.316V) initiates a restart sequence in the LTC4211. The timing diagram in Figure 10 illustrates a 4211f 17 LTC4211 U OPERATIO FAST COMPARATOR ARMED SLOW COMPARATOR ARMED CIRCUIT BREAKER TRIPS SHORT CIRCUIT 1 2 VCC 3 4 5 6 7 8 RESET PULLED LOW DUE TO POWER BAD A B C ON TIMER GATE FPD VOUT GATE VOUT POWER BAD VFB < VREF POWER GOOD VFB > VREF RESET >150mV VCC – VSENSE FAULT 300ns TYP 4211 F08 Figure 8. Output Short Circuit Causes Fast Comparator to Trip the Circuit Breaker 4211f 18 LTC4211 U OPERATIO FAST COMPARATOR ARMED SLOW COMPARATOR ARMED CIRCUIT BREAKER TRIPS OVER CURRENT RESET PULLED LOW DUE TO POWER BAD 1 2 VCC 3 4 5 6 7 8 A B C ON TIMER GATE VOUT GATE VOUT FPD POWER BAD VFB < VREF POWER GOOD VFB > VREF RESET >50mV VCC – VSENSE VREF FILTER 2µA 10µA FAULT 4211 F09 CIRCUIT BREAKER TRIPS Figure 9. Mild Overcurrent Slow Comparator Trips the Circuit Breaker After Filter Programming Period 4211f 19 LTC4211 U OPERATIO FAST COMPARATOR ARMED SLOW COMPARATOR ARMED CIRCUIT BREAKER TRIPS CIRCUIT BREAKER RESET 1 2 VCC 3 4 5 6 7 8 B 9 ON 9A ON 1 ON TIMER GATE GATE VOUT FPD VFB < VREF VOUT RESET VSENSE = 50mV VCC – VSENSE REGULATING LOAD CURRENT FILTER >50mV tFAULTSC 2µA VREF 10µA FAULT 4211 F10 tRESET Figure 10. Power-Up in Overcurrent, Slow Comparator Trips the Circuit Breaker start-up sequence where the LTC4211 is powered up into a load overcurrent condition. Note that the circuit breaker trips at Time Point B and is reset at Time Point 9A. ADJUSTING SLOW COMP’S RESPONSE TIME The response time of SLOW COMP is adjusted using a capacitor connected from the LTC4211’s FILTER pin to ground. If this pin is left unused, SLOW COMP’s delay defaults to 20µs. During normal operation, the FILTER output pin is held low as an internal 10µA pull-down current source is connected to this pin by transistor M4. This pull-down current source is turned off when an overcurrent load condition is detected by SLOW COMP. During an overcurrent condition, the internal 2µA pull-up current source is connected to the FILTER pin by transistor M5, thereby charging CFILTER. As the charge on the capacitor accumulates, the voltage across CFILTER increases. Once the FILTER pin voltage increases to 1.236V, the electronic circuit breaker trips and the LTC4211’s GATE pin is switched quickly to ground by transistor M3. After the circuit breaker is tripped, M5 is turned OFF, M4 is turned ON and the 10µA pull-down current then holds the FILTER pin voltage low. The SLOW COMP response time from an overcurrent fault condition to when the circuit breaker trips (GATE OFF) is given by Equation 7: tSLOWCOMP = 1.236V • C FILTER + 20µs 2µA (7) For example, if CFILTER = 1000pF, SLOW COMP’s response time = 638µs. As a design aid, SLOW COMP’s delay time (tSLOW COMP) versus CFILTER for standard values of CFILTER from 100pF to 1000pF is illustrated in Table 2. 4211f 20 LTC4211 U OPERATIO For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and the LTC4211’s VCC and SENSE pins are strongly recommended. The drawing in Figure 11 illustrates the correct way of making connections between the LTC4211 and the sense resistor. PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. Table 2. tSLOWCOMP vs CFILTER CFILTER tSLOWCOMP 100pF 82µs 220pF 156µs 330pF 224µs 470pF 310µs 680pF 440µs 820pF 527µs 1000pF 638µs SENSE RESISTOR CONSIDERATIONS The fault current level at which the LTC4211’s internal electronic circuit breaker trips is determined by a sense resistor connected between the LTC4211’s VCC and SENSE pins and two separate trip points. The first trip point is set by the SLOW COMP’s threshold, VCB(SLOW) = 50mV, and occurs should a load current fault condition exist for more than 20µs. The current level at which the electronic circuit breaker trips is given by Equation 8: ITRIP(SLOW) = VCB(SLOW) RSENSE = VCB(FAST ) RSENSE = CURRENT FLOW TO LOAD TRACK WIDTH W: 0.03" PER AMP ON 1 OZ COPPER IRC-TT SENSE RESISTOR LR251201R010F OR EQUIVALENT 0.01Ω, 1%, 1W CURRENT FLOW TO LOAD W 4211 F11 50mV RSENSE (8) TO TO VCC SENSE The second trip point is set by the FAST COMP’s threshold, VCB(FAST) = 150mV, and occurs during fast load current transients that exist for 300ns or longer. The current level at which the circuit breaker trips in this case is given by Equation 9: ITRIP(FAST ) = The power rating of the sense resistor should accommodate steady-state fault current levels so that the component is not damaged before the circuit breaker trips. Table␣ 4 in the Appendix lists sense resistors that can be used with the LTC4211’s circuit breaker. 150mV RSENSE (9) As a design aid, the currents at which electronic circuit breaker trips for common values for RSENSE are shown in Table 3. Figure 11. Making PCB Connections to the Sense Resistor CALCULATING CIRCUIT BREAKER TRIP CURRENT For a selected RSENSE value, the nominal load current that trips the circuit breaker is given by Equation 10: ITRIP(NOM) = VCB(NOM) RSENSE(NOM) = 50mV RSENSE(NOM) (10) The minimum load current that trips the circuit breaker is given by Equation 11. Table 3. ITRIP(SLOW) and ITRIP(FAST) vs RSENSE RSENSE ITRIP(SLOW) ITRIP(FAST) 0.005Ω 10A 30A 0.006Ω 8.3A 25A 0.007Ω 7.1A 21A 0.008Ω 6.3A 19A 0.009Ω 5.6A 17A 0.01Ω 5A 15A ITRIP(MIN) = VCB(MIN) RSENSE(MAX) = 40mV RSENSE(MAX) (11) where R RSENSE(MAX) = RSENSE(NOM) • 1 + TOL 100 4211f 21 LTC4211 U OPERATIO The maximum load current that trips the circuit breaker is given in Equation 12. ITRIP(MAX) = VCB(MAX) RSENSE(MIN) = 60mV RSENSE(MIN) (12) where R RSENSE(MIN) = RSENSE(NOM) • 1 – TOL 100 For example: If a sense resistor with 7mΩ ±5% RTOL is used for current limiting, the nominal trip current ITRIP(NOM) = 7.1A. From Equations 11 and 12, ITRIP(MIN) = 5.4A and ITRIP(MAX) = 9.02A respectively. For proper operation and to avoid the circuit breaker tripping unnecessarily, the minimum trip current (ITRIP(MIN)) must exceed the circuit’s maximum operating load current. For reliability purposes, the operation at the maximum trip current (ITRIP(MAX)) must be evaluated carefully. If necessary, two resistors with the same RTOL can be connected in parallel to yield an RSENSE(NOM) value that fits the circuit requirements. POWER MOSFET SELECTION CRITERIA To start the power MOSFET selection process, choose the maximum drain-to-source voltage, VDS(MAX), and the maximum drain current, ID(MAX) of the MOSFET. The VDS(MAX) rating must exceed the maximum input supply voltage (including surges, spikes, ringing, etc.) and the ID(MAX) rating must exceed the maximum short-circuit current in the system during a fault condition. In addition, consider three other key parameters: 1) the required gatesource (VGS) voltage drive, 2) the voltage drop across the drain-to-source on resistance, RDS(ON) and 3) the maximum junction temperature rating of the MOSFET. Power MOSFETs are classified into two categories: standard MOSFETs (RDS(ON) specified at VGS = 10V) and logic-level MOSFETs (RDS(ON) specified at VGS = 5V). The absolute maximum rating for VGS is typically ±20V for standard MOSFETs. However, the VGS maximum rating for logic-level MOSFETs ranges from ±8V to ±20V depending upon the manufacturer and the specific part number. The LTC4211’s GATE overdrive as a function of VCC is illustrated in the Typical Performance curves. Logiclevel MOSFETs are recommended for low supply voltage applications and standard MOSFETs can be used for applications where supply voltage is greater than 4.75V. Note that in some applications, the gate of the external MOSFET can discharge faster than the output voltage when the circuit breaker is tripped. This causes a negative VGS voltage on the external MOSFET. Usually, the selected external MOSFET should have a ±VGS(MAX) rating that is higher than the operating input supply voltage to ensure that the external MOSFET is not destroyed by a negative VGS voltage. In addition, the ±VGS(MAX) rating of the MOSFET must be higher than the gate overdrive voltage. Lower ±VGS(MAX) rating MOSFETs can be used with the LTC4211 if the GATE overdrive is clamped to a lower voltage. The circuit in Figure 12 illustrates the use of Zener diodes to clamp the LTC4211’s GATE overdrive signal if lower voltage MOSFETs are used. RSENSE Q1 VCC VOUT D1* D2* RG 200Ω GATE 4211 F12 *USER SELECTED VOLTAGE CLAMP (A LOW BIAS CURRENT ZENER DIODE IS RECOMMENDED) 1N4688 (5V) 1N4692 (7V): LOGIC-LEVEL MOSFET 1N4695 (9V) 1N4702 (15V): STANDARD-LEVEL MOSFET Figure 12. Optional Gate Clamp for Lower VGS(MAX) MOSFETs 4211f 22 LTC4211 U OPERATIO The RDS(ON) of the external pass transistor should be low to make its drain-source voltage (VDS) a small percentage of VCC. At a VCC = 2.5V, VDS + VRSENSE = 0.1V yields 4% error at the output voltage. This restricts the choice of MOSFETs to very low RDS(ON). At higher VCC voltages, the VDS requirement can be relaxed in which case MOSFET package dissipation (PD and TJ) may limit the value of RDS(ON). Table 5 lists some power MOSFETs that can be used with the LTC4211. For reliable circuit operation, the maximum junction temperature (TJ(MAX)) for a power MOSFET should not exceed the manufacturer’s recommended value. This includes normal mode operation, start-up, current-limit and autoretry mode in a fault condition. Under normal conditions the junction temperature of a power MOSFET is given by Equation 13: MOSFET Junction Temperature, TJ(MAX) ≤ TA(MAX) + θJA • PD (13) where PD = (ILOAD)2 • RDS(ON) θJA = junction-to-ambient thermal resistance TA(MAX) = maximum ambient temperature If a short circuit happens during start-up, the external MOSFET can experience a big single pulse energy. This is especially true if the applications only employed a small gate capacitor or no gate capacitor at all. Consult the safe operating area (SOA) curve of the selected MOSFET to ensure that the TJ(MAX) is not exceeded during start-up. USING STAGGERED PIN CONNECTORS The LTC4211 can be used on either a printed circuit board or on the backplane side of the connector, and examples for both are shown in Figures 13 and 14. Printed circuit board edge connectors with staggered pins are recommended as the insertion and removal of circuit boards do sequence the pin connections. Supply voltage and ground connections on the printed circuit board should be wired to the edge connector’s long pins or blades. Control and status signals (like RESET, FAULT and ON) passing through the card’s edge connector should be wired to short length pins or blades. PCB CONNECTION SENSE There are a number of ways to use the LTC4211’s ON pin to detect whether the printed circuit board has been fully seated in the backplane before the LTC4211 commences a start-up cycle. The first example is shown in the schematic on the front page of this data sheet. In this case, the LTC4211 is mounted on the PCB and a 20k/10k resistive divider is connected to the ON pin. On the edge connector, R1 is wired to a short pin. Until the connectors are fully mated, the ON pin is held low, keeping the LTC4211 in an OFF state. Once the connectors are mated, the resistive divider is connected to VCC, VON > 1.316V and the LTC4211 begins a start-up cycle. In Figure 13, an LTC4211 is illustrated in a basic configuration on a PCB daughter card. The ON pin is connected to VCC on the backplane through a 10k pull-up resistor once the card is seated into the backplane. R2 bleeds off any potential static charge which might exist on the backplane, the connector or during card installation. A third example is shown in Figure 14 where the LTC4211 is mounted on the backplane. In this example, a 2N2222 transistor and a pair of resistors (R4, R5) form the PCB connection sense circuit. With the card out of the chassis, Q2’s base is biased to VCC through R5, biasing Q2 ON and driving the LTC4211’s ON pin low. The base of Q2 is also wired to a socket on the backplane connector. When a card is firmly seated into the backplane, the base of Q2 is then grounded through a short pin connection on the card. Q2 is biased OFF, the LTC4211’s ON pin is pulled-up to VCC and a start-up cycle begins. In the previous three examples, the connection sense was hard wired with no processor (low) interrupt capability. As illustrated in Figure 15, the addition of an inexpensive logic-level discrete MOSFET and a couple of resistors offers processor interrupt control to the connection sense. R4 keeps the gate of M2 at VCC until the card is firmly mated to the backplane. A logic low for the ON/OFF signal turns M2 OFF, allows the ON pin to pull high and turns on the LTC4211. 4211f 23 LTC4211 U W U U APPLICATIO S I FOR ATIO BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) VIN 5V LONG 5V VCC RSENSE 0.007Ω Z1* SHORT RESET R1 10Ω C1 0.1µF Q1 Si4410DY VOUT 5V 5A R6 10k 1 SHORT 2 RESET ON R2 10k VCC SENSE LTC4211 LONG 4 GATE FB GND Z1 = 1SMA10A OR SMAJ10A * OPTIONAL + 8 COUT 7 R4 36k 6 5 R5 15k TIMER 3 CTIMER 10nF 4211 F13 Figure 13. Hot Swap Controller On Daughter Board (Staggered Pin Connections) RSENSE 0.007Ω VIN 5V BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) Q1 Si4410DY VOUT 5V 5A LONG + Z1* RX 10Ω CX 0.1µF PCB CONNECTION SENSE LONG R5 10k 8 R4 10k 2 Q2 4 VCC ON 7 SENSE GATE LTC4211 RESET FB GND R1 36k 6 R3 10k 1 3 CTIMER 10nF SHORT SHORT 5 SHORT TIMER Z1 = 1SMA10A OR SMAJ10A * OPTIONAL COUT R7 15k RESET R2 100k 4211 F14 Figure 14. Hot Swap Controller on Backplane (Staggered Pin Connections) A more elaborate connection sense scheme is shown in Figure 16. The bases of Q1 and Q2 are wired to short pins located on opposite ends of the edge connector because the installation/removal of printed circuit cards generally requires rocking the card back and forth. When VCC makes connection, the bases of transistors Q1 and Q2 are pulled high, biasing them ON. When either one of them is ON, the LTC4211’s ON pin is held low, keeping the LTC4211 OFF. When both the short base connector pins of Q1 and Q2 finally mate to the backplane, their bases are grounded, biasing the transistors OFF. The ON pin voltage is then pulled high by R3 enabling the LTC4211 and a power-up cycle begins. A software-initiated power-down cycle can be started by momentarily driving transistor M1 with a logic high signal. This in turn will drive the LTC4211’s ON pin low. If the ON pin is held low for more than 8µs, the LTC4211’s GATE pin is switched to ground. 4211f 24 LTC4211 U W U U APPLICATIO S I FOR ATIO BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) RSENSE 0.007Ω LONG VCC 5V CLOAD 8 7 VCC SHORT R1 10k 6 SENSE GATE 2 M2 4 CTIMER 10nF PCB CONNECTION SENSE LONG RESET GND 3 GND µP LOGIC 1 RESET TIMER R7 10k R6 15k LTC4211 ON R2 10k R5 36k 5 FB R4 10k SHORT ON/OFF VOUT 5V 5A + RX 10Ω CX 100nF Z1* M1 Si4410DY 4211 F15 ZZ1 = 1SMA10A OR SMAJ10A M2: 2N7002LT1 * OPTIONAL Figure 15. Connection Sense with ON/OFF Control BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) LAST BLADE OR PIN ON CONNECTOR SHORT RSENSE 0.007Ω PCB CONNECTION SENSE VCC LONG Z1* RX 10Ω CX 0.1µF M2 Si4410DY CLOAD R1 10k R2 10k R3 10k 8 7 VCC 6 SENSE GATE FB 2 R8 10k GND SHORT TIMER LONG R4 36k R5 15k RESET 1 R7 10k µP LOGIC RESET GND 3 M1 5 LTC4211 ON Q1 Q2 ON/RESET VOUT 5V 5A + 4 CTIMER 10nF 4211 F16 SHORT LAST BLADE OR PIN ON CONNECTOR Z1 = 1SMA10A OR SMAJ10A M1: 2N7002LT1 Q1, Q2: MMBT3904LT1 * OPTIONAL Figure 16. Connection Sense for Rocking the Daughter Board Back and Forth 4211f 25 LTC4211 U W U U APPLICATIO S I FOR ATIO 12V Hot Swap Application Figure 17 shows a 12V, 3A hot swap application circuit. The resistor divider R1/R2 programs the undervoltage lockout externally and allows the system to start up after VCC increases above 9.46V. The resistor divider R3/R4 monitors VOUT and signals the RESET pin when VOUT goes above 10.54V. Transient voltage suppressor Z1 and snubber network (CX, RX) are highly recommended to protect the 12V applications system from ringing and voltage spikes. RG is recommended for VCC > 10V and it can minimize high frequency parasitic oscillations in the power MOSFET. Figure 18. In this case, the autoretry circuitry will attempt to restart the LTC4211 with a 50% duty cycle, as shown in the timing diagram of Figure 19. To prevent overheating the external MOSFET and other components during the autoretry sequence, adding a capacitor (CAUTO) to the circuit introduces an RC time constant (tOFF) that adjusts the autoretry duty cycle. Equation 14 gives the autoretry duty cycle, modified by this external time constant: Autoretry Duty Cycle ≈ tTIMER • 100% (14) tOFF + 2 • tTIMER AUTORETRY AFTER A FAULT where tTIMER = LTC4211 system timing(see TIMER function) and tOFF is a time needed to charge capacitor CAUTO from 0V to the ON pin threshold (1.316V). To configure the LTC4211 to automatically retry after a fault condition, the FAULT and ON pins can be connected to a pull-up resistor (RAUTO) to the supply, as shown in For the values shown, the external RC time constant is set at 1 second, the tTIMER delay equals 6.2ms and the autoretry duty cycle drops from 50% to 2.5%. BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) RSENSE 0.012Ω LONG VCC 12V Z1** RX 10Ω CX 100nF 7 8 6 SENSE 2 GATE R4 12.4k R2 10k RESET TIMER GND 3 R5 10k R3 93.1k 5 LTC4211 ON PCB CONNECTION SENSE LONG CLOAD RG 100Ω FB R1 61.9k VOUT 12V 3A + VCC SHORT M1 Si4410DY µP LOGIC 1 RESET GND CTIMER 8.2nF 4 GND Z1 = 1SMA12A OR SMAJ12A ** HIGHLY RECOMMENDED 4211 F17 Figure 17. 12V Hot Swap Application BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) VCC 5V RSENSE 0.007Ω LONG RPULL-UP 10k RESET RAUTO (SEE NOTE) R3 10Ω C1 0.1µF VOUT 5V 5A Z1* R1 36k SHORT 1 2 3 GND Q1 Si4410DY CAUTO 1µF LONG CFILTER 100pF CTIMER 10nF 4 5 RESET ON FAULT VCC LTC4211MS FILTER SENSE TIMER GATE GND FB 10 + CLOAD 9 R2 15k 8 7 NOTE: Q1 MOUNTED TO 300mm2 COPPER AREA RAUTO = 1M YIELDS 2.5% DUTY CYCLE AND Q1 TCASE = 50°C RAUTO = 3.2M YIELDS 0.8% DUTY CYCLE AND Q1 TCASE = 37°C 6 Z1 = 1SMA10A OR SMAJ10A * OPTIONAL 4211 F18 Figure 18. LTC4211MS Autoretry Application 4211f 26 LTC4211 U W U U APPLICATIO S I FOR ATIO FAST COMPARATOR ARMED SLOW COMPARATOR ARMED 1 VCC 2 3 45 6 7 8 B ON/FAULT ON/FAULT tRESET TIMER GATE GATE VOUT FPD VFB < VREF VOUT RESET VSENSE = 50mV VCC – VSENSE >50mV REGULATED LOAD CURRENT VREF FILTER 10µA 2µA tOFF t1 t2 tFILTER tOFF 4211 F19 DUTY CYCLE = t2 (t << t1, t2 AND tOFF) tOFF + t1 + t2 FILTER Figure 19. Autoretry Timing To increase the RC delay, the user may either increase CAUTO or RAUTO. However, increasing CAUTO > 2µF will actually limit the RC delay due to the reset sink-current capability of the FAULT pin. Therefore, in order to increase the RC delay, it is more effective to either increase RAUTO or to put a bleed resistor in parallel with CAUTO to GND. As an example, increasing RAUTO from 1M to 3.2M decreases duty cycle to 0.8%. HOT SWAPPING TWO SUPPLIES Using two external pass transistors, the LTC4211 can switch two supply voltages. In some cases, it is necessary to bring up the dominant supply first during power-up but ramp them down together during the power-down phase. The circuit in Figure 20 shows how to program two different delays for the pass transistors. The 5V supply is powered up first. R1 and C3 are used to set the rise and fall times on the 5V supply. Next, the 3.3V supply ramps up with 20ms delay set by R6 and C2. On the falling edge, both supplies ramp down together because D1 and D2 bypass R1 and R6. OVERVOLTAGE TRANSIENT PROTECTION Good engineering practice calls for bypassing the supply rail of any analog circuit. Bypass capacitors are often placed at the supply connection of every active device, in addition to one or more large value bulk bypass capacitors per supply rail. If power is connected abruptly, the large bypass capacitors slow the rate of rise of the supply voltage and heavily damp any parasitic resonance of lead or PC track inductance working against the supply bypass capacitors. The opposite is true for LTC4211 Hot Swap circuits mounted on plug-in cards. In most cases, there is no supply bypass capacitor present on the powered supply 4211f 27 LTC4211 U W U U APPLICATIO S I FOR ATIO BACKPLANE PCB EDGE CONNECTOR CONNECTOR (MALE) (FEMALE) 3.3V 5V OUT 3.3V OUT R8 10Ω C4 0.1µF Z1* 5V R9 10Ω C5 0.1µF ON SHORT LONG R11 10k 4 D3** R7 10Ω 5% Q1 1/2 Si4936DY CLOAD VOUT2 5V 2A + D2 1N4148 LTC4211 3 C1 10nF 16V R2 0.015Ω 5% 10k 2 R10 10k GND CURRENT LIMIT: 3.3A 1 SHORT VOUT1 3.3V 2A + LONG Z2* RESET Q2 1/2 Si4936DY LONG RESET ON TIMER GND VCC SENSE GATE FB 8 R3 10Ω 5% R6 1M 5% R1 10k 5% 7 6 CLOAD D1 1N4148 R4 2.74k 1% TRIP POINT: 4.06V 5 Z1, Z2: 1SMA10A OR SMAJ10A * OPTIONAL C3 0.047µF 25V C2 0.022µF 25V R5 1.2k 1% 4211 F20 **D3 IS OPTIONAL AND HELPS DISCHARGE VOUT1 IF VOUT2 SHORTS Figure 20. Switching 5V and 3.3V voltage side of the MOSFET switch. An abrupt connection, produced by inserting the board into a backplane connector, resulting in a fast rising edge applied on the supply line of the LTC4211. Since there is no bulk capacitance to damp the parasitic track inductance, supply voltage transients excite parasitic resonant circuits formed by the power MOSFET capacitance and the combined parasitic inductance from the wiring harness, the backplane and the circuit board traces. In these applications, there are two methods that should be applied together for eliminating these supply voltage transients: using transient voltage suppressor to clip the transient to a safe level and snubber networks. Snubber networks are series RC networks whose time constants are experimentally determined based on the board’s parasitic resonance circuits. As a starting point, the capacitors in these networks are chosen to be 10× to 100× the power MOSFET’s COSS under bias. The series resistor is a value determined experimentally and ranges from 1Ω to 50Ω, depending on the parasitic resonance circuit. For applications with supply voltages of 12V or higher the ringing and overshoot during hot-swapping or when the output is short-circuited can easily exceed the absolute maximum specification of the LTC4211. To reduce the danger, transient voltage suppressors and snubber networks are highly recommended. For applications with lower supply voltage such as 5V, usually a snubber is adequate to reduce the supply ringing. Although, the need of a transient voltage suppressor arises for inductive and high current application. Note that in all LTC4211 5V applications schematics, transient suppressor and snubber networks have been added for protection. The transient suppressor is optional and a simple short-circuit test can be performed to determine the need of it. These protection networks should be mounted very close to the LTC4211’s supply input rail using short lead lengths to minimize lead inductance. This is shown schematically in Figure 21, and a recommended layout of the transient protection devices around the LTC4211 is shown in Figure 22. RSENSE 0.007Ω VIN 5V 8 VCC Q1 Si4410DY 7 R1 36k 6 SENSE GATE 5 FB RX 10Ω Z1* VOUT 5V 5A + COUT R2 15k LTC4211 CX 0.1µF GND 4 TIMER 1 RESET 2 ON RESET ON 3 CTIMER INPUT GND Z1 = 1SMA10A OR SMAJ10A * OPTIONAL OUTPUT GND 4211 F21 Figure 21. Placing Transient Protection Devices Close to the LTC4211’s Input Rail 4211f 28 LTC4211 U W U U APPLICATIO S I FOR ATIO CURRENT FLOW TO LOAD CURRENT FLOW TO LOAD POWER MOSFET (SO-8) SENSE RESISTOR (RSENSE) D G D S W W CX D S D S Z1* TRANSIENT VOLTAGE SUPPRESSOR RGX* CGX* FB GATE SENSE VIA TO GND PLANE VCC SNUBBER NETWORK RX R4 15k R3 36k NOTES: DRAWING IS NOT TO SCALE! *OPTIONAL COMPONENTS **ADDITIONAL DETAILS OMITTED FOR CLARITY GND TIMER ON RESET LTC4211** 1 CTIMER 10nF CURRENT FLOW FROM LOAD W 4211 F28 Figure 22. Recommended Layout for LTC4211 Protection Devices, RSENSE, Power MOSFET and Feedback Network 4211f 29 LTC4211 U W U U APPLICATIO S I FOR ATIO SUPPLY OVERVOLTAGE DETECTION/ PROTECTION USING FILTER PIN In addition to using external protection devices around the LTC4211 for large scale transient protection, low power Zener diodes can be used with the LTC4211’s FILTER pin to act as a supply overvoltage detection/protection circuit on either the high side (input) or low side (output) of the external pass transistor. Recall that internal control circuitry keeps the LTC4211 GATE voltage from ramping up if VFILTER > 1.156V, or when an external fault condition (VFILTER > 1.236V) causes FAULT to be asserted low. High Side (Input) Overvoltage Protection As shown in Figure 23, a low power Zener diode can be used to sense an overvoltage condition on the input (high) side of the main 5V supply. In this example, a low bias current 1N4691 Zener diode is chosen to protect the system. Here, the Zener diode is connected from VCC to the LTC4211’s FILTER pin (Pin 3 MS). If the input voltage to the system is greater than 6.8V during start-up, the voltage on the FILTER pin is pulled higher than its 1.156V threshold. As a result, the GATE pin is not allowed to ramp and the second timing cycle will not commence until the supply overvoltage condition is removed. Should the supply overvoltage condition occur during normal operation, internal control logic would trip the electronic circuit breaker and the GATE would be pulled to ground, shutting OFF the external pass transistor. If a lower supply overvoltage threshold is desired, use a Zener diode with a smaller breakdown voltage. A timing diagram for illustrating LTC4211 operation under a high side overvoltage condition is shown in Figure 24. The start-up sequence in this case (between Time Points 1 and 2) is identical to any other start-up sequence under normal operating conditions. At Time Point 2A, the input supply voltage causes the Zener diode to conduct thereby forcing VFILTER > 1.156V. At Time Point 3, FAULT is asserted low and the TIMER pin voltage ramps down. At Time Point 4, the LTC4211 checks if VFILTER < 1.156V. BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) LONG 5V R4 10k FAULT RESET ON/OFF R3 10Ω C1 0.1µF Z1* Q1 Si4410DY VOUT 5V 5A SHORT R5 10k SHORT Z2 6.2V SHORT R7 10k 1 3 4 CFILTER 47pF R1 36k LTC4211 2 R6 10k GND RSENSE 0.007Ω RESET FAULT ON VCC FILTER SENSE TIMER CTIMER 5 GND 10nF GATE FB 10 9 8 + CLOAD R2 15k 7 6 4211 F23 LONG Z1 = 1SMA10A OR SMAJ10A Z2 = 1N4691 * OPTIONAL Figure 23. LTC4211MS High Side Overvoltage Protection Implementation 4211f 30 LTC4211 U W U U APPLICATIO S I FOR ATIO OVERVOLTAGE 1 2 VCC 2A 3 4 IF ANY FAULT HAPPENS AFTER THIS POINT, THE CIRCUIT BREAKER TRIPS AND FAULT LATCHES LOW IF OVERVOLTAGE GOES AWAY, SECOND CYCLE CONTINUES 5 SLOW COMPARATOR ARMED OVERVOLTAGE CIRCUIT BREAKER TRIPS, GATE PULLS DOWN AND FAULT LATCHES LOW 6 7 8 A B C ON TIMER GATE VOUT GATE VOUT FPD POWER BAD VFB < VREF POWER GOOD VFB > VREF RESET >VREF >VREF – 80mV FILTER FAULT 4211 F24 FAULT IS PULLED LOW (BUT NOT LATCHED) DUE TO A START-UP OVERVOLTAGE PROBLEM FAULT LATCHED LOW Figure 24. High Side Overvoltage Protection FAULT is asserted low (but not latched) to indicate a startup failure. Only if the input overvoltage condition is removed before Time Point 5 does the start-up sequence resume at the second timing cycle. At this point in time, the GATE pin voltage is allowed to ramp up, FAULT is pulled to logic high and the circuit breaker is armed. Should, at any time after Time Point 5, a supply overvoltage condition develop (VFILTER > 1.236V), the electronic circuit breaker will trip, the GATE will be pulled low to turn off the external MOSFET and FAULT will be asserted low and latched. This sequence is shown in detail at Time Point B. Low Side (Output) Overvoltage Protection A Zener diode can be used in a similar fashion to detect/ protect the system against a supply overvoltage condition on the load (or low) side of the pass transistor. In this case, the Zener diode is connected from the load to the LTC4211’s FILTER pin, as shown in Figure 25. An additional diode, D1, prevents the FILTER pin from pulling low during an output short-circuit. Figure 26 illustrates the timing diagram for a low side output overvoltage condition. In this example, the LTC4211 can only sense the overvoltage supply condition after Time Point 5 and the GATE pin has 4211f 31 LTC4211 U W U U APPLICATIO S I FOR ATIO BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) D1 IN4148 LONG 5V R3 10k R4 10Ω C1 0.1µF Z1* RSENSE 0.007Ω Q1 Si4410DY VOUT 5V 5A SHORT FAULT R5 10k SHORT RESET Z2 6.2V SHORT ON/OFF 1 2 R6 10k R7 10k 3 4 CFILTER 47pF R1 36k LTC4211 RESET FAULT ON VCC FILTER SENSE TIMER CTIMER 5 GND 10nF GATE FB + CLOAD 10 9 R2 15k 8 7 6 4211 F25 LONG GND Z1 = 1SMA10A OR SMAJ10A Z2 = 1N4691 * OPTIONAL Figure 25. LTC4211MS Low Side Overvoltage Protection Implementation OVERVOLTAGE SENSED BY FILTER PIN CIRCUIT BREAKER TRIPS 1 2 VCC 345 6A 6B ON TIMER GATE VOUT FPD RESET FILTER VREF FAULT 4211 F26 Figure 26. Low Side Overvoltage Protection 4211f 32 LTC4211 U W U U APPLICATIO S I FOR ATIO ramped up to its nominal operating value. After Time Point␣ 5, a supply voltage fault occurs at the load and the Zener diode begins to conduct, causing VFILTER to increase. At Time Point 6A, VFILTER is greater than 1.236V, the circuit breaker is tripped, the GATE pin voltage is pulled to ground and FAULT is asserted low and latched. In either case, the LTC4211 can be configured to automatically initiate a start-up sequence. Please refer to the section on AutoRetry After a Fault for additional information. PCB Layout Considerations For proper operation of the LTC4211’s circuit breaker function, a 4-wire Kelvin connection to the sense resistors is highly recommended. A recommended PCB layout for the sense resistor, the power MOSFET and the GATE drive components around the LTC4211 is illustrated in Figure␣ 22. In Hot Swap applications where load currents can reach 10A or more, narrow PCB tracks exhibit more resistance than wider tracks and operate at more elevated temperatures. Since the sheet resistance of 1 ounce copper foil is approximately 0.54mΩ/square, track resistances add up quickly in high current applications. Thus, to keep PCB track resistance and temperature rise to a minimum, PCB track width must be appropriately sized. Consult Appendix A of LTC Application Note 69 for details on sizing and calculating trace resistances as a function of copper thickness. In the majority of applications, it will be necessary to use plated-through vias to make circuit connections from component layers to power and ground layers internal to the PC board. For 1 ounce copper foil plating, a good starting point is 1A of DC current per via, making sure the via is properly dimensioned so that solder completely fills any void. For other plating thicknesses, check with your PCB fabrication facility. 4211f 33 LTC4211 U APPE DIX Table 4 lists some current sense resistors that can be used with the circuit breaker. Table 5 lists some power MOSFETs that are available. Table 6 lists the web sites of several manufacturers. Since this information is subject to change, please verify the part numbers with the manufacturer. Table 4. Sense Resistor Selection Guide CURRENT LIMIT VALUE PART NUMBER DESCRIPTION MANUFACTURER 1A LR120601R050 0.05Ω 0.5W 1% Resistor IRC-TT 2A LR120601R025 0.025Ω 0.5W 1% Resistor IRC-TT 2.5A LR120601R020 0.02Ω 0.5W 1% Resistor IRC-TT 3.3A WSL2512R015F 0.015Ω 1W 1% Resistor Vishay-Dale 5A LR251201R010F 0.01Ω 1.5W 1% Resistor IRC-TT 10A WSR2R005F 0.005Ω 2W 1% Resistor Vishay-Dale Table 5. N-Channel Selection Guide CURRENT LEVEL (A) PART NUMBER DESCRIPTION MANUFACTURER 0 to 2 MMDF3N02HD Dual N-Channel SO-8 RDS(ON) = 0.1Ω, CISS = 455pF ON Semiconductor 2 to 5 MMSF5N02HD Single N-Channel SO-8 RDS(ON) = 0.025Ω, CISS = 1130pF ON Semiconductor 5 to 10 MTB50N06V Single N-Channel DD Pak RDS(ON) = 0.028Ω, CISS = 1570pF ON Semiconductor 10 to 20 MTB75N05HD Single N-Channel DD Pak RDS(ON) = 0.0095Ω, CISS = 2600pF ON Semiconductor Table 6. Manufacturers’ Web Sites MANUFACTURER WEB SITE TEMIC Semiconductor www.temic.com International Rectifier www.irf.com ON Semiconductor www.onsemi.com Harris Semiconductor www.semi.harris.com IRC-TT www.irctt.com Vishay-Dale www.vishay.com Vishay-Siliconix www.vishay.com Diodes, Inc. www.diodes.com 4211f 34 LTC4211 U PACKAGE DESCRIPTIO MS8 Package 8-Lead Plastic MSOP (Reference LTC DWG # 05-08-1660) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 0.254 (.010) 3.2 – 3.45 (.126 – .136) 8 0.52 (.206) REF 7 6 5 3.00 ± 0.102 (.118 ± .004) NOTE 4 4.88 ± 0.1 (.192 ± .004) DETAIL “A” 0° – 6° TYP GAUGE PLANE 0.42 ± 0.04 (.0165 ± .0015) TYP 1 0.53 ± 0.015 (.021 ± .006) 0.65 (.0256) BSC DETAIL “A” RECOMMENDED SOLDER PAD LAYOUT 2 3 4 1.10 (.043) MAX 0.86 (.034) REF 0.18 (.077) SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.22 – 0.38 (.009 – .015) 0.13 ± 0.05 (.005 ± .002) 0.65 (.0256) BCS MSOP (MS8) 0102 MS Package 10-Lead Plastic MSOP (Reference LTC DWG # 05-08-1661) 3.00 ± 0.102 (.118 ± .004) (NOTE 3) 0.889 ± 0.127 (.035 ± .005) 5.23 (.206) MIN 0.497 ± 0.076 (.0196 ± .003) REF 10 9 8 7 6 0.254 (.010) 3.2 – 3.45 (.126 – .136) 3.00 ± 0.102 (.118 ± .004) NOTE 4 4.88 ± 0.10 (.192 ± .004) DETAIL “A” 0° – 6° TYP GAUGE PLANE 1 2 3 4 5 0.50 0.305 ± 0.038 (.0197) (.0120 ± .0015) BSC TYP RECOMMENDED SOLDER PAD LAYOUT 0.53 ± 0.01 (.021 ± .006) 0.86 (.034) REF 1.10 (.043) MAX DETAIL “A” 0.18 (.007) SEATING PLANE NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.17 – 0.27 (.007 – .011) 0.13 ± 0.05 (.005 ± .002) 0.50 (.0197) TYP MSOP (MS) 1001 S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch) (Reference LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.014 – 0.019 (0.355 – 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 8 7 6 5 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) BSC 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) SO8 1298 1 2 3 4 4211f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LTC4211 U TYPICAL APPLICATIO S LOW COST OVERVOLTAGE PROTECTION There is an alternative method to implementing the overvoltage protection using a resistor divider at the FILTER pin (see Figures 27 and 28). In this implementation, the SLOW COMP is NULL in Normal Mode. Only the FAST COMP circuit breaker is available and the current limit level is 150mV/RSENSE. During the soft-cycle, the inrush current servo loop is at 50mV/RSENSE. So, the heavy load should only turn on at/after the end of second cycle where the RESET pin goes high. BACKPLANE PCB EDGE CONNECTOR CONNECTOR (FEMALE) (MALE) LONG 5V R4 10k R3 10Ω C1 0.1µF Z1* RSENSE 0.007Ω Q1 Si4410DY VOUT 5V 5A SHORT FAULT R5 10k SHORT RESET R8 4.3k SHORT ON/OFF 2 R6 10k R7 10k 3 R9 750Ω R1 36k LTC4211 1 4 RESET FAULT ON VCC FILTER SENSE GATE TIMER CTIMER 5 GND 10nF FB 10 + CLOAD 9 R2 15k 8 7 6 4211 F29 LONG GND Z1 = 1SMA10A OR SMAJ10A * OPTIONAL Figure 27. LTC4211MS High Side Overvoltage Protection Implementation (In Normal Mode, SLOW COMP is Disabled, In Soft-Start Cycle, ISOFTSTART is Still 50mV/RSENSE) BACKPLANE PCB EDGE CONNECTOR CONNECTOR (MALE) (FEMALE) LONG 5V R3 10k R7 10Ω C1 0.1µF Z1* RSENSE 0.007Ω Q1 Si4410DY VOUT 5V 5A SHORT FAULT R4 10k SHORT RESET SHORT ON/OFF 1 2 R5 10k R6 10k 3 RESET FAULT ON VCC FILTER SENSE 4 TIMER CTIMER 5 GND 10nF LONG GND R1 3.6k LTC4211 GATE FB 10 + CLOAD 9 R2 750Ω 8 7 R8 750Ω 6 4211 F30 Z1 = 1SMA10A OR SMAJ10A * OPTIONAL Figure 28. LTC4211MS Low Side Overvoltage Protection Implementation (In Normal Mode, SLOW COMP is Disabled, In Soft-Start Cycle, ISOFTSTART is Still 50mV/RSENSE) RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC1421 Two Channels, Hot Swap Controller 24-Pin, Operates from 3V to 12V and Supports – 12V LTC1422 Single Channel, Hot Swap Controller 8-Pin, Operates from 2.7V to 12V LT1640AL/LT1640AH Negative Voltage Hot Swap Controller 8-Pin, Operates from –10V to –80V LT1641-1/LT1641-2 Positive Voltage Hot Swap Controller 8-Pin, Operates from 9V to 80V, Latch-Off/Auto Retry LTC1642 Single Channel, Hot Swap Controller 16-Pin, Overvoltage Protection to 33V LTC1644 PCI Hot Swap Controller 16-Pin, 3.3V, 5V and ±12V, 1V Precharge, PCI Reset Logic LTC1647 Dual Channel, Hot Swap Controller 8-Pin, 16-Pin, Operates from 2.7V to 16.5V LTC4230 Triple Hot Swap Controller with Multifunction Current Control Operates from 1.7V to 16.5V 4211f 36 Linear Technology Corporation LT/TP 0702 2K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2001