19-2083; Rev 0; 8/01 16-Bit ADC, 200ksps, 5V Single-Supply with Reference The MAX1132/MAX1133 feature internal calibration circuitry to correct linearity and offset errors. On-demand calibration allows the user to optimize performance. Three user-programmable logic outputs are provided for the control of an 8-channel mux or a PGA. Applications Industrial Process Control Features ♦ 200ksps (Bipolar) and 150ksps (Unipolar) Sampling ADC ♦ 16-Bits, No Missing Codes ♦ 1.5LSB INL Guaranteed ♦ 85dB (min) SINAD ♦ +5V Single-Supply Operation ♦ Low-Power Operation, 7.5mA (Unipolar Mode) ♦ 2.5µA Shutdown Mode ♦ Software-Configurable Unipolar and Bipolar Input Ranges 0 to +12V and ±12V (MAX1132) 0 to +4.096V and ±4.096V (MAX1133) Internal or External Reference ♦ Internal or External Clock ♦ SPI/QSPI/MICROWIRE-Compatible Serial Interface ♦ Three User-Programmable Logic Outputs ♦ Small 20-Pin SSOP Package Ordering Information PART TEMP. RANGE PIN-PACKAGE INL (LSB) MAX1132ACAP* 0°C to +70°C 20 SSOP ±1.5 MAX1132BCAP 0°C to +70°C 20 SSOP ±2.5 Ordering Information continued at end of data sheet. Industrial I/O Modules Pin Configuration Data-Acquisition Systems Medical Instruments Portable and Battery-Powered Equipment TOP VIEW REF 1 20 AIN REFADJ 2 19 AGND AGND 3 18 CREF AVDD 4 DGND 5 SHDN Functional Diagram appears at end of data sheet. Typical Application Circuit appears at end of data sheet. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. 6 17 CS MAX1132 MAX1133 16 DIN 15 DVDD P2 7 14 DGND P1 8 13 SCLK P0 9 12 RST SSTRB 10 11 DOUT SSOP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1132/MAX1133 General Description The MAX1132/MAX1133 are 200ksps, 16-bit ADCs. These serially interfaced ADCs connect directly to SPI™, QSPI™, and MICROWIRE™ devices without external logic. They combine an input scaling network, internal track/hold, clock, a +4.096V reference, and three general-purpose digital output pins (for external multiplexer or PGA control) in a 20-pin SSOP package. The excellent dynamic performance (SINAD ≥ 85dB), high-speed (200ksps), and low power (7.5mA) of these ADCs, make them ideal for applications such as industrial process control, instrumentation, and medical applications. The MAX1132 accepts input signals of 0 to +12V (unipolar) or ±12V (bipolar), while the MAX1133 accepts input signals of 0 to +4.096V (unipolar) or ±4.096V (bipolar). Operating from a single +4.75V to +5.25V analog supply and a +4.75V to +5.25V digital supply, power-down modes reduce current consumption to 1mA at 10ksps and further reduce supply current to less than 20µA at slower data rates. A serial strobe output (SSTRB) allows direct connection to the TMS320 family of digital signal processors. The MAX1132/MAX1133 user can select either the internal clock, or an external serial-interface clock for the ADC to perform analog-to-digital conversions. MAX1132/MAX1133 16-Bit ADC, 200ksps, 5V Single-Supply with Reference ABSOLUTE MAXIMUM RATINGS AVDD to AGND, DVDD to DGND .............................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V AIN to AGND.....................................................................±16.5V REFADJ, CREF, REF to AGND.................-0.3V to (AVDD + 0.3V) Digital Inputs to DGND.............................................-0.3V to +6V Digital Outputs to DGND .........................-0.3V to (DVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 20-Pin SSOP (derate 8.00mW/°C above +70°C) .........640mW Operating Temperature Ranges MAX113_CAP ......................................................0°C to +70°C MAX113_EAP....................................................-40°C to +85°C Storage Temperature Range .............................-60°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (AVDD = DVDD = +5V ±5%, fSCLK = 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps), bipolar input, external VREF = +4.096V, VREFADJ = AVDD, CREF = 2.2µF, CCREF = 1µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) 16 INL Bipolar mode ±1.5 MAX113_B ±2.5 No Missing Codes Differential Nonlinearity 16 DNL Bipolar mode -1 +1 MAX113_B -1 +1.75 0.77 Unipolar Offset Error Bipolar LSB Bits MAX113_A Transition Noise Gain Error (Note 3) Bits MAX113_A LSB LSBRMS MAX1132 ±4 MAX1133 ±2 MAX1132 ±6 mV ±5 MAX1133 Unipolar ±0.2 Bipolar ±0.3 %FSR Offset Drift (Bipolar and Unipolar) Excluding reference drift ±1 ppm/oC Gain Drift (Bipolar and Unipolar) Excluding reference drift ±1 ppm/oC DYNAMIC SPECIFICATIONS (5kHz sine-wave input, 200ksps, 4.8MHz clock, bipolar input mode. MAX1132: 24Vp-p. MAX1133: 8.192Vp-p) SINAD SNR THD SFDR 2 fIN = 5kHz 85 fIN = 100kHz fIN = 5kHz 87 fIN = 100kHz -90 fIN = 100kHz fIN = 100kHz dB 92 fIN = 5kHz fIN = 5kHz dB 85 -92 92 96 _______________________________________________________________________________________ dB dB 16-Bit ADC, 200ksps, 5V Single-Supply with Reference (AVDD = DVDD = +5V ±5%, fSCLK = 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps), bipolar input, external VREF = +4.096V, VREFADJ = AVDD, CREF = 2.2µF, CCREF = 1µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ANALOG INPUT MAX1132 Input Range MAX1133 MAX1132 Input Impedance MAX1133 Unipolar Bipolar Unipolar Bipolar 0 12 -12 12 0 4.096 -4.096 4.096 Unipolar 7.5 10.0 Bipolar 5.9 7.9 Unipolar 100 1000 Bipolar 3.4 4.5 Input Capacitance V kΩ 32 pF CONVERSION RATE Internal Clock Frequency 4 MHz Aperture Delay tAD 10 ns Aperture Jitter tAS 50 ps MODE 1 (24 External Clock Cycles per Conversion) External Clock Frequency fSCLK Sample Rate fS = fSCLK /24 Conversion Time (Note 4) tCONV+ACQ = 24 / fSCLK Unipolar 0.1 3 Bipolar 0.1 4.8 Unipolar 4.17 125 Bipolar 4.17 200 Unipolar 8 240 Bipolar 5 240 MHz ksps µs MODE 2 (Internal Clock Mode) External Clock Frequency (Data Transfer Only) Conversion Time SSTRB low pulse width 4 8 MHz 6 µs Unipolar 1.82 Bipolar 1.14 fSCLK Unipolar or bipolar 0.1 4.8 MHz Sample Rate fS = fSCLK /32 Unipolar or bipolar 3.125 150 ksps Conversion Time (Note 4) tCONV+ACQ = 32 / fSCLK Unipolar or bipolar 6.67 320 µs Acquisition Time µs MODE 3 (32 External Clock Cycles per Conversion) External Clock Frequency INTERNAL REFERENCE Output Voltage VREF 4.056 4.096 4.136 V REF Short-Circuit Current 24 mA Output Tempco ±20 ppm/oC _______________________________________________________________________________________ 3 MAX1132/MAX1133 ELECTRICAL CHARACTERISTICS (continued) MAX1132/MAX1133 16-Bit ADC, 200ksps, 5V Single-Supply with Reference ELECTRICAL CHARACTERISTICS (continued) (AVDD = DVDD = +5V ±5%, fSCLK = 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps), bipolar input, external VREF = +4.096V, VREFADJ = AVDD, CREF = 2.2µF, CCREF = 1µF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS Capacitive Bypass at REF MIN TYP 0.47 Maximum Capacitive Bypass at REFADJ REFADJ Output Voltage REFADJ Input Range For small adjustments from 4.096V REFADJ Buffer Disable Threshold To power-down the internal reference MAX UNITS 10 µF 10 µF 4.096 V ±100 AVDD 0.5V Buffer Voltage Gain mV AVDD 0.1V 1 V V/V EXTERNAL REFERENCE (Reference buffer disabled. Reference applied to REF) Input Range (Notes 5 and 6) 3.0 Input Current 4.096 VREF = 4.096V, fSCLK = 4.8MHz 250 VREF = 4.096V, fSCLK = 0 230 In power-down, fSCLK = 0 0.1 4.2 V µA DIGITAL INPUTS Input High Voltage VIH Input Low Voltage VIL Input Leakage Input Hysteresis Input Capacitance IIN 2.4 V VIN = 0 or DVDD 0.8 V ±1 µA VHYST 0.2 V CIN 10 pF DIGITAL OUTPUTS Output High Voltage VOH Output Low Voltage VOL Three-State Leakage Current IL Three-State Output Capacitance ISOURCE = 0.5mA DVDD 0.5 V ISINK = 5mA 0.4 ISINK = 16mA 0.8 CS = DVDD ±10 CS = DVDD 10 V µA pF POWER SUPPLIES Analog Supply (Note 7) AVDD Digital Supply (Note 7) DVDD 4.75 4.75 Digital Supply Current Power-Supply Rejection Ratio (Note 8) 4 IANALOG IDIGITAL PSRR 5.25 V V 5 5.25 5 8 Bipolar mode 8.5 11 SHDN = 0, or software power-down mode 0.3 10 µA Unipolar or bipolar mode 2.5 3.5 mA SHDN = 0, or software power-down mode 2.2 10 µA AVDD = DVDD = 4.75V to 5.25V 72 Unipolar mode Analog Supply Current 5 _______________________________________________________________________________________ mA dB 16-Bit ADC, 200ksps, 5V Single-Supply with Reference (AVDD = DVDD = +5V ±5%, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER Acquisition Time SYMBOL CONDITIONS MIN TYP MAX UNITS tACQ 1.14 DIN to SCLK Setup tDS 50 DIN to SCLK Hold tDH 0 ns SCLK to DOUT Valid tDO 70 ns CS Fall to DOUT Enable tDV CLOAD = 50pF 80 ns CS Rise to DOUT Disable tTR CLOAD = 50pF 80 ns CS to SCLK Rise Setup tCSS CS to SCLK Rise Hold SCLK High Pulse Width SCLK Low Pulse Width SCLK Fall to SSTRB µs ns 100 ns tCSH 0 ns tCH 80 ns tCL 80 ns CLOAD = 50pF 80 ns CS Fall to SSTRB Enable tSDV CLOAD = 50pF, external clock mode 80 ns CS Rise to SSTRB Disable tSTR CLOAD = 50pF, external clock mode 80 ns SSTRB Rise to SCLK Rise tSCK Internal clock mode RST Pulse Width tSSTRB tRS 0 ns 208 ns Note 1: Tested at AVDD = DVDD = +5V, bipolar input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset error have been nulled. Note 3: Offset nulled. Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period, clock has 50% duty cycle. Includes the acquisition time. Note 5: ADC performance is limited by the converter’s noise floor, typically 300µVp-p. Note 6: When an external reference has a different voltage than the specified typical value, the full scale of the ADC will scale proportionally. Note 7: Electrical characteristics are guaranteed from AVDD(MIN) = DVDD(MIN) to AVDD(MAX) = DVDD(MAX). For operations beyond this range, see the Typical Operating Characteristics. For guaranteed specifications beyond the limits, contact the factory. Note 8: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage. _______________________________________________________________________________________ 5 MAX1132/MAX1133 TIMING CHARACTERISTICS (Figures 5 and 6) Typical Operating Characteristics (MAX1132/MAX1133: AVDD = DVDD = +5V , fSCLK = 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps), bipolar input, external REF = +4.096V, 0.22µF bypassing on REFADJ, 2.2µF on REF, 1µF on CREF, TA = 25°C, unless otherwise noted.) DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE 0 -0.5 -1.0 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 11.5 6865 MAX1132 toc04 B -2 C -3 B 10.3 10.1 A 9.9 -40 C 0.02 B 0.01 20 40 60 80 TOTAL SUPPLY CURRENT vs. CONVERSION RATE (USING SHUTDOWN) A: AVDD, DVDD = +4.75V B: AVDD, DVDD = +5.00V C: AVDD, DVDD = +5.25V 0.03 0 -20 TEMPERATURE (°C) A 100 TOTAL SUPPLY CURRENT (mA) -1 C 10.5 13729 27457 41185 54913 20593 34321 48049 61777 DIGITAL OUTPUT CODE 0.04 GAIN ERROR (% FULL SCALE) OFFSET VOLTAGE (mV) A: AVDD, DVDD = +4.75V B: AVDD, DVDD = +5.00V C: AVDD, DVDD = +5.25V 10.7 GAIN ERROR vs. TEMPERATURE OFFSET VOLTAGE vs. TEMPERATURE 0 10.9 9.5 1 13729 27457 41185 54913 20593 34321 48049 61777 DIGITAL OUTPUT CODE MAX1132 toc05 6865 11.1 9.7 -1.0 1 A: AVDD, DVDD = +4.75V B: AVDD, DVDD = +5.00V C: AVDD, DVDD = +5.25V 11.3 -0.8 -1.5 MAX1132 toc03 0.8 MAX1132 toc06 0.5 MAX1132 toc02 1.0 1.0 DIFFERENTIAL NONLINEARITY (LSB) MAX1132 toc01 INTEGRAL NONLINEARITY (LSB) 1.5 TOTAL SUPPLY CURRENT vs. TEMPERATURE TOTAL SUPPLY CURRENT (mA) INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE 10 1.00 0.10 A 0 -20 0 20 40 60 0.01 -40 80 -20 0 20 40 60 80 0 TEMPERATURE (°C) TEMPERATURE (°C) NORMALIZED REF VOLTAGE vs. TEMPERATURE 1 10 MAX1132 toc07 0 fSAMPLE = 200kHz fIN = 5kHz -20 100 80 AMPLITUDE (dB) AMPLITUDE (dB) -40 -60 -80 fSAMPLE = 200kHz 90 1.005 1.000 1000 SINAD PLOT FFT PLOT 1.010 100 CONVERSION RATE (ksps) MAX1132 toc08 -40 MAX1132 toc09 -4 NORMALIZED REF VOLTAGE (V) MAX1132/MAX1133 16-Bit ADC, 200ksps, 5V Single-Supply with Reference 70 60 50 40 30 0.995 20 -100 10 -120 0.990 -40 -20 0 20 40 TEMPERATURE (°C) 6 60 80 0 0 9 18 27 36 45 54 63 72 81 90 99 FREQUENCY (kHz) 0.1 1 10 FREQUENCY (kHz) _______________________________________________________________________________________ 100 16-Bit ADC, 200ksps, 5V Single-Supply with Reference SFDR PLOT 110 100 THD PLOT 0 -20 90 -30 80 AMPLITUDE (dB) AMPLITUDE (dB) fSAMPLE = 200kHz -10 MAX1132 toc11 fSAMPLE = 200kHz MAX1132 toc10 120 70 60 50 40 -40 -50 -60 -70 -80 30 20 -90 10 -100 0 -110 0.1 1 10 100 0.1 FREQUENCY (kHz) 1 10 100 FREQUENCY (kHz) Pin Description PIN NAME FUNCTION Reference Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In internal reference mode, the reference buffer provides a +4.096V nominal output, externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling REFADJ to AVDD. Bypass to AGND with a 2.2µF capacitor when using the internal reference. 1 REF 2 REFADJ 3 AGND Analog Ground. This is the primary analog ground (Star Ground). 4 AVDD Analog Supply. 5V ±5%. Bypass AVDD to AGND (pin 3) with a 0.1µF capacitor. 5 DGND Digital Ground 6 SHDN Shutdown Control Input. Drive SHDN low to put the ADC in shutdown mode. 7 P2 User-Programmable Output 2 8 P1 User-Programmable Output 1 9 P0 User-Programmable Output 0 10 SSTRB Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC begins a conversion and goes high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period before the MSB decision. It is high impedance when CS is high in external clock mode. 11 DOUT Serial Data Output. MSB first, straight binary format for unipolar input, two’s complement for bipolar input. Each bit is clocked out of DOUT at the falling edge of SCLK. 12 RST Reset Input. Drive RST low to put the device in the power-on default mode. See the Power-On Reset section. Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to AGND with 0.22µF. When using an external reference, connect REFADJ to AVDD to disable the internal bandgap reference. _______________________________________________________________________________________ 7 MAX1132/MAX1133 Typical Operating Characteristics (continued) (MAX1132/MAX1133: AVDD = DVDD = +5V , fSCLK = 4.8MHz, external clock (50% duty cycle), 24 clocks/conversion (200ksps), bipolar input, external REF = +4.096V, 0.22µF bypassing on REFADJ, 2.2µF on REF, 1µF on CREF, TA = 25°C, unless otherwise noted.) 16-Bit ADC, 200ksps, 5V Single-Supply with Reference MAX1132/MAX1133 Pin Description (continued) PIN NAME FUNCTION 13 SCLK Serial Data Clock Input. Serial data on DIN is loaded on the rising edge of SCLK, and serial data is updated on DOUT on the falling edge of SCLK. In external clock mode, SCLK sets the conversion speed. 14 DGND Digital Ground. Connect to pin 5. 15 DVDD Digital Supply. 5V ±5%. Bypass DVDD to DGND (pin 14) with a 0.1µF capacitor. 16 DIN Serial Data Input. Serial data on DIN is latched on the rising edge of SCLK. 17 CS Chip-Select Input. Drive CS low to enable the serial interface. When CS is high, DOUT is high impedance. In external clock mode, SSTRB is high impedance when CS is high. 18 CREF Reference Buffer Bypass. Bypass CREF to AGND (pin 3) with 1µF. 19 AGND Analog Ground. Connect pin 19 to pin 3. 20 AIN Analog Input Detailed Description The MAX1132/MAX1133 analog-to-digital converters (ADCs) use a successive-approximation technique and input track/hold (T/H) circuitry to convert an analog signal to a 16-bit digital output. The MAX1132/MAX1133 easily interfaces to microprocessors (µPs). The data bits can be read either during the conversion in external clock mode or after the conversion in internal clock mode. In addition to a 16-bit ADC, the MAX1132/MAX1133 include an input scaler, an internal digital microcontroller, calibration circuitry, an internal clock generator, and an internal bandgap reference. The input scaler for the MAX1132 enables conversion of input signals ranging from 0 to +12V (unipolar input) or ±12V (bipolar input). The MAX1133 accepts 0 to +4.096V (unipolar input) or ±4.096V (bipolar input). Input range selection is software controlled. Calibration To minimize linearity, offset, and gain errors, the MAX1132/MAX1133 have on-demand software calibration. Initiate calibration by writing a Control-Byte with bit M1 = 0, and bit M0 = 1 (see Table 1). Select internal or external clock for calibration by setting the INT/EXT bit in the Control Byte. Calibrate the MAX1132/MAX1133 with the clock used for performing conversions. Offsets resulting from synchronous noise (such as the conversion clock) are canceled by the MAX1132/ MAX1133’s calibration circuitry. However, because the magnitude of the offset produced by a synchronous signal depends on the signal’s shape, recalibration may be appropriate if the shape or relative timing of the 8 clock or other digital signals change, as might occur if more than one clock signal or frequency is used. Input Scaler The MAX1132/MAX1133 have an input scaler which allows conversion of true bipolar input voltages while operating from a single +5V supply. The input scaler attenuates and shifts the input as necessary to map the external input range to the input range of the internal DAC. The MAX1132 analog input range is 0 to +12V (unipolar) or ±12V (bipolar). The MAX1133 analog input range is 0 to +4.096V (unipolar) or ±4.096V (bipolar). Unipolar and bipolar mode selection is configured with bit 6 of the serial Control Byte. Figure 1 shows the equivalent input circuit of the MAX1132/MAX1133. The resistor network on the analog input provides ±16.5V fault protection. This circuit limits the current going into or out of the pin to less than 2mA. The overvoltage protection is active, even if the device is in a power-down mode, or if AVDD = 0. Digital Interface The digital interface pins consist of SHDN, RST, SSTRB, DOUT, SCLK, DIN and CS. Bringing SHDN low, places the MAX1132/MAX1133 in its 2.5µA shutdown mode. A logic low on RST halts the MAX1132/MAX1133 operation and returns the part to its power-on reset state. In external clock mode, SSTRB is is low and pulses high for one clock cycle at the start of conversion. In internal clock mode, SSTRB goes low at the start of the conversion and goes high to indicate the conversion is finished. _______________________________________________________________________________________ 16-Bit ADC, 200ksps, 5V Single-Supply with Reference VOLTAGE REFERENCE S1 UNIPOLAR R1 2.5kΩ R2 CHOLD 30pF TRACK S2 AIN T/H OUT R3 HOLD TRACK HOLD S3 S1 = BIPOLAR/UNIPOLAR S2, S3 = T/H SWITCH R2 = 7.6kΩ (MAX1132) OR 2.5kΩ (MAX1133) R3 = 3.9kΩ (MAX1132) OR INFINITY (MAX1133) Figure 1. Equivalent Input Circuit The DIN input accepts Control Byte data which is clocked in on each rising edge of SCLK. After CS goes low or after a conversion or calibration completes, the first logic “1” clocked into DIN is interpreted as the START bit, the MSB of the 8-bit Control Byte. The SCLK input is the serial data transfer clock which clocks data in and out of the MAX1132/MAX1133. SCLK also drives the A/D conversion steps in external clock mode (see Internal and External Clock Modes section). DOUT is the serial output of the conversion result. DOUT is updated on the falling edge of SCLK. DOUT is high-impedance when CS is high. CS must be low for the MAX1132/MAX1133 to accept a Control Byte. The serial interface is disabled when CS is high. User-Programmable Outputs The MAX1132/MAX1133 have three user-programmable outputs, P0, P1 and P2. The power-on default state for the programmable outputs is zero. These are pushpull CMOS outputs suitable for driving a multiplexer, a PGA, or other signal preconditioning circuitry. The userprogrammable outputs are controlled by bits 0, 1, and 2 of the Control Byte (Table 2). The user-programmable outputs are set to zero during power-on reset (POR) or when RST goes low. During hardware or software shutdown P0, P1, and P2 are unchanged and remain low-impedance. Start a conversion by clocking a Control Byte into the device’s internal shift register. With CS low, each rising edge on SCLK clocks a bit from DIN into the MAX1132/MAX1133’s internal shift register. After CS goes low or after a conversion or calibration completes, the first arriving logic “1” is defined as the start bit of the Control Byte. Until this first start bit arrives, any number of logic “0” bits can be clocked into DIN with no effect. If at any time during acquisition or conversion, CS is brought high and then low again, the part is placed into a state where it can recognize a new start bit. If a new start bit occurs before the current conversion is complete, the conversion is aborted and a new acquisition is initiated. Internal and External Clock Modes The MAX1132/MAX1133 may use either the external serial clock or the internal clock to perform the successive-approximation conversion. In both clock modes, the external clock shifts data in and out of the MAX1132/MAX1133. Bit 5 (INT/EXT) of the Control Byte programs the clock mode. External Clock In external clock mode, the external clock not only shifts data in and out, but it also drives the ADC conversion steps. In short acquisition mode, SSTRB pulses high for one clock period after the seventh falling edge of SCLK following the start bit. The MSB of the conversion is available at DOUT on the eighth falling edge of SCLK (Figure 2). In long acquisition mode, when using external clock, SSTRB pulses high for one clock period after the fifteenth falling edge of SCLK following the start bit. The MSB of the conversion is available at DOUT on the sixteenth falling edge of SCLK (Figure 3). In external clock mode, SSTRB is high-impedance when CS is high. In external clock mode, CS is normally held low during the entire conversion. If CS goes high during the conversion, SCLK is ignored until CS goes low. This allows external clock mode to be used with 8bit bytes. Internal Clock In internal clock mode, the MAX1132/MAX1133 generates its own conversion clock. This frees the microprocessor from the burden of running the SAR conversion clock, and allows the conversion results to be read back at the processor’s convenience, at any clock rate up to 8MHz. SSTRB goes low at the start of the conversion and goes high when the conversion is complete. SSTRB will be _______________________________________________________________________________________ 9 MAX1132/MAX1133 Starting a Conversion BIPOLAR MAX1132/MAX1133 16-Bit ADC, 200ksps, 5V Single-Supply with Reference Table 1. Control Byte Format BIT NAME 7 (MSB) START The first logic “1” bit, after CS goes low, defines the beginning of the Control Byte 6 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, analog input signals from 0 to +12V (MAX1132) or 0 to VREF (MAX1133) can be converted. In bipolar mode analog input signals from -12V to +12V (MAX1132) or -VREF to +VREF (MAX1133) can be converted. 5 INT/EXT Selects the internal or external conversion clock. 1 = Internal, 0 = External. 4 M1 3 DESCRIPTION M0 2 1 0(LSB) P2 P1 P0 M1 M0 MODE 0 0 24 External clocks per conversion (short acquisition mode) 0 1 Start Calibration. Starts internal calibration. 1 0 Software power-down mode 1 1 32 External clocks per conversion (long acquisition mode) These three bits are stored in a port register and output to pins P2, P1, P0 for use in addressing a mux or PGA. These three bits are updated in the port register simultaneously when a new Control Byte is written. Table 2. User-Programmable Outputs OUTPUT PIN PROGRAMMED THROUGH CONTROL BYTE POWER-ON OR RST DEFAULT P2 Bit 2 0 P1 Bit 1 0 P0 Bit 0 0 DESCRIPTION User-programmable outputs follow the state of the Control Byte’s three LSBs and are updated simultaneously when a new Control Byte is written. Outputs are push-pull. In hardware and software shutdown, these outputs are unchanged and remain low-impedance. CS tACQ SCLK DIN 1 UNI/ START BIP 4 INT/ EXT M1 8 M0 P2 P1 15 12 21 24 P0 SSTRB B15 MSB B14 DOUT A/D STATE IDLE ACQUISITION B13 B12 B11 B10 B9 B4 B3 B2 B1 B0 LSB CONVERSION Figure 2. Short Acquisition Mode (24-Clock Cycles) External Clock, Bipolar Mode 10 ______________________________________________________________________________________ FILLED WITH ZEROS IDLE 16-Bit ADC, 200ksps, 5V Single-Supply with Reference MAX1132/MAX1133 CS tACQ SCLK DIN 1 4 UNI/ START BIP INT/ EXT M1 8 M0 P2 P1 15 19 29 32 P0 SSTRB B15 MSB DOUT A/D STATE IDLE B14 B13 ACQUISITION B4 CONVERSION B3 B2 B1 B0 FILLED WITH ZEROS LSB IDLE Figure 3. Long Acquisition Mode (32-Clock Cycles) External Clock, Bipolar Mode low for a maximum of 6µs, during which time SCLK should remain low for best noise performance. An internal register stores data when the conversion is in progress. SCLK clocks the data out of the internal storage register at any time after the conversion is complete. The MSB of the conversion is available at DOUT when SSTRB goes high. The subsequent 15 falling edges on SCLK shift the remaining bits out of the internal storage register (Figure 4). CS does not need to be held low once a conversion is started. When internal clock mode is selected, SSTRB does not go into a high-impedance state when CS goes high. Figure 5 shows the SSTRB timing in internal clock mode. In internal clock mode, data can be shifted in to the MAX1132/MAX1133 at clock rates up to 4.8MHz, provided that the minimum acquisition time, tACQ, is kept above 1.14µs in bipolar mode and 1.82µs in unipolar mode. Data can be clocked out at 8MHz. Output Data The output data format is straight binary for unipolar conversions and two’s complement in bipolar mode. In both modes the MSB is shifted out of the MAX1132/ MAX1133 first. Data Framing The falling edge of CS does NOT start a conversion on the MAX1132/MAX1133. The first logic high clocked into DIN is interpreted as a start bit and defines the first bit of the Control Byte. A conversion starts on the falling edge of SCLK, after the seventh bit of the Control Byte (the P1 bit) is clocked into DIN. The start bit is defined as: The first high bit clocked into DIN with CS low anytime the converter is idle, e.g., after AV DD is applied, or as the first high bit clocked into DIN after CS is pulsed high, then low. OR If a falling edge on CS forces a start bit before the conversion or calibration is complete, then the current operation will be terminated and a new one started. Applications Information Power-On Reset When power is first applied to the MAX1132/MAX1133 or if RST is pulsed low, the internal calibration registers are set to their default values. The user-programmable registers (P0, P1, and P2) are low, and the device is configured for bipolar mode with internal clocking. Calibration To compensate the MAX1132/MAX1133 for temperature drift and other variations, they should be periodically calibrated. After any change in ambient temperature more than 10°C the device should be recalibrated. A 100mV change in supply voltage or any change in the reference voltage should be followed by a calibration. Calibration corrects for errors in gain, offset, integral nonlinearity, and differential nonlinearity. The MAX1132/ MAX1133 should be calibrated after power-up or the assertion of reset. Make sure the power supplies and the reference voltage have fully settled prior to initiating the calibration sequence. Initiate calibration by setting M1 = 0 and M0 = 1 in the Control-Byte. In internal clock mode, SSTRB goes low at ______________________________________________________________________________________ 11 MAX1132/MAX1133 16-Bit ADC, 200ksps, 5V Single-Supply with Reference CS tACQ 1 SCLK UNI/ START BIP DIN 4 INT/ EXT M1 9 8 M0 P2 P1 21 24 P0 SSTRB tCONV B15 MSB DOUT B14 B13 B4 B3 B2 B1 B0 LSB FILLED WITH ZEROS Figure 4. Internal Clock Mode Timing, Short Acquisition, Bipolar Mode CS tCONV tCSS tSCK tCSH SSTRB t SSTRB SCLK P0 CLOCK IN NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION. Figure 5. Internal Clock Mode SSTRB Detailed Timing CS tSTR tSDV SSTRB tSSTRB tSSTRB SCLK P1 CLOCKED IN Figure 6. External Clock Mode SSTRB Detailed Timing 12 ______________________________________________________________________________________ 16-Bit ADC, 200ksps, 5V Single-Supply with Reference Reference The MAX1132/MAX1133 can be used with an internal or external reference. An external reference can be connected directly at the REF pin or at the REFADJ pin. CREF is an internal reference node and must be bypassed with a 1µF capacitor when using either the internal or an external reference. Internal Reference When using the MAX1132/MAX1133’s internal reference, place a 0.22µF ceramic capacitor from REFADJ to AGND and place a 2.2µF capacitor from REF to AGND. Fine adjustments can be made to the internal reference voltage by sinking or sourcing current at REFADJ. The input impedance of REFADJ is nominally 9kΩ. The internal reference voltage is adjustable to ±1.5% with the circuit of Figure 7. External reference An external reference can be placed at either the input (REFADJ) or the output (REF) of the MAX1132/ MAX1133’s internal buffer amplifier. When connecting an external reference to REFADJ, the input impedance is typically 9kΩ. Using the buffered REFADJ input makes buffering of the external reference unnecessary, however, the internal buffer output must be bypassed at REF with a 2.2µF capacitor. When connecting an external reference at REF, REFADJ must be connected to AVDD. Then the input impedance at REF is a minimum of 164kΩ for DC currents. During conversion, an external reference at REF must deliver 250µA DC load current and have an output impedance of 10Ω or less. If the reference has a higher output impedance or is noisy, bypass it at the REF pin with a 4.7µF capacitor. Analog Input The MAX1132/MAX1133 use a capacitive DAC that provides an inherent track/hold function. Drive AIN with a source impedance less than 10Ω. Any signal conditioning circuitry must settle with 16-bit accuracy in less than 500ns. Limit the input bandwidth to less than half the sampling frequency to eliminate aliasing. The MAX1132/MAX1133 has a complex input impedance which varies from unipolar to bipolar mode (Figure 1). +5V MAX1132 510kΩ 100kΩ REFADJ 24kΩ 0.22µF Figure 7. MAX1132 Reference-Adjust Circuit Input Range The analog input range in unipolar mode is 0 to +12V for the MAX1132, and 0 to +4.096V for the MAX1133. In bipolar mode, the analog input can be -12V to +12V for the MAX1132, and -4.096V to +4.096V for the MAX1133. Unipolar and bipolar mode is programmed with the UNI/BIP bit of the Control Byte. When using a reference other than the MAX1132/MAX1133’s internal +4.096V reference, the full-scale input range will vary accordingly. The full-scale input range depends on the voltage at REF and the sampling mode selected (Tables 3 and 4). Input Acquisition and Settling Clocking in a Control Byte starts input acquisition. In bipolar mode the main capacitor array starts acquiring the input as soon as a start bit is recognized. If unipolar mode is selected by the second DIN bit, the part will immediately switch to unipolar sampling mode and acquire a sample. Acquisition can be extended by eight clock cycles by setting M1 = 1, M0 = 1 (long acquisition mode). The sampling instant in short acquisition completes on the falling edge of the sixth clock cycle after the start bit (Figure 2). Acquisition is 5.5 clock cycles in short acquisition mode and 13.5 clock cycles in long acquisition mode. Short acquisition mode is 24 clock cycles per conversion. Using the external clock to run the conversion process limits unipolar conversion speed to 125ksps instead of 200ksps in bipolar mode. The input resistance in unipolar mode is larger than that of bipolar mode (Figure1). The RC time constant in unipolar mode is larger than that of bipolar mode, reducing the maximum conversion rate in 24 external clock mode. Long acquisition mode with external clock allows both unipolar and bipolar sampling of 150ksps (4.8MHz/32 clock cycles) by adding eight extra clock cycles to the conversion. ______________________________________________________________________________________ 13 MAX1132/MAX1133 the beginning of calibration and goes high to signal the end of calibration, approximately 80,000 clock cycles later. In external clock mode, SSTRB goes high at the beginning of calibration and goes low to signal the end of calibration. Calibration should be performed in the same clock mode as will be used for conversions. MAX1132/MAX1133 16-Bit ADC, 200ksps, 5V Single-Supply with Reference Table 3. Unipolar Full Scale and Zero Scale PART REFERENCE ZERO SCALE MAX1132 MAX1133 FULL SCALE Internal 0 +12V External 0 +12(VREF/4.096) Internal 0 +4.096V External 0 +VREF Table 4. Bipolar Full Scale, Zero Scale, and Negative Scale PART MAX1132 MAX1133 REFERENCE NEGATIVE FULL SCALE ZERO SCALE FULL SCALE Internal -12V 0 +12V External -12(VREF/4.096) 0 +12(VREF/4.096) Internal -4.096V 0 +4.096V External -VREF 0 +VREF Most applications require an input buffer amplifier. If the input signal is multiplexed, the input channel should be switched immediately after acquistion, rather than near the end of or after a conversion. This allows more time for the input buffer amplifier to respond to a large step-change in input signal. The input amplifier must have a high enough slew-rate to complete the required output voltage change before the beginning of the acquisition time. At the beginning of acquisition, the capacitive DAC is connected to the amplifier output, causing some output disturbance. Ensure that the sampled voltage has settled to within the required limits before the end of the acquisition time. If the frequency of interest is low, AIN can be bypassed with a large enough capacitor to charge the capacitive DAC with very little change in voltage. However, for AC use, AIN must be driven by a wideband buffer (at least 10MHz), which must be stable with the DACs capacitive load (in parallel with any AIN bypass capacitor used) and also settle quickly (Figures 8 or 9). Digital Noise Digital noise can couple to AIN and REF. The conversion clock (SCLK) and other digital signals that are active during input acquisition contribute noise to the conversion result. If the noise signal is synchronous to the sampling interval, an effective input offset is produced. Asynchronous signals produce random noise on the input, whose high-frequency components may be aliased into the frequency band of interest. Minimize noise by presenting a low impedance (at the frequencies contained in the noise signal) at the inputs. This 14 requires bypassing AIN to AGND, or buffering the input with an amplifier that has a small-signal bandwidth of several MHz, or preferably both. AIN has a bandwidth of about 4MHz. Offsets resulting from synchronous noise (such as the conversion clock) are canceled by the MAX1132/ MAX1133’s calibration scheme. The magnitude of the offset produced by a synchronous signal depends on the signal’s shape. Recalibration may be appropriate if the shape or relative timing of the clock or other digital signals change, as might occur if more than one clock signal or frequency is used. Distortion Avoid degrading dynamic performance by choosing an amplifier with distortion much less than the MAX1132/ MAX1133’s THD (-90dB) at frequencies of interest. If the chosen amplifier has insufficient common-mode rejection, which results in degraded THD performance, use the inverting configuration to eliminate errors from common-mode voltage. Low temperature-coefficient resistors reduce linearity errors caused by resistance changes due to self-heating. To reduce linearity errors due to finite amplifier gain, use an amplifier circuit with sufficient loop gain at the frequencies of interest. DC Accuracy If DC accuracy is important, choose a buffer with an offset much less than the MAX1132/MAX1133’s maximum offset (±6mV), or whose offset can be trimmed while maintaining good stability over the required temperature range. ______________________________________________________________________________________ 16-Bit ADC, 200ksps, 5V Single-Supply with Reference MAX1132/MAX1133 1kΩ +15V 100pF 0.1µF 2 7 6 IN 3 MAX427 20Ω ELANTEC EL2003 AIN 4 0.0033µF 0.1µF -15V Figure 8. AIN Buffer for AC/DC Use Mode 2 Long Acquisition Mode (32 SCLK) Configure long acquisition by setting M1 = 1 and M0 = 1. In long acquisition mode, the acquisition time is 13.5 clock cycles. The total period is 32 clock cycles per conversion. 510Ω +5V 0.1µF 2 7 22Ω 6 IN 3 AIN MAX410 4 0.1µF 0.1µF -5V Figure 9. ±5V Buffer for AC/DC Use Has ±3.5V Swing Operating Modes and Serial Interfaces The MAX1132/MAX1133 are fully compatible with MICROWIRE and SPI/QSPI devices. MICROWIRE and SPI/QSPI both transmit a byte and receive a byte at the same time. The simplest software interface requires only three 8-bit transfers to perform a conversion (one 8-bit transfer to configure the ADC, and two more 8-bit transfers to clock out the 16-bit conversion result). Short Acquisition Mode (24 SCLK) Configure short acquisition by setting M1 = 0 and M0 = 0. In short acquisition mode, the acquisition time is 5.5 clock cycles. The total period is 24 clock cycles per conversion. Calibration Mode A calibration is initiated through the serial interface by setting M1 = 0, M0 = 1. Calibration can be done in either internal or external clock mode, though it is desirable that the part be calibrated in the same mode in which it will be used to do conversions. The part will remain in calibration mode for approximately 80,000 clock cycles unless the calibration is aborted. Calibration is halted if RST or SHDN goes low, or if a valid start condition occurs. Software Shutdown A software power-down is initiated by setting M1 = 1, M0 = 0. After the conversion completes, the part shuts down. It reawakens upon receiving a new start bit. Conversions initiated with M1 = 1 and M0 = 0 (shutdown) use the acquisition mode selected for the previous conversion. Shutdown Mode The MAX1132/MAX1133 may be shut down by pulling SHDN low or by asserting software shutdown. In addition to lowering power dissipation to 13µW, considerable power can be saved by shutting down the converter for short periods (duration will be affected by REF startup time with internal reference) between conversions. There is no need to perform a calibration after the converter has been shut down, unless the time in ______________________________________________________________________________________ 15 MAX1132/MAX1133 16-Bit ADC, 200ksps, 5V Single-Supply with Reference shutdown is long enough that the supply voltage or ambient temperature may have changed. Supplies, Layout, Grounding and Bypassing For best system performance, use separate analog and digital ground planes. The two ground planes should be tied together at the MAX1132/MAX1133. Use pins 3 and 14 as the primary AGND and DGND, respectively. If the analog and digital supplies come from the same source, isolate the digital supply from the analog with a low value resistor (10Ω). The MAX1132/MAX1133 are not sensitive to the order of AVDD and DVDD sequencing. Either supply can be present in the absence of the other. Do not apply an external reference voltage until after both AVDD and DVDD are present. Be sure that digital return currents do not pass through the analog ground. All return current paths must be low-impedance. A 5mA current flowing through a PC board ground trace impedance of only 0.05Ω creates an error voltage of about 250µV, or about 2LSBs error with a ±4V full-scale system. The board layout should ensure as much as possible that digital and analog signal lines are kept separate. Do not run analog and digital lines parallel to one another. If you must cross one with the other, do so at right angles. The ADC is sensitive to high-frequency noise on the AVDD power supply. Bypass this supply to the analog ground plane with 0.1µF. If the main supply is not adequately bypassed, add an additional 1µF or 10µF lowESR capacitor in parallel with the primary bypass capacitor. Transfer Function Figures 10 and 11 show the MAX1132/MAX1133’s transfer functions. In unipolar mode, the output data is binary format and in bipolar mode it is two’s complement. Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. INL for the MAX1132/MAX1133 is measured using the endpoint method. DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. Aperture Delay Aperture delay (tAD) is the time between the falling edge of the sampling clock and the instant when an actual sample is taken. Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical, minimum analogto-digital noise is caused by quantization error only and results directly from the ADCs resolution (N bits): SNR = (6.02 ✕ N + 1.76)dB In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is calculated by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion Signal-to-Noise Plus Distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all other ADC output signals: SINAD (dB) = 20 ✕ log (SignalRMS/NoiseRMS) Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADCs error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number of bits as follows: ENOB = (SINAD - 1.76) / 6.02 Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: THD= 20 × log V22 + V32 + V42 + V52 / V1 Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step-width and the ideal value of 1LSB. A 16 ______________________________________________________________________________________ 16-Bit ADC, 200ksps, 5V Single-Supply with Reference MAX1132/MAX1133 OUTPUT CODE OUTPUT CODE FULL-SCALE TRANSITION 11 . . . 111 011 . . . 111 11 . . . 110 011 . . . 110 11 . . . 101 000 . . . 010 +FS = +4.096V -FS = -4.096V 1LSB = 8.192 65536 000 . . . 001 FS = +2.048V 000 . . . 000 FS 1LSB = 65536 111 . . . 111 111 . . . 110 111 . . . 101 00 . . . 011 00 . . . 010 100 . . . 001 00 . . . 001 100 . . . 000 00 . . . 000 0 1 2 3 INPUT VOLTAGE (LSBs) FS FS - 3/2LSB Figure 10. MAX1135 Unipolar Transfer Function, 2.048V = Full Scale where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. 0V -FS +FS - 1LSB INPUT VOLTAGE (LSBs) Figure 11. MAX1133 Bipolar Transfer Function, 4.096V = Full Scale Chip Information TRANSISTOR COUNT: 21,807 PROCESS: BiCMOS Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component), to the RMS value of the next largest distortion component. ______________________________________________________________________________________ 17 16-Bit ADC, 200ksps, 5V Single-Supply with Reference MAX1132/MAX1133 Functional Diagram AVDD AGND 9kΩ CREF REFADJ MAX1132 MAX1133 REFERENCE REF AIN INPUT SCALING NETWORK DAC COMPARATOR ANALOG TIMING CONTROL DVDD SSTRB DGND CS SERIAL INPUT PORT SCLK DIN MEMORY CLOCK GENERATOR SHDN +5V AIN REFADJ 18 TEMP. RANGE PIN-PACKAGE INL (LSB) MAX1132AEAP* -40°C to +85°C 20 SSOP ±1.5 MAX1132BEAP -40°C to +85°C 20 SSOP ±2.5 AVDD MAX1133ACAP* 0°C to +70°C 20 SSOP ±1.5 SHDN MAX1133BCAP 0°C to +70°C 20 SSOP ±2.5 MAX1133AEAP* -40°C to +85°C 20 SSOP ±1.5 MAX1133BEAP -40°C to +85°C 20 SSOP ±2.5 DVDD MAX1132 MAX1133 CREF REF Ordering Information (continued) PART 0.1µF 0.22µF P2 P1 CONTROL Typical Application Circuit 2.2µF CALIBRATION ENGINE DOUT P0 RST 1µF SERIAL OUTPUT PORT CS SCLK DIN DOUT RST SSTRB +5V 0.1µF MC68HCXX I/O SCLK MOSI MISO I/O *Future product DGND AGND ______________________________________________________________________________________ 16-Bit ADC, 200ksps, 5V Single-Supply with Reference SSOP.EPS Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 © 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. MAX1132/MAX1133 Package Information