SEMICONDUCTOR TECHNICAL DATA !# ! !# " $ ! L SUFFIX CERAMIC CASE 620 The MC14543B BCD–to–seven segment latch/decoder/driver is designed for use with liquid crystal readouts, and is constructed with complementary MOS (CMOS) enhancement mode devices. The circuit provides the functions of a 4–bit storage latch and an 8421 BCD–to–seven segment decoder and driver. The device has the capability to invert the logic levels of the output combination. The phase (Ph), blanking (BI), and latch disable (LD) inputs are used to reverse the truth table phase, blank the display, and store a BCD code, respectively. For liquid crystal (LC) readouts, a square wave is applied to the Ph input of the circuit and the electrically common backplane of the display. The outputs of the circuit are connected directly to the segments of the LC readout. For other types of readouts, such as light–emitting diode (LED), incandescent, gas discharge, and fluorescent readouts, connection diagrams are given on this data sheet. Applications include instrument (e.g., counter, DVM etc.) display driver, computer/calculator display driver, cockpit display driver, and various clock, watch, and timer uses. • • • • • • Latch Storage of Code Blanking Input Readout Blanking on All Illegal Input Combinations Direct LED (Common Anode or Cathode) Driving Capability Supply Voltage Range = 3.0 V to 18 V Capable of Driving Two Low–power TTL Loads, One Low–power Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range • Pin–for–Pin Replacement for CD4056A (with Pin 7 Tied to VSS). • Chip Complexity: 207 FETs or 52 Equivalent Gates Input Voltage, All Inputs ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD TA = – 55° to 125°C for all packages. Outputs LD BI Ph* D C Symbol Value Unit VDD – 0.5 to + 18 V Vin – 0.5 to VDD + 0.5 V X X X X 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 1 0 1 0 0 0 0 0 1 1 0 1 2 3 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 0 0 0 1 0 1 1 1 0 1 1 1 0 4 5 6 7 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 8 9 Blank Blank 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Blank Blank Blank Blank Iin ± 10 mA – 55 to + 125 _C 0 0 0 X X Power Dissipation, per Package† PD 500 mW † † † † Tstg – 65 to + 150 _C 10 mA Maximum Continuous Output Power* (Source or Sink) per Output POHmax POLmax 70 mW * POHmax = IOH (VOH – VDD) and POLmax = IOL (VOL – VSS) * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C Blank 0 TA IOHmax IOLmax Display 1 Operating Temperature Range Maximum Continuous Output Drive Current (Source or Sink) per Output B A a b c d e f g X DC Input Current per Pin Storage Temperature Range Plastic Ceramic SOIC TRUTH TABLE MAXIMUM RATINGS* (Voltages referenced to VSS) DC Supply Voltage D SUFFIX SOIC CASE 751B Inputs ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Rating P SUFFIX PLASTIC CASE 648 X X ** ** Inverse of Output Combinations Above Display as above X = Don’t care † = Above Combinations * = For liquid crystal readouts, apply a square wave to Ph For common cathode LED readouts, select Ph = 0 For common anode LED readouts, select Ph = 1 ** = Depends upon the BCD code previously applied when LD = 1 REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14543B 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — 5.0 5.0 10 10 15 – 3.0 – 0.64 — – 1.6 – 4.2 — — — — — – 2.4 – 0.51 — – 1.3 – 3.4 – 4.2 – 0.88 – 10.1 – 2.25 – 8.8 — — — — — – 1.7 – 0.36 — – 0.9 – 2.4 — — — — IOL 5.0 10 10 15 0.64 1.6 — 4.2 — — — — 0.51 1.3 — 3.4 0.88 2.25 10.1 8.8 — — — — 0.36 0.9 — 2.4 — — — mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) Vin = 0 or VDD, Iout = 0 µA IDD 5.0 10 15 — — — 5.0 10 20 — — — 0.005 0.010 0.015 5.0 10 20 — — — 150 300 600 µAdc Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT 5.0 10 15 Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 0.5 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 9.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink mAdc IT = (1.6 µA/kHz) f + IDD IT = (3.1 µA/kHz) f + IDD IT = (4.7 µA/kHz) f + IDD µAdc #Noise immunity specified for worst–case input combination. Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V = 2.0 V min @ VDD = 10 V = 2.5 V min @ VDD = 15 V †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency. ** The formulas given are for the typical characteristics only at 25_C. MC14543B 2 MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns tTLH Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 12.5 ns tTHL Turn–Off Delay Time tPLH = (1.7 ns/pF) CL + 520 ns tPLH = (0.66 ns/pF) CL + 217 ns tPLH = (0.5 ns/pF) CL + 160 ns tPLH Turn–On Delay Time tPHL = (1.7 ns/pF) CL + 420 ns tPHL = (0.66 ns/pF) CL + 172 ns tPHL = (0.5 ns/pF) CL + 130 ns tPHL VDD Min Typ Max 5.0 10 15 — — — 100 50 40 200 100 80 5.0 10 15 — — — 100 50 40 200 100 80 5.0 10 15 — — — 605 250 185 1210 500 370 5.0 10 15 — — — 505 205 155 1650 660 495 Unit ns ns ns ns Setup Time tsu 5.0 10 15 350 450 500 — — — ns Hold Time th 5.0 10 15 40 30 20 — — — ns tWH 5.0 10 15 250 100 80 — — — ns Latch Disable Pulse Width (Strobing Data) 125 50 40 * The formulas given are for the typical characteristics only. LOGIC DIAGRAM BI 7 VDD = PIN 16 VSS = PIN 8 9 a A 5 10 b 11 c B 3 12 d 13 e C 2 15 f 14 g D 4 LD 1 MOTOROLA CMOS LOGIC DATA PHASE 6 MC14543B 3 24 VDD = 15 Vdc VDD = 5.0 Vdc POHmax = 70 mWdc IOL , SINK CURRENT (mAdc) IOH, SOURCE CURRENT (mAdc) 0 – 6.0 VDD = 10 Vdc – 12 – 18 18 VDD = 10 Vdc 12 6.0 VDD = 15 Vdc – 24 – 16 POLmax = 70 mWdc VDD = 5.0 Vdc VSS = 0 Vdc VSS = 0 Vdc 0 – 12 – 8.0 – 4.0 (VOH – VDD), SOURCE DEVICE VOLTAGE (Vdc) 0 0 4.0 8.0 12 (VOL – VSS), SINK DEVICE VOLTAGE (Vdc) Figure 1. Typical Output Source Characteristics 16 Figure 2. Typical Output Sink Characteristics (a) Inputs D, Ph, and BI low, and Inputs A, B, and LD high. 20 ns 20 ns 90% 10% C 50% tPLH tPHL 90% 50% g VSS VOH 10% tTLH tTHL VDD VOL (b) Inputs D, Ph, and BI low, and Inputs A and B high. 20 ns 90% 10% LD Inputs BI and Ph low, and Inputs D and LD high. f in respect to a system clock. VSS tsu C VDD 50% th 50% 50% VSS All outputs connected to respective CL loads. 20 ns A, B, AND C 10% ANY OUTPUT 20 ns 90% 50% 1 2f 50% DUTY CYCLE VOH VDD VSS VOH VOL Figure 3. Dynamic Power Dissipation Signal Waveforms MC14543B 4 VDD g VOL (c) Data DCBA strobed into latches LD 50% tWH VDD VSS Figure 4. Dynamic Signal Waveforms MOTOROLA CMOS LOGIC DATA CONNECTIONS TO VARIOUS DISPLAY READOUTS LIQUID CRYSTAL (LC) READOUT MC14543B OUTPUT Ph INCANDESCENT READOUT APPROPRIATE VOLTAGE ONE OF SEVEN SEGMENTS COMMON BACKPLANE MC14543B OUTPUT Ph SQUARE WAVE (VSS TO VDD) VSS LIGHT EMITTING DIODE (LED) READOUT COMMON CATHODE LED COMMON ANODE LED MC14543B OUTPUT Ph GAS DISCHARGE READOUT APPROPRIATE VOLTAGE VDD MC14543B OUTPUT Ph MC14543B OUTPUT Ph VSS VDD NOTE: Bipolar transistors may be added for gain (for VDD v 10 V or Iout ≥ 10 mA). PIN ASSIGNMENT LD 1 16 VDD C 2 15 f B 3 14 g D 4 13 e A 5 12 d PH 6 11 c BI 7 10 b VSS 8 9 a VSS CONNECTIONS TO SEGMENTS a f g b e VDD = PIN 16 VSS = PIN 8 DISPLAY 0 MOTOROLA CMOS LOGIC DATA c d 1 2 3 4 5 6 7 8 9 MC14543B 5 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– K H G D J 16 PL 0.25 (0.010) MC14543B 6 SEATING PLANE M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA CMOS LOGIC DATA ◊ *MC14543B/D* MC14543B MC14543B/D 7