SEMICONDUCTOR TECHNICAL DATA L SUFFIX CERAMIC CASE 620 The MC14558B decodes 4–bit binary coded decimal data dependent on the state of auxiliary inputs, Enable and RBI, and provides an active–high seven–segment output for a display driver. An auxiliary input truth table is shown, in addition to the BCD to seven–segment truth table, to indicate the functions available with the two auxiliary inputs. Leading Zero blanking is easily obtained with an external flip–flop in time division multiplexed systems displaying most significant decade first. • • • • • • P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B Supply Voltage Range = 3.0 Vdc to 18 Vdc Segment Blanking for All Illegal Input Combinations Lamp Test Function Capability for Suppression of Non–Significant Zeros Lamp Intensity Function Capable of Driving Two Low–power TTL Loads. One Low–power Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ TA = – 55° to 125°C for all packages. MAXIMUM RATINGS* (Voltages referenced to VSS) Rating Symbol Value Unit VDD – 0.5 to + 18 V Input Voltage, All Inputs Vin – 0.5 to VDD + 0.5 V DC Input Voltage, per Pin Iin ± 10 mAdc Operating Temperature Range TA – 55 to + 125 _C Power Dissipation, per Package† PD 500 mW Tstg – 65 to + 150 DC Supply Voltage Storage Temperature Range Plastic Ceramic SOIC PIN ASSIGNMENT B 1 16 VDD C 2 15 f ENABLE 3 14 g RBO 4 13 a RBI 5 12 b D 6 11 c A 7 10 d VSS 8 9 e _C * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C a g f e b c d DISPLAY AUXILIARY INPUT TRUTH TABLE Enable Pin 3 RBI Pin 5 BCD Input Code RBO Pin 4 0 0 0 X 0 Lamp Test 0 1 X 1 Blank Segments 1 1 0 1 Display Zero 1 0 0 0 Blank Segments 1 X 1–9 1 1–9 Displayed 1 2 3 4 5 6 7 8 9 Function Performed X = Don’t Care RBI = Ripple Blanking Input RBO = Ripple Blanking Output REV 3 1/94 MOTOROLA Motorola, Inc. 1995 CMOS LOGIC DATA MC14558B 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — 5.0 5.0 10 15 – 3.0 – 0.64 – 1.6 – 4.2 — — — — – 2.4 – 0.51 – 1.3 – 3.4 – 4.2 – 0.88 – 2.25 – 8.8 — — — — – 1.7 – 0.36 – 0.9 – 2.4 — — — — IOL 5.0 10 15 0.64 1.6 4.2 — — — 0.51 1.3 3.4 0.88 2.25 8.8 — — — 0.36 0.9 2.4 — — — mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) Vin = 0 or VDD Iout = 0 µA IDD 5.0 10 15 — — — 5.0 10 20 — — — 0.005 0.010 0.015 5.0 10 20 — — — 150 300 600 µAdc Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) IT 5.0 10 15 Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink mAdc IT = (1.2 µA/kHz) f + IDD IT = (2.4 µA/kHz) f + IDD IT = (3.6 µA/kHz) f + IDD µAdc #Noise immunity specified for worst–case input combination. Noise Margin for both “1” and “0” level = 1.0 V min @ VDD = 5.0 V = 2.0 V min @ VDD = 10 V = 2.5 V min @ VDD = 15 V †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + 3.5 x 10–3 (CL – 50) VDDf where: IT is in µA (per package), CL in pF, VDD in V, and f in kHz is input frequency. ** The formulas given are for the typical characteristics only at 25_C. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). MC14558B 2 MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C; see Figure 1) Characteristic Symbol Output Rise Time tTLH = (3.0 ns/pF) CL + 30 ns tTLH = (1.5 ns/pF) CL + 15 ns tTLH = (1.1 ns/pF) CL + 10 ns tTLH Output Fall Time tTHL = (1.5 ns/pF) CL + 25 ns tTHL = (0.75 ns/pF) CL + 12.5 ns tTHL = (0.55 ns/pF) CL + 9.5 ns tTHL Propagation Delay Time tPLH = (1.7 ns/pF) CL + 495 ns tPLH = (0.66 ns/pF) CL + 187 ns tPLH = (0.5 ns/pF) CL + 120 ns tPLH Propagation Delay Time tPHL = (1.7 ns/pF) CL + 695 ns tPHL = (0.66 ns/pF) CL + 242 ns tPHL = (0.5 ns/pF) CL + 160 ns tPHL VDD Min Typ Max 5.0 10 15 — — — 100 50 40 200 100 80 5.0 10 15 — — — 100 50 40 200 100 80 5.0 10 15 — — — 580 220 145 1160 440 230 5.0 10 15 — — 780 275 185 1560 550 370 Unit ns ns ns ns * The formulae given are for the typical characteristics only. TRUTH TABLE Inputs Outputs* Enable Pin 3 RBI Pin 5 D Pin 6 C Pin 2 B Pin 1 A Pin 7 a Pin 13 b Pin 12 c Pin 11 d Pin 10 e Pin 9 f Pin 15 g Pin 14 RBO Pin 4 1 1 0 0 0 0 1 1 1 1 1 1 0 1 1 X 0 0 0 1 0 0 0 0 1 1 0 1 1 X 0 0 1 0 1 1 0 1 1 0 1 1 1 X 0 0 1 1 1 1 1 1 0 0 1 1 1 X 0 1 0 0 0 1 1 0 0 1 1 1 1 X 0 1 0 1 1 0 1 1 0 1 1 1 1 X 0 1 1 0 0 0 1 1 1 1 1 1 1 X 0 1 1 1 1 1 1 0 0 0 0 1 1 X 1 0 0 0 1 1 1 1 1 1 1 1 1 X 1 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X 1 1 1 1 1 1 1 0 0 1 X X X X 0 0 0 0 0 0 0 1 Display Blank Blank * All non–valid BCD input codes produce a blank display. X = Don’t Care 20 ns ANY INPUT 20 ns 10% tPLH 90% tPHL 50% ANY OUTPUT tTLH 50% 90% 10% tTHL Figure 1. Signal Waveforms MOTOROLA CMOS LOGIC DATA MC14558B 3 MC14558B 4 RBO 4 g D 6 14 f 15 e C 2 9 d B A 1 11 10 c b 12 7 RBI 5 ENABLE 3 13 a LOGIC DIAGRAM MOTOROLA CMOS LOGIC DATA TYPICAL APPLICATIONS N4 RBI VSS N3 RBO RBI En N2 RBO RBI En N1 RBO RBI En N–1 RBO RBI En N–2 RBO RBI En N–3 RBO RBI En RBO En VSS LAMP TEST Figure 2. Leading and Trailing Zero Suppression with Lamp Test N4 N3 N2 N1 N–1 N–2 N–3 VDD RBO RBI RBI En BLANKING RBO RBI En RBO RBI En RBO RBI En RBO RBI En RBO RBI En RBO En Figure 3. Leading and Trailing Zero Suppression with PWM Intensity Blanking and No Lamp Test N4 N3 RBO RBI RBI En N2 RBO En RBI N1 RBO En RBI N–1 RBO En RBI RBO En N–2 RBI RBO En N–3 RBI RBO En BLANKING LAMP TEST Figure 4. Zero Suppression with Lamp Test and Intensity Blanking MOTOROLA CMOS LOGIC DATA MC14558B 5 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– K H G D J 16 PL 0.25 (0.010) MC14558B 6 SEATING PLANE M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA CMOS LOGIC DATA ◊ *MC14558B/D* MC14558B MC14558B/D 7