MC54/74F174 HEX D FLIP-FLOP WITH MASTER RESET The MC54/74F174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The device has a Master Reset to simultaneously clear all flip-flops. The F174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. The state of each D input, one setup time before low-to-high clock transition, is transferred to the corresponding flig-flop’s Q output. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The F174 is useful for applications where only the true output is required and the Clock and Master Reset are common to all storage elements. • Six Edge-triggered D-type Inputs • Buffered Positive Edge-triggered Common Clock • Buffered, Asynchronous Common Reset HEX D FLIP-FLOP WITH MASTER RESET FAST SCHOTTKY TTL J SUFFIX CERAMIC CASE 620-09 16 1 CONNECTION DIAGRAM DIP (TOP VIEW) VCC Q5 D5 D4 Q4 D3 Q3 CP 16 15 14 13 12 11 10 9 N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 16 1 1 2 3 4 5 6 7 8 MR Q0 D0 D1 Q1 D2 Q2 GND ORDERING INFORMATION MC54FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC FUNCTION TABLE Inputs Outputs @ tn, MR = H @ tn + 1 Dn Qn H H L L LOGIC SYMBOL 14 tn = Bit time before clock pulse tn + 1 = Bit time after clock pulse H = HIGH Voltage Level L = LOW Voltage Level 13 D5 D4 Q5 Q4 11 6 D3 D2 Q3 Q2 4 D1 D0 Q1 Q0 CP MR 3 9 1 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 4-86 15 12 10 7 5 2 MC54/74F174 LOGIC DIAGRAM MR CP D5 D4 D Q D3 D CP CD Q D2 D CP CD Q D CP CD Q4 Q5 D1 Q D CP CD Q3 D0 Q D CP CD Q2 Q CP CD Q1 Q0 GUARANTEED OPERATING RANGES Symbol Parameter VCC Supply Voltage TA Operating Ambient Temperature Range Min Typ Max Unit 54, 74 4.5 5.0 5.5 V 54 –55 25 125 °C 74 0 25 70 IOH Output Current — High 54, 74 –1.0 mA IOL Output Current — Low 54, 74 20 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage Min Typ Max 2.0 Unit Test Conditions V Guaranteed Input HIGH Voltage 0.8 V Guaranteed Input LOW Voltage –1.2 V VCC = MIN, IIN = – 18 mA 54, 74 2.5 V IOL = – 1.0 mA VCC = 4.50 V 74 2.7 V IOL = – 1.0 mA VCC = 4.75 V VCC = MIN VOL Output LOW Voltage 0.5 V IOL = 20 mA IIH Input HIGH Current 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V –0.6 mA VCC = MAX, VIN = 0.5 V –150 mA VCC = MAX, VOUT = 0 V 45 mA VCC = MAX, Dn = MR = 4.5 V, CP = IIL Input LOW Current IOS Output Short Circuit Current (Note 2) ICC Power Supply Current – 60 30 NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable device type. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-87 MC54/74F174 AC CHARACTERISTICS Symbol Parameter 54/74F 54F 74F TA = +25°C TA = –55°C to +125°C TA = 0°C to +70°C VCC = +5.0 V VCC = 5.0 V ± 10% VCC = 5.0 V ± 10% CL = 50 pF CL = 50 pF CL = 50 pF Min Typ Max Min Max 80 Min Max fmax Maximum Clock Frequency 100 140 80 tPLH Propagation Delay 3.5 5.5 8.0 3.5 10.0 3.5 9.0 tPHL CP to Qn 4.5 7.0 10 4.5 12.0 4.5 11.0 tPHL Propagation Delay MR to Qn 5.0 10 14 5.0 16.0 5.0 15.0 Unit MHz ns ns AC OPERATING REQUIREMENTS Symbol Parameter Min 54/74F 54F 74F TA = +25°C TA = –55°C to +125°C TA = 0°C to +70°C VCC = +5.0 V VCC = 5.0 V ± 10% VCC = 5.0 V ± 10% Typ Max Min max Min ts(H) Setup Time, HIGH or LOW 4.0 4.0 4.0 ts (L) Dn to CP 4.0 4.0 4.0 th(H) Hold Time, HIGH or LOW 0 1.0 0 th(L) Dn to CP 0 1.0 0 tw(H) CP Pulse Width, HIGH 4.0 4.0 4.0 6.0 6.0 6.0 tw(L) or LOW Max Unit ns ns tw(L) MR Pulse Width LOW 5.0 5.0 5.0 ns trec Recovery Time MR to CP 5.0 5.0 5.0 ns FAST AND LS TTL DATA 4-88