MC74F112 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The MC74F112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD force both Q and Q HIGH. DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP FAST SCHOTTKY TTL CONNECTION DIAGRAM VCC CD1 CD2 CP2 16 15 14 13 K2 J2 SD2 Q2 12 11 10 9 J SUFFIX CERAMIC CASE 620-09 16 C K D Q CP Q J SD 1 S J D Q CP K Q CD 1 2 3 4 5 6 7 8 CP1 K1 J1 SD1 Q1 Q1 Q2 GND N SUFFIX PLASTIC CASE 648-08 16 1 D SUFFIX SOIC CASE 751B-03 FUNCTION TABLE (Each Half) Inputs Output @ tn @ tn + 1 16 1 J K Q L L Qn L H L H L H H H Qn ORDERING INFORMATION MC74FXXXJ MC74FXXXN MC74FXXXD Ceramic Plastic SOIC Asynchronous Inputs: LOW Input to SD sets Q to HIGH level LOGIC SYMBOL LOW Input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH 10 4 H = HIGH Voltage Level L = LOW Voltage Level tn = Bit time before clock pulse tn + 1 = Bit time after clock pulse SD 3 J 1 CP 2 K Q Q 5 6 J 13 CP 12 K 15 4-45 CD 14 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA SD 11 Q 9 Q 7 MC74F112 LOGIC DIAGRAM (one half shown) Q Q CD J SD K CP GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 74 4.5 5.0 5.5 V TA Operating Ambient Temperature Range 74 0 25 70 °C IOH Output Current — High 74 –1.0 mA IOL Output Current — Low 74 20 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current Min Typ 2.0 Unit Test Conditions V Guaranteed Input HIGH Voltage 0.8 V Guaranteed Input LOW Voltage –1.2 V IIN = –18 mA VCC = MIN 74 2.5 3.4 V IOH = –1.0 mA VCC = 4.50 V 74 2.7 3.4 V IOH = –1.0 mA VCC = 4.75 V 0.5 V IOL = 20 mA VCC = MIN 20 µA VCC = MAX, VIN = 2.7 V 100 µA VCC = MAX, VIN = 7.0 V –0.6 mA (CP Inputs) –2.4 mA (CD and SD Inputs) –3.0 mA –150 mA VCC = MAX, VOUT = 0 V 19 mA VCC = MAX, VCP = 0 V 0.35 Input LOW Current (J and K Inputs) IIL Max IOS Output Short Circuit Current (Note 2) ICC Power Supply Current –60 12 VCC = MAX, VIN = 0.5 V NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under guaranteed operating ranges. 2. Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 4-46 MC74F112 AC CHARACTERISTICS 74F 74F TA = +25°C TA = 0°C to +70°C VCC = +5.0 V VCC = 5.0 V ± 10% CL = 50 PF Symbol Parameter Min CL = 50 PF Max Min Max fmax Maximum Clock Frequency 110 tPLH Propagation Delay 2.0 6.5 2.0 7.5 tPHL CPn to Qn or Qn 2.0 6.5 2.0 7.5 tPLH Propagation Delay 2.0 6.5 2.0 7.5 tPHL CDn or SDn to Qn or Qn 2.0 6.5 2.0 7.5 Unit MHz ns ns AC OPERATING REQUIREMENTS Symbol Parameter 74F 74F TA = +25°C TA = 0°C to +70°C VCC = +5.0 V VCC = 5.0 V ± 10% Min Typ Max Min Max Unit ts (H) Setup Time, HIGH or LOW 4.0 4.0 ts (L) Jn or Kn to CPn 3.0 3.0 th (H) Hold Time, HIGH or LOW 0 0 th (L) Jn or Kn to CPn 0 0 tw (H) CPn Pulse Width, HIGH 4.5 4.5 4.5 4.5 CDn or SDn Pulse Width, LOW 4.5 4.5 ns Recovery Time CDn or SDn to CP 4.0 5.0 ns tw (L) tw (L) trec ns ns or LOW FAST AND LS TTL DATA 4-47