SN54/74LS113A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS113A offers individual J, K, set, and clock inputs. These
monolithic dual flip-flops are designed so that when the clock goes HIGH, the
inputs are enabled and data will be accepted. The logic level of the J and K
inputs may be allowed to change when the clock pulse is HIGH and the
bistable will perform according to the truth table as long as minimum setup
times are observed. Input data is transferred to the outputs on the
negative-going edge of the clock pulse.
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM (Each Flip-Flop)
J SUFFIX
CERAMIC
CASE 632-08
14
1
14
1
N SUFFIX
PLASTIC
CASE 646-06
D SUFFIX
SOIC
CASE 751A-02
14
1
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
MODE SELECT — TRUTH TABLE
INPUTS
OUTPUTS
OPERATING MODE
Set
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
SD
J
K
Q
Q
L
H
H
H
H
X
h
l
h
l
X
h
h
l
l
H
q
L
H
q
L
q
H
L
q
Ceramic
Plastic
SOIC
LOGIC SYMBOL
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
5-189
FAST AND LS TTL DATA
SN54/74LS113A
GUARANTEED OPERATING RANGES
Symbol
Parameter
Min
Typ
Max
Unit
VCC
Supply Voltage
54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
TA
Operating Ambient Temperature Range
54
74
– 55
0
25
25
125
70
°C
IOH
Output Current — High
54, 74
– 0.4
mA
IOL
Output Current — Low
54
74
4.0
8.0
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol
Parameter
Min
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VIK
Input Clamp Diode Voltage
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IIH
Input HIGH Current
Typ
Max
Unit
2.0
54
0.7
74
0.8
– 0.65
– 1.5
Test Conditions
V
Guaranteed Input HIGH Voltage for
All Inputs
V
Guaranteed Input LOW Voltage for
All Inputs
V
VCC = MIN, IIN = – 18 mA
54
2.5
3.5
V
74
2.7
3.5
V
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
54, 74
0.25
0.4
V
IOL = 4.0 mA
74
0.35
0.5
V
IOL = 8.0 mA
J, K
Set
Clock
20
60
80
µA
VCC = MAX, VIN = 2.7 V
J, K
Set
Clock
0.1
0.3
0.4
mA
VCC = MAX, VIN = 7.0 V
– 0.4
– 0.8
mA
VCC = MAX, VIN = 0.4 V
– 100
mA
VCC = MAX
6.0
mA
VCC = MAX
J, K
Set, Clock
IIL
Input LOW Current
IOS
Short Circuit Current (Note 1)
ICC
Power Supply Current
– 20
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
fMAX
tPLH
tPHL
Parameter
Maximum Clock Frequency
Min
Typ
30
45
Propagation Delay, Clock
Set to Output
Max
Unit
Test Conditions
MHz
15
20
ns
15
20
ns
Max
Unit
VCC = 5.0 V
CL = 15 pF
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min
Typ
tW
Clock Pulse Width High
20
ns
tW
Set Pulse Width
25
ns
ts
Setup Time
20
ns
th
Hold Time
0
ns
FAST AND LS TTL DATA
5-190
Test Conditions
VCC = 5.0 V
Case 751A-02 D Suffix
14-Pin Plastic
SO-14
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Case 632-08 J Suffix
14-Pin Ceramic Dual In-Line
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Case 646-06 N Suffix
14-Pin Plastic
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FAST AND LS TTL DATA
5-191
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