SN54/74LS174 HEX D FLIP-FLOP The LSTTL / MSI SN54 / 74LS174 is a high speed Hex D Flip-Flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW to HIGH clock transition. The device has a Master Reset to simultaneously clear all flip-flops. The LS174 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all Motorola TTL families. • • • • HEX D FLIP-FLOP LOW POWER SCHOTTKY Edge-Triggered D-Type Inputs Buffered-Positive Edge-Triggered Clock Asynchronous Common Reset Input Clamp Diodes Limit High Speed Termination Effects J SUFFIX CERAMIC CASE 620-09 CONNECTION DIAGRAM DIP (TOP VIEW) Q5 15 VCC 16 D5 14 D4 13 Q4 12 D3 11 Q3 10 CP 16 9 1 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. N SUFFIX PLASTIC CASE 648-08 16 1 MR 2 Q0 3 D0 4 D1 5 Q1 6 D2 8 GND 7 Q2 1 PIN NAMES D SUFFIX SOIC CASE 751B-03 LOADING (Note a) 16 HIGH D0 – D5 CP MR Q0 – Q5 Data Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Outputs (Note b) LOW 1 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. ORDERING INFORMATION SN54LSXXXJ SN74LSXXXN SN74LSXXXD NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) b. Temperature Ranges. Ceramic Plastic SOIC LOGIC SYMBOL LOGIC DIAGRAM 3 4 6 11 13 14 MR CP D5 1 9 D4 14 D3 13 D2 D1 6 11 D0 4 3 9 1 D Q D Q D Q D Q D Q D Q CP CD CP CD CP CD CP CD CP CD CP CD D0 D1 D2 D3 D4 D5 CP MR Q0 Q1 Q2 Q3 Q4 Q5 2 5 7 10 12 15 15 VCC = PIN 16 GND = PIN 8 Q5 12 Q4 10 Q3 7 5 2 Q2 Q1 Q0 = PIN NUMBERS FAST AND LS TTL DATA 5-1 VCC = PIN 16 GND = PIN 8 SN54/74LS174 FUNCTIONAL DESCRIPTION A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The LS174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. The LS174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to the corresponding flipflop’s output following the LOW to HIGH Clock (CP) transition. TRUTH TABLE Inputs (t = n, MR = H) Outputs (t = n+1) Note 1 D Q H L H L Note 1: t = n + 1 indicates conditions after next clock. GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 74 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient Temperature Range 54 74 – 55 0 25 25 125 70 °C IOH Output Current — High 54, 74 – 0.4 mA IOL Output Current — Low 54 74 4.0 8.0 mA DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current Typ Max Unit 2.0 54 V V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA 0.7 74 0.8 – 0.65 – 1.5 Test Conditions Guaranteed Input HIGH Voltage for All Inputs 54 2.5 3.5 V 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 54, 74 0.25 0.4 V IOL = 4.0 mA 74 0.35 0.5 V IOL = 8.0 mA 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V – 100 mA VCC = MAX 26 mA VCC = MAX – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. FAST AND LS TTL DATA 5-2 SN54/74LS174 AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Typ 30 40 Unit Max fMAX Maximum Input Clock Frequency tPHL Propagation Delay, MR to Output 23 35 ns tPLH tPHL Propagation Delay, Clock to Output 20 21 30 30 ns Max Unit Test Conditions MHz VCC = 5.0 V CL = 15 pF AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ tW Clock or MR Pulse Width 20 ns ts Data Setup Time 20 ns th Data Hold Time 5.0 ns trec Recovery Time 25 ns Test Conditions VCC = 5.0 V AC WAVEFORMS 1/fmax tw 1.3 V CP 1.3 V ts(H) D * 1.3 V Q t th(H)s(L) 1.3 V tPLH 1.3 V MR th(L) 1.3 V 1.3 V tW 1.3 V trec 1.3 V tPHL 1.3 V CP Q tPHL 1.3 V 1.3 V *The shaded areas indicate when the input is permitted to *change for predictable output performance. Figure 1. Clock to Output Delays, Clock Pulse Width, Frequency, Setup and Hold Times Data to Clock Figure 2. Master Reset to Output Delay, Master Reset Pulse Width, and Master Reset Recovery Time DEFINITIONS OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. nition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (trec) — is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recog- FAST AND LS TTL DATA 5-3