19-3943; Rev 3; 4/09 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take advantage of video timing to reduce the serial-data rate. The MAX9248/MAX9250 pair with the MAX9247 serializer to form a complete digital video transmission system. For operating frequencies less than 35MHz, the MAX9248/ MAX9250 can also pair with the MAX9217 serializer. The MAX9248 features spread-spectrum capability, allowing output data and clock to spread over a specified frequency range to reduce EMI. The data and clock outputs are programmable for a spectrum spread of ±4% or ±2%. The MAX9250 features output enable input control to allow data busing. Proprietary data decoding reduces EMI and provides DC balance. The DC balance allows AC-coupling, providing isolation between the transmitting and receiving ends of the interface. The MAX9248/MAX9250 feature a selectable rising or falling output latch edge. ESD tolerance is specified for ISO 10605 with ±10kV Contact Discharge and ±30kV Air-Gap Discharge. The MAX9248/MAX9250 operate from a +3.3V ±10% core supply and feature a separate output supply for interfacing to 1.8V to 3.3V logic-level inputs. These devices are available in a 48-lead LQFP package and are specified from -40°C to +85°C or -40°C to +105°C. Features o Programmable ±4% or ±2% Spread-Spectrum Output for Reduced EMI (MAX9248) o Proprietary Data Decoding for DC Balance and Reduced EMI o Control Data Deserialized During Video Blanking o Five Control Data Inputs are Single-Bit-Error Tolerant o Output Transition Time is Scaled to Operating Frequency for Reduced EMI o Staggered Output Switching Reduces EMI o Output Enable Allows Busing of Outputs (MAX9250) o Clock Pulse Stretch on Lock o Wide ±2% Reference Clock Tolerance o Synchronizes to MAX9247 Serializer Without External Control o ISO 10605 and IEC 61000-4-2 Level 4 ESD Protection o Separate Output Supply Allows Interface to 1.8V to 3.3V Logic o +3.3V Core Power Supply o Space-Saving LQFP Package o -40°C to +85°C and -40°C to +105°C Operating Temperature Ranges Applications Navigation System Displays Ordering Information TEMP RANGE PIN-PACKAGE In-Vehicle Entertainment Systems MAX9248ECM+ PART -40°C to +85°C 48 LQFP Video Cameras MAX9248ECM/V+ -40°C to +85°C 48 LQFP LCD Displays MAX9248GCM+ -40°C to +105°C 48 LQFP MAX9248GCM/V+ -40°C to +105°C 48 LQFP -40°C to +85°C 48 LQFP MAX9250ECM+ MAX9250ECM/V+ -40°C to +85°C 48 LQFP MAX9250GCM+ -40°C to +105°C 48 LQFP MAX9250GCM/V+ -40°C to +105°C 48 LQFP +Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9248/MAX9250 General Description MAX9248/MAX9250 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers ABSOLUTE MAXIMUM RATINGS VCC_ to _GND........................................................-0.5V to +4.0V Any Ground to Any Ground...................................-0.5V to +0.5V IN+, IN- to LVDSGND............................................-0.5V to +4.0V IN+, IN- Short Circuit to LVDSGND or VCCLVDS ........Continuous (R/F, OUTEN, RNG_, REFCLK, SS PWRDWN) to GND................................. -0.5V to (VCC + 0.5V) (RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT, LOCK) to VCCOGND .............................-0.5V to (VCCO + 0.5V) Continuous Power Dissipation (TA = +70°C) 48-Lead LQFP (derate 21.7mW/°C above +70°C).....1739mW ESD Protection Machine Model (RD = 0Ω, CS = 200pF) All Pins to GND............................................................±200V Human Body Model (RD = 1.5kΩ, CS = 100pF) All Pins to GND..............................................................±2kV ISO 10605 (RD = 2kΩ, CS = 330pF) Contact Discharge (IN+, IN-) to GND ............................±10kV Air-Gap Discharge (IN+, IN-) to GND ............................±30kV IEC 61000-4-2 (RD = 330Ω, CS = 150pF) Contact Discharge (IN+, IN-) to GND ............................±10kV Air-Gap Discharge (IN+, IN-) to GND ............................±15kV Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC_ = +3.0V to +3.6V, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.05V to 1.2V, input common-mode voltage VCM = ⏐VID / 2⏐ to VCC - ⏐VID / 2⏐, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, ⏐VID⏐ = 0.2V, VCM = 1.2V, TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED INPUTS (R/F, OUTEN, RNG0, RNG1, REFCLK, PWRDWN, SS) High-Level Input Voltage VIH 2.0 Low-Level Input Voltage VIL -0.3 +0.8 -100 +20 -20 +20 Input Current IIN VIN = -0.3V to 0 (MAX9248/ MAX9250ECM), PWRDWN = V = -0.15V to 0 (MAX9248/ IN high or low MAX9250GCM), VIN = 0 to (VCC + 0.3V) Input Clamp Voltage VCL ICL = -18mA VCC + 0.3 -1.5 V V µA V SINGLE-ENDED OUTPUTS (RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT, LOCK) High-Level Output Voltage Low-Level Output Voltage VOH VOL High-Impedance Output Current IOZ Output Short-Circuit Current IOS 2 IOH = -100µA VCCO - 0.1 IOH = -2mA, RNG1 = high VCCO - 0.35 IOH = -2mA, RNG1 = low VCCO - 0.4 V IOL = 100µA 0.1 IOL = 2mA, RNG1 = high 0.3 IOL = 2mA, RNG1 = low 0.35 PWRDWN = low or OUTEN = low, VO = -0.3V to (VCCO + 0.3V) -10 RNG1 = high, VO = 0 -10 -50 RNG1 = low, VO = 0 -7 -40 _______________________________________________________________________________________ +10 V µA mA 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers (VCC_ = +3.0V to +3.6V, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.05V to 1.2V, input common-mode voltage VCM = ⏐VID / 2⏐ to VCC - ⏐VID / 2⏐, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, ⏐VID⏐ = 0.2V, VCM = 1.2V, TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LVDS INPUT (IN+, IN-) Differential Input High Threshold VTH (Note 3) Differential Input Low Threshold VTL (Note 3) -50 PWRDWN = high or low (Note 3) -40 PWRDWN = MAX9248/MAX9250ECM high or low MAX9248/MAX9250GCM 42 60 78 42 60 88 42 60 78 42 60 88 Input Current IIN+, IIN- Input Bias Resistor (Note 3) Power-Off Input Current RIB IINO+, IINO- 50 VCC_ = MAX9248/MAX9250ECM 0 or open, PWRDWN = 0 or open, MAX9248/MAX9250GCM Figure 1 VCC_ = 0 or open, PWRDWN = 0 or open (Note 3) -60 mV mV +40 +60 µA kΩ µA POWER SUPPLY MAX9250 CL = 8pF, worst-case pattern, Figure 2 Worst-Case Supply Current MAX9248 CL = 8pF, worst-case pattern, Figure 2 RNG1 = low RNG0 = low 2.5MHz 19 5MHz 33 RNG1 = low RNG0 = high 5MHz 28 10MHz 49 10MHz 33 20MHz 59 RNG1 = high RNG0 = low RNG1 = high RNG0 = high 20MHz 45 42MHz 89 RNG1 = low RNG0 = low 2.5MHz 31 5MHz 48 5MHz 40 10MHz 70 RNG1 = low RNG0 = high RNG1 = high RNG0 = low RNG1 = high RNG0 = high Power-Down Supply Current ICCZ (Note 4) 10MHz 49 20MHz 87 20MHz 68 35MHz 100 42MHz 120 50 mA µA _______________________________________________________________________________________ 3 MAX9248/MAX9250 DC ELECTRICAL CHARACTERISTICS (continued) MAX9248/MAX9250 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers AC ELECTRICAL CHARACTERISTICS (VCC_ = +3.0V to +3.6V, CL = 8pF, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.1V to 1.2V, input common-mode voltage VCM = ⏐VID / 2⏐ to VCC - ⏐VID / 2⏐, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, ⏐VID⏐ = 0.2V, VCM = 1.2V, TA = +25°C.) (Notes 3, 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFCLK TIMING REQUIREMENTS Period Frequency Frequency Variation Duty Cycle Transition Time tT fCLK ΔfCLK MAX9248/MAX9250ECM 23.8 400.0 MAX9248/MAX9250GCM 28.6 400.0 MAX9248/MAX9250ECM 2.5 42.0 MAX9248/MAX9250GCM 2.5 35.0 REFCLK to serializer PCLK_IN -2.0 DC tTRAN 40 50 20% to 80% ns MHz +2.0 % 60 % 6 ns SWITCHING CHARACTERISTICS RNG1 = high Output Rise Time tR Figure 3 RNG1 = low RNG1 = high Output Fall Time tR Figure 3 RNG1 = low MAX9248/ MAX9250ECM 2.2 4.6 MAX9248/ MAX9250GCM 2.2 4.9 MAX9248/ MAX9250ECM 2.8 5.2 MAX9248/ MAX9250GCM 2.8 6.1 MAX9248/ MAX9250ECM 1.9 4.0 MAX9248/ MAX9250ECM 2.3 4.3 MAX9248/ MAX9250GCM 2.3 5.2 ns ns PCLK_OUT High Time tHIGH Figure 4 0.4 x tT 0.45 x tT 0.6 x tT ns PCLK_OUT Low Time tLOW Figure 4 0.4 x tT 0.45 x tT 0.6 x tT ns Data Valid Before PCLK_OUT tDVB Figure 5 0.35 x tT 0.4 x tT ns Data Valid After PCLK_OUT tDVA Figure 5 0.35 x tT 0.4 x tT ns PLL Lock to REFCLK tPLLREF MAX9248, Figure 8 33,600 x tT MAX9250, Figure 7 16,928 x tT SS = high, Figure 11 Spread-Spectrum Output Frequency (MAX9248) fPCLK_OUT SS = low, Figure 11 4 Maximum output frequency fREFCLK fREFCLK + 3.6% + 4.0% fREFCLK + 4.4% Minimum output frequency fREFCLK fREFCLK - 4.4% - 4.0% fREFCLK - 3.6% Maximum output frequency fREFCLK fREFCLK + 1.8% + 2.0% fREFCLK + 2.2% Minimum output frequency fREFCLK fREFCLK - 2.2% - 2.0% fREFCLK - 1.8% _______________________________________________________________________________________ ns MHz 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers (VCC_ = +3.0V to +3.6V, CL = 8pF, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.1V to 1.2V, input common-mode voltage VCM = ⏐VID / 2⏐ to VCC - ⏐VID / 2⏐, TA = -40°C to +105°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, ⏐VID⏐ = 0.2V, VCM = 1.2V, TA = +25°C.) (Notes 3, 5) PARAMETER SYMBOL CONDITIONS Spread-Spectrum Modulation Frequency fSSM Figure 11 Power-Down Delay tPDD Figures 7, 8 SS Change Delay MIN TYP MAX fREFCLK / 1024 UNITS kHz 100 ns 32,800 x tT ns tΔSSPLL MAX9248, Figure 17 Output Enable Time tOE MAX9250, Figure 8 10 30 ns Output Disable Time tOZ MAX9250, Figure 9 10 30 ns Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH and VTL. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25°C. Note 3: Parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma. Note 4: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ VCC - 0.3V. PWRDWN is ≤ 0.3V, REFCLK is static. Note 5: CL includes probe and test jig capacitance. _______________________________________________________________________________________ 5 MAX9248/MAX9250 AC ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VCC_ = +3.3V, CL = 8pF, TA = +25°C, unless otherwise noted.) 40 30 20 MAX9250 4 3 tF 2 9 1 10 15 20 25 30 40 35 45 1.8 FREQUENCY (MHz) OUTPUT POWER SPECTRUM vs. FREQUENCY (REFCLK = 42MHz, NO SPREAD, 4%, AND 2% SPREAD) -10 RESOLUTION BW = 30kHz VIDEO BW = 100kHz NO SPREAD 2% SPREAD BIT-ERROR RATE -30 -40 -50 -70 39 40 41 42 43 FREQUENCY (MHz) 44 45 6 5 4 tF 3 2 RNG1 = LOW 2.4 2.7 3.0 1.8 3.3 2.1 2.4 2.7 3.0 OUTPUT SUPPLY VOLTAGE (V) OUTPUT SUPPLY VOLTAGE (V) BIT-ERROR RATE vs. CABLE LENGTH CABLE LENGTH vs. FREQUENCY BIT-ERROR RATE < 10-9 CAT5 CABLE 1.00E-13 4% SPREAD -20 -60 6 1.00E-14 MAX9248/50 toc04 0 2.1 1.00E-12 1.00E-11 REFCLK = 42MHz 840Mbps DATA RATE FOR CABLE LENGTH < 10m BER < 10-12 1.00E-10 0 2 4 6 3.3 45 MAX9248/50 toc05 10 40 35 FREQUENCY (MHz) 5 7 0 0 0 tR 8 1 RNG1 = HIGH 0 MAX9248/50 toc03 tR 10 MAX9248/50 toc06 MAX9248 50 5 MAX9248/50 toc02 OUTPUT TRANSITION TIME (ns) 60 SUPPLY CURRENT (mA) 6 MAX9248/50 toc01 70 OUTPUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (VCCO) OUTPUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (VCCO) OUTPUT TRANSITION TIME (ns) WORST-CASE PATTERN SUPPLY CURRENT vs. FREQUENCY POWER SPECTRUM (dBm) MAX9248/MAX9250 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers 30 25 20 15 10 5 8 CAT5 CABLE LENGTH (m) 10 12 0 2 4 6 8 10 12 14 16 18 20 CABLE LENGTH (m) _______________________________________________________________________________________ 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers PIN MAX9248 MAX9250 NAME FUNCTION Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of PCLK_OUT for latching data into the next chip. Set R/F = high for a rising latch edge. Set R/F = low for a falling latch edge. Internally pulled down to GND. 1 1 R/F 2 2 RNG1 LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input frequency. Internally pulled down to GND. 3 3 VCCLVDS LVDS Supply Voltage. Bypass to LVDSGND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 4 4 IN+ Noninverting LVDS Serial-Data Input 5 5 IN- Inverting LVDS Serial-Data Input 6 6 LVDSGND 7 7 PLLGND 8 8 VCCPLL 9 9 RNG0 LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input frequency. Internal pulldown to GND. 10 10 GND Digital Supply Ground 11 11 VCC Digital Supply Voltage. Supply for LVTTL/LVCMOS inputs and digital circuits. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible with the smallest value capacitor closest to the supply pin. 12 12 REFCLK LVTTL/LVCMOS Reference Clock Input. Apply a reference clock that is within ±2% of the serializer PCLK_IN frequency. Internally pulled down to GND. 13 13 PWRDWN 14 — SS 15–23 15–23 24 24 DE_OUT LVTTL/LVCMOS Data-Enable Output. High indicates RGB_OUT[17:0] are active. Low indicates CNTL_OUT[8:0] are active. 25, 37 25, 37 VCCOGND Output Supply Ground 26, 38 26, 38 VCCO LVDS Supply Ground PLL Supply Ground PLL Supply Voltage. Bypass to PLLGND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible with the smallest value capacitor closest to the supply pin. LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. LVTTL/LVCMOS Spread-Spectrum Input. SS selects the frequency spread of PCLK_OUT and output data relative to PCLK_IN. Drive SS high for 4% spread and pull low for 2% spread. LVTTL/LVCMOS Control Data Outputs. CNTL_OUT[8:0] are latched into the next chip on the CNTL_OUT0– rising or falling edge of PCLK_OUT as selected by R/F when DE_OUT is low, and are held CNTL_OUT8 at the last state when DE_OUT is high. Output Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible with the smallest value capacitor closest to the supply pin. _______________________________________________________________________________________ 7 MAX9248/MAX9250 Pin Description Pin Description (continued) PIN NAME MAX9248 MAX9250 FUNCTION 27 27 LOCK 28 28 PCLK_OUT 29–36, 39–48 29–36, 39–48 RGB_OUT0– RBG_OUT7, RGB_OUT8– RGB_OUT17 — 14 OUTEN LVTTL/LVCMOS Lock Indicator Output. Outputs are valid when LOCK is low. LVTTL/LVCMOS Parallel Clock Output. Latches data into the next chip on the edge selected by R/F. LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Outputs. RGB_OUT[17:0] are latched into the next chip on the edge of PCLK_OUT selected by R/F when DE_OUT is high, and are held at the last state when DE_OUT is low. LVTTL/LVCMOS Output Enable Input. High activates the single-ended outputs. Driving low places the single-ended outputs in high impedance except LOCK. Internally pulled down to GND. Functional Diagram 0 CNTL_OUT IN+ IN- DE_OUT SER-TO-PAR RGB_OUT DC BALANCE/ DECODE IN- 1 FIFO IN+ SER-TO-PAR R/F DC BALANCE/ DECODE MAX9248/MAX9250 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers 1 0 R/F OUTEN RGB_OUT CNTL_OUT DE_OUT PCLK_OUT PCLK_OUT REFCLK PLL REFCLK SSPLL SS PWRDWN TIMING AND CONTROL PLL LOCK REF_IN PWRDWN TIMING AND CONTROL LOCK MAX9248 RNG[0:1] 8 MAX9250 RNG[0:1] _______________________________________________________________________________________ 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers MAX9248/MAX9250 PCLK_OUT IN+ RIB ODD RGB_OUT CNTL_OUT LVDS RECEIVER 1.2V EVEN RGB_OUT CNTL_OUT RIB IN- RISING LATCH EDGE SHOWN (R/F = HIGH). Figure 1. LVDS Input Bias Figure 2. Worst-Case Output Pattern 0.9 x VCCO DE_OUT PCLK_OUT 2.0V tHIGH LOCK 0.8V PCLK_OUT 0.1 x VCCO RGB_OUT[17:0] tR CNTL_OUT[8:0] tF tLOW Figure 3. Output Rise and Fall Times Figure 4. High and Low Times 2.0V PCLK_OUT 0.8V PCLK_OUT SHOWN FOR R/F = HIGH (RISING LATCH EDGE) tDVB tDVA DE_OUT LOCK RGB_OUT[17:0] 2.0V 2.0V 0.8V 0.8V CNTL_OUT[8:0] Figure 5. Synchronous Output Timing 20 SERIAL BITS SERIAL-WORD N IN+, IN- PCLK_OUT SHOWN FOR R/F = HIGH SERIAL-WORD N + 1 tDELAY PCLK_OUT CNTL_OUT RGB_OUT PARALLEL-WORD N - 1 PARALLEL-WORD N Figure 6. Deserializer Delay _______________________________________________________________________________________ 9 MAX9248/MAX9250 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers 2.0V 0.8V PWRDWN TRANSITION WORD FOUND tPLLREF tPDD REFCLK RECOVERED CLOCK PCLK_OUT HIGH IMPEDANCE HIGH IMPEDANCE CLOCK STRETCH VALID DATA RGB_OUT CNTL_OUT DE_OUT HIGH IMPEDANCE HIGH IMPEDANCE LOCK HIGH IMPEDANCE HIGH IMPEDANCE NOTE: R/F = HIGH Figure 7. PLL Lock to REFCLK and Power-Down Delay for MAX9250 2.0V 0.8V PWRDWN tPLLREF TRANSITION WORD FOUND 288 CLOCK CYCLES tPDD REFCLK OUTPUT CLOCK SPREAD PCLK_OUT HIGH IMPEDANCE HIGH IMPEDANCE CLOCK STRETCH OUTPUT DATA SPREAD VALID DATA RGB_OUT CNTL_OUT DE_OUT HIGH IMPEDANCE HIGH IMPEDANCE LOCK HIGH IMPEDANCE HIGH IMPEDANCE NOTE: R/F = HIGH Figure 8. PLL Lock to REFCLK and Power-Down Delay for MAX9248 10 ______________________________________________________________________________________ 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers OUTEN 0.8V MAX9248/MAX9250 OUTEN 2.0V MAX9250 MAX9250 tOE tOZ DE_OUT DE_OUT RGB_OUT[17:0] RGB_OUT[17:0] HIGH IMPEDANCE ACTIVE CNTL_OUT[8:0] CNTL_OUT[8:0] Figure 9. Output Enable Time ACTIVE HIGH IMPEDANCE Figure 10. Output Disable Time FREQUENCY 1 / fSSM fRxCLKOUT (MAX) fRxCLKIN TIME fRxCLKOUT (MIN) Figure 11. Simplified Modulation Profile ______________________________________________________________________________________ 11 MAX9248/MAX9250 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers Detailed Description The MAX9248/MAX9250 DC-balanced deserializers operate at a 2.5MHz-to-42MHz parallel clock frequency, deserializing video data to the RGB_OUT[17:0] outputs when the data-enable output DE_OUT is high, or control data to the CNTL_OUT[8:0] outputs when DE_OUT is low. The outputs on the MAX9248 are programmable for ±2% or ±4% spread relative to the LVDS input clock frequency, while the MAX9250 has no spread, but has an output-enable input that allows output busing. The video phase words are decoded using two overhead bits, EN0 and EN1. Control phase words are decoded with one overhead bit, EN0. Encoding, performed by the MAX9247 serializer, reduces EMI and maintains DC balance across the serial cable. The serial-input word formats are shown in Tables 1 and 2. Control data inputs C0 to C4, each repeated over three serial bit times by the serializer, are decoded using majority voting. Two or three bits at the same state determine the state of the recovered bit, providing single bit-error tolerance for C0 to C4. The state of C5 to C8 is determined by the level of the bit itself (no voting is used). AC-Coupling Benefits AC-coupling increases the input voltage of the LVDS receiver to the voltage rating of the capacitor. Two capacitors are sufficient for isolation, but four capacitors—two at the serializer output and two at the deserializer input—provide protection if either end of the cable is shorted to a high voltage. AC-coupling blocks low-frequency ground shifts and common-mode noise. The MAX9247 serializer can also be DC-coupled to the MAX9248/MAX9250 deserializers. Figures 12 and 14 show the AC-coupled serializer and deserializer with two capacitors per link, and Figures 13 and 15 show the AC-coupled serializer and deserializer with four capacitors per link. Applications Information Selection of AC-Coupling Capacitors See Figure 16 for calculating the capacitor values for AC-coupling depending on the parallel clock frequency. The plot shows capacitor values for two- and fourcapacitor-per-link systems. For applications using less than 18MHz clock frequency, use 0.1µF capacitors. Termination and Input Bias The IN+ and IN- LVDS inputs are internally connected to +1.2V through 42kΩ (min) to provide biasing for ACcoupling (Figure 1). Assuming 100Ω interconnect, the LVDS input can be terminated with a 100Ω resistor. Match the termination to the differential impedance of the interconnect. Use a Thevenin termination, providing 1.2V bias, on an AC-coupled link in noisy environments. For interconnect with 100Ω differential impedance, pull each LVDS line up to VCC with 130Ω and down to ground with 82Ω at the deserializer input (Figures 12 and 15). This termination provides both differential and common-mode termination. The impedance of the Thevenin termination should be half the differential impedance of the interconnect and provide a bias voltage of 1.2V. Table 1. Serial Video Phase Word Format 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 EN0 EN1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 Bit 0 is the LSB and is deserialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols. Table 2. Serial Control Phase Word Format 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 EN0 C0 C0 C0 C1 C1 C1 C2 C2 C2 C3 C3 C3 C4 C4 C4 C5 C6 C7 C8 Bit 0 is the LSB and is deserialized first. C[8:0] are the mapped control inputs. 12 ______________________________________________________________________________________ 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers MAX9248/MAX9250 VCC 130Ω * OUT CMF DE_IN IN * 82Ω PLL 1 CNTL_OUT 0 DE_OUT PCLK_OUT PLL RNG1 TIMING AND CONTROL R/F OUTEN RGB_OUT 82Ω RNG0 PCLK_IN RNG0 RNG1 SER-TO-PAR 130Ω DC BALANCE/ DECODE 0 PAR-TO-SER CNTL_IN 1 INPUT LATCH RGB_IN DC BALANCE/ ENCODE PRE REF_IN PWRDWN TIMING AND CONTROL PWRDWN LOCK MAX9247 MAX9250 CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE *CAPACITORS CAN BE AT EITHER END. Figure 12. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Two Capacitors per Link VCC 130Ω IN OUT CMF DE_IN 82Ω 82Ω RNG0 PCLK_IN RNG0 RNG1 PLL TIMING AND CONTROL SER-TO-PAR 130Ω DC BALANCE/ DECODE 0 PAR-TO-SER CNTL_IN 1 INPUT LATCH RGB_IN DC BALANCE/ ENCODE PRE RNG1 CNTL_OUT DE_OUT PCLK_OUT REF_IN MAX9247 CERAMIC RF SURFACE-MOUNT CAPACITOR 0 PLL PWRDWN TIMING AND CONTROL PWRDWN 1 R/F OUTEN RGB_OUT LOCK MAX9250 100Ω DIFFERENTIAL STP CABLE Figure 13. AC-Coupled MAX9247 Serializer and MAX9250 Deserializer with Four Capacitors per Link ______________________________________________________________________________________ 13 VCC CMF IN- 82Ω 1 0 RGB_OUT FIFO * SER-TO-PAR OUT R/F IN+ DC BALANCE/ DECODE 0 130Ω 130Ω * PAR-TO-SER CNTL_IN 1 DC BALANCE/ ENCODE RGB_IN INPUT LATCH PRE CNTL_OUT DE_OUT 82Ω DE_IN PCLK_OUT REFCLK PCLK_IN RNG0 RNG1 PLL PLL SSPLL TIMING AND CONTROL SS PWRDWN TIMING AND CONTROL PWRDWN LOCK MAX9247 MAX9248 RNG[0:1] CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE *CAPACITORS CAN BE AT EITHER END. Figure 14. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Two Capacitors per Link VCC 130Ω R/F OUT CMF IN82Ω 1 0 RGB_OUT FIFO IN+ SER-TO-PAR 0 130Ω DC BALANCE/ DECODE CNTL_IN 1 PAR-TO-SER RGB_IN DC BALANCE/ ENCODE PRE INPUT LATCH MAX9248/MAX9250 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers DE_OUT 82Ω DE_IN PCLK_IN RNG0 RNG1 PCLK_OUT REFCLK PLL PLL SSPLL TIMING AND CONTROL LOCK MAX9247 MAX9248 RNG[0:1] CERAMIC RF SURFACE-MOUNT CAPACITOR SS PWRDWN TIMING AND CONTROL PWRDWN 100Ω DIFFERENTIAL STP CABLE Figure 15. AC-Coupled MAX9247 Serializer and MAX9248 Deserializer with Four Capacitors per Link 14 CNTL_OUT ______________________________________________________________________________________ 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The RNG[1:0] inputs select the operating frequency range of the MAX9248/MAX9250 and the transition time of the outputs. Select the frequency range that includes the MAX9247 serializer PCLK_IN frequency. Table 3 shows the selectable frequency ranges and the corresponding data rates and output transition times. 120 CAPACITOR VALUE (nF) Frequency Range Setting (RNG[1:0]) 140 100 FOUR CAPACITORS PER LINK 80 60 40 20 TWO CAPACITORS PER LINK 0 18 Table 3. Frequency Range Programming RNG1 RNG0 PARALLEL CLOCK (MHz) SERIALDATA RATE (Mbps) 0 0 2.5 to 5.0 50 to 100 0 1 5 to 10 100 to 200 1 0 10 to 20 200 to 400 1 1 20 to 42 400 to 840 OUTPUT TRANSITION TIME Slow Fast Power Down Driving PWRDWN low puts the outputs in high impedance and stops the PLL. With PWRDWN ≤ 0.3V and all LVTTL/LVCMOS inputs ≤ 0.3V or ≥ VCC - 0.3V, the supply current is reduced to less than 50µA. Driving PWRDWN high initiates lock to the local reference clock (REFCLK) and afterwards to the serial input. Lock and Loss-of-Lock (LOCK) When PWRDWN is driven high, the PLL begins locking to REFCLK, drives LOCK from high impedance to high and the other outputs from high impedance to low, except PCLK_OUT. PCLK_OUT outputs REFCLK while the PLL is locking to REFCLK. Lock to REFCLK takes a maximum of 16,928 REFCLK cycles for the MAX9250. The MAX9248 has an additional spread-spectrum PLL (SSPLL) that also begins locking to REFCLK. Locking both PLLs to REFCLK takes a maximum of 33,600 REFCLK cycles for the MAX9248. 21 24 27 30 33 36 39 42 PARALLEL CLOCK FREQUENCY (MHz) Figure 16. AC-Coupling Capacitor Values vs. Clock Frequency of 18MHz to 42MHz When the MAX9248/MAX9250 complete their lock to REFCLK, the serial input is monitored for a transition word. When a transition word is found, LOCK output is driven low, indicating valid output data and the parallel rate clock recovered from the serial input is output on PCLK_OUT. The MAX9248 SSPLL waits an additional 288 clock cycles after the transition word is found before LOCK is driven low and sequence takes effect. PCLK_OUT is stretched on the change from REFCLK to recovered clock (or vice versa) at the time when the transition word is found. If a transition word is not detected within 222 cycles of PCLK_OUT, LOCK is driven high, the other outputs except PCLK_OUT are driven low. REFCLK is output on PCLK_OUT and the deserializer continues monitoring the serial input for a transition word. See Figure 7 for the MAX9250 and Figure 8 for the MAX9248 regarding the synchronization timing diagram. The MAX9248 input-to-output delay can be as low as (4.5t T + 8.0)ns or as high as (36t T + 16)ns due to spread-spectrum variations (see Figure 6). The MAX9250 input-to-output delay can be as low as (3.575tT + 8)ns or as high as (3.725tT + 16)ns. ______________________________________________________________________________________ 15 MAX9248/MAX9250 Input Frequency Detection A frequency-detection circuit detects when the LVDS input is not switching. When not switching, all outputs except LOCK are low, LOCK is high, and PCLK_OUT follows REFCLK. This condition occurs, for example, if the serializer is not driving the interconnect or if the interconnect is open. MAX9248/MAX9250 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers Spread-Spectrum Selection The MAX9248 single-ended data and clock outputs are programmable for a variation of ±2% or ±4% around the LVDS input clock frequency. The modulation rate of the frequency variation is 32kHz for a 33MHz LVDS clock input and scales linearly with the clock frequency (see Table 4). The output spread is controlled through the SS input (see Table 5). Driving SS high spreads all data and clock outputs by ±4%, while pulling low spreads ±2%. Table 4. Modulation Rate fPCLK_IN fM(kHz) = fPCLK_IN / 1024 8 7.81 10 9.77 16 15.63 32 31.25 40 39.06 42 41.01 High Low Data and clock output spread ±2% relative to REFCLK SS ±4% OR ±2% SPREAD The outputs of two MAX9250s can be bused to form a 2:1 mux with the outputs controlled by the output enable. Wait 30ns between disabling one deserializer (driving OUTEN low) and enabling the second one (driving OUTEN high) to avoid contention of the bused outputs. OUTEN controls all outputs except LOCK. Rising or Falling Output Latch Edge (R/F) OUTPUT SPREAD Data and clock output spread ±4% relative to REFCLK Output Enable (OUTEN) and Busing Outputs The MAX9248/MAX9250 have a selectable rising or falling output latch edge through a logic setting on R/F. Driving R/F high selects the rising output latch edge, which latches the parallel output data into the next chip on the rising edge of PCLK_OUT. Driving R/F low selects the falling output latch edge, which latches the parallel output data into the next chip on the falling edge of PCLK_OUT. The MAX9248/MAX9250 outputlatch-edge polarity does not need to match the MAX9247 serializer input-latch-edge polarity. Select the latch-edge polarity required by the chip being driven by the MAX9248/MAX9250. Table 5. SS Function SS INPUT LEVEL Any spread change causes a delay time of 32,000 x tT before output data is valid. When the spread amount is changed from ±2% to ±4% or vice versa, the data outputs go low for one tΔSSPLL delay (see Figure 17). The data outputs stay low, but are not valid when the spread amount is changed. ±4% OR ±2% SPREAD tΔSSPLL (32,800 x tT) PCLK_OUT RGB_OUT[17:0] CNTL_OUT8:0] LOW LOCK Figure 17. Output Waveforms when Spread Amount is Changed 16 ______________________________________________________________________________________ 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers VIDEO DATA MAX9248/MAX9250 CONTROL DATA CONTROL DATA PCLK_OUT CNTL_OUT DE_OUT RGB_OUT PCLK_OUT TIMING SHOWN FOR R/F = HIGH (RISING OUTPUT LATCH EDGE) = OUTPUT DATA HELD Figure 18. Output Timing Staggered and Transition Time Adjusted Outputs RGB_OUT[17:0] are grouped into three groups of six, with each group switching about 1ns apart in the video phase to reduce EMI and ground bounce. CNTL_OUT[8:0] switch during the control phase. Output transition times are slower in the 2.5MHz to 5MHz and 5MHz to 10MHz ranges and faster in the 10MHz to 20MHz and 20MHz to 42MHz ranges. Data-Enable Output (DE_OUT) The MAX9248/MAX9250 deserialize video and control data at different times. Control data is deserialized during the video blanking time. DE_OUT high indicates that video data is being deserialized and output on RGB_OUT[17:0]. DE_OUT low indicates that control data is being deserialized and output on CNTL_OUT[8:0]. When outputs are not being updated, the last data received is latched on the outputs. Figure 18 shows the DE_OUT timing. Power-Supply Sequencing of MAX9247 and MAX9248/MAX9250 Video Link The MAX9247 and MAX9248/MAX9250 video link can be powered up in several ways. The best approach is to keep both MAX9247 and MAX9248 powered down while supplies are ramping up and PCLK_IN of the MAX9247 and REFCLK of the MAX9248/MAX9250 are stabilizing. After all of the power supplies of the MAX9247 and MAX9248/MAX9250 are stable, including PCLK_IN and REFCLK, do the following: • • • Power up the MAX9247 first Wait for at least tLOCK of MAX9247 (or 17100 x tT) to get activity on the link Power up the MAX9248 Power-Supply Circuits and Bypassing There are separate on-chip power domains for digital circuits and LVTTL/LVCMOS inputs (VCC supply and GND), outputs (V CCO supply and V CCOGND ), PLL (V CCPLL supply and PLLGND), and the LVDS input (VCCLVDS supply and LVDSGND). The grounds are isolated by diode connections. Bypass each VCC, VCCO, VCCPLL, and VCCLVDS pin with high-frequency, surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. The outputs are powered from V CCO , which accepts a 1.71V to 3.6V supply, allowing direct interface to inputs with 1.8V to 3.3V logic levels. Cables and Connectors Interconnect for LVDS typically has a differential impedance of 100Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. ______________________________________________________________________________________ 17 DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE DISCHARGE RESISTANCE CS 150pF Figure 20. IEC 61000-4-2 Contact Discharge ESD Test Circuit Figure 19. Human Body ESD Test Circuit RD 2kΩ CS 200pF Figure 22. Machine Model ESD Test Circuit Board Layout 18 RGB_OUT10 RGB_OUT9 RGB_OUT8 VCCO VCCOGND 41 37 43 RGB_OUT14 RGB_OUT13 RGB_OUT12 RGB_OUT11 44 45 46 RGB_OUT17 RGB_OUT16 RGB_OUT15 ESD Protection R/F RNG1 1 36 2 35 VCCLVDS IN+ INLVDSGND PLLGND VCCPLL RNG0 3 34 4 33 GND VCC REFCLK 32 5 6 31 MAX9248/MAX9250 7 30 RGB_OUT7 RGB_OUT6 RGB_OUT5 RGB_OUT4 RGB_OUT3 RGB_OUT2 RGB_OUT1 RGB_OUT0 PCLK_OUT LOCK VCCO 12 25 VCCOGND CNTL_OUT0 CNTL_OUT1 CNTL_OUT2 CNTL_OUT3 CNTL_OUT4 24 26 18 27 11 17 28 10 16 29 9 15 8 14 The MAX9248/MAX9250 ESD tolerance is rated for Human Body Model, Machine Model, IEC 61000-4-2 and ISO 10605. The ISO 10605 and IEC 61000-4-2 standards specify ESD tolerance for electronic systems. All LVDS inputs on the MAX9248/MAX9250 meet ISO 10605 ESD protection at ±30kV Air-Gap Discharge and ±10kV Contact Discharge and IEC 61000-4-2 ESD protection at ±15kV Air-Gap Discharge and ±10kV Contact Discharge. All other pins meet the Human Body Model ESD tolerance of ±2kV. The Human Body Model discharge components are CS = 100pF and RD = 1.5kΩ (Figure 19). The IEC 61000-4-2 discharge components are CS = 150pF and RD = 330Ω (see Figure 20). The ISO 10605 discharge components are CS = 330pF and RD = 2kΩ (Figure 21). The Machine Model discharge components are CS = 200pF and RD = 0Ω (Figure 22). 47 TOP VIEW 48 Pin Configuration 13 Separate the LVTTL/LVCMOS outputs and LVDS inputs to prevent crosstalk. A four-layer PCB with separate layers for power, ground, and signals is recommended. DEVICE UNDER TEST STORAGE CAPACITOR DE_OUT Figure 21. ISO 10605 Contact Discharge ESD Test Circuit HIGHVOLTAGE DC SOURCE 23 DEVICE UNDER TEST 42 STORAGE CAPACITOR DISCHARGE RESISTANCE 20 CS 330pF CHARGE-CURRENTLIMIT RESISTOR DISCHARGE RESISTANCE CNTL_OUT5 CNTL_OUT6 CNTL_OUT7 CNTL_OUT8 HIGHVOLTAGE DC SOURCE RD 0Ω 19 CHARGE-CURRENTLIMIT RESISTOR DEVICE UNDER TEST STORAGE CAPACITOR 38 STORAGE CAPACITOR CHARGE-CURRENTLIMIT RESISTOR 39 CS 100pF DISCHARGE RESISTANCE 22 HIGHVOLTAGE DC SOURCE R2 330Ω 40 CHARGE-CURRENTLIMIT RESISTOR RD 1.5kΩ 21 1MΩ PWRDWN SS (OUTEN) MAX9248/MAX9250 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers LQFP ______________________________________________________________________________________ 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers PROCESS: CMOS For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 48 LQFP C48+3 21-0054 ______________________________________________________________________________________ 19 MAX9248/MAX9250 Package Information Chip Information MAX9248/MAX9250 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers Revision History REVISION NUMBER REVISION DATE DESCRIPTION PAGES CHANGED 2 5/08 Replaced TQFP and TQFN packages with LQFP package, changed temperature limits for +105°C part, and added Machines Model ESD text and diagram 1–5, 7, 16–19 3 4/09 Added /V parts in the Ordering Information table and added new PowerSupply Sequencing of MAX9247 and MAX9248/MAX9250 Video Link section 1, 17 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.