19-3557; Rev 1; 4/05 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer The MAX9218 digital video serial-to-parallel converter deserializes a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take advantage of video timing to reduce the serial data rate. The MAX9218 pairs with the MAX9217 serializer to form a complete digital video transmission system. Proprietary data decoding reduces EMI and provides DC balance. The DC balance allows AC-coupling, providing isolation between the transmitting and receiving ends of the interface. The MAX9218 features a selectable rising or falling output latch edge. ESD tolerance is specified for ISO 10605 with ±10kV contact discharge and ±30kV air discharge. The MAX9218 operates from a +3.3V core supply and features a separate output supply for interfacing to 1.8V to 3.3V logic-level inputs. This device is available in 48lead Thin QFN and TQFP packages and is specified from -40°C to +85°C. Features ♦ Proprietary Data Decoding for DC Balance and Reduced EMI ♦ Control Data Deserialized During Video Blanking ♦ Five Control Data Inputs Are Single Bit-Error Tolerant ♦ Output Transition Time Is Scaled to Operating Frequency for Reduced EMI ♦ Staggered Output Switching Reduces EMI ♦ Output Enable Allows Busing of Outputs ♦ Clock Pulse Stretch on Lock ♦ Wide ±2% Reference Clock Tolerance ♦ Synchronizes to MAX9217 Serializer Without External Control ♦ ISO 10605 ESD Protection ♦ Separate Output Supply Allows Interface to 1.8V to 3.3V Logic ♦ +3.3V Core Power Supply ♦ Space-Saving Thin QFN and TQFP Packages ♦ -40°C to +85°C Operating Temperature Ordering Information Applications Navigation System Display PART PKG CODE TEMP RANGE PIN-PACKAGE In-Vehicle Entertainment System MAX9218ECM -40°C to +85°C 48 TQFP Video Camera MAX9218ETM LCD Displays C48-5 -40°C to +85°C 48 Thin QFN-EP* T4866-1 *EP = Exposed pad. R/F RNG1 1 36 2 35 VCCLVDS IN+ 3 34 4 33 INLVDS GND PLL GND VCCPLL RNG0 GND VCC 5 32 9 28 10 27 11 26 RGB_OUT3 RGB_OUT2 RGB_OUT1 RGB_OUT0 PCLK_OUT LOCK VCCO 12 25 VCCOGND 31 MAX9218 30 8 29 RGB_OUT8 VCCO VCCO GND 37 38 39 40 41 RGB_OUT12 RGB_OUT11 RGB_OUT10 RGB_OUT9 43 42 RGB_OUT14 RGB_OUT13 45 44 RGB_OUT16 RGB_OUT15 46 VCCLVDS IN+ INLVDS GND 3 34 4 33 5 32 PLL GND VCCPLL RNG0 GND VCC 7 31 RGB_OUT7 RGB_OUT6 RGB_OUT5 RGB_OUT4 RGB_OUT3 8 29 RGB_OUT2 RGB_OUT1 RGB_OUT0 9 28 PCLK_OUT 10 27 11 26 12 25 LOCK VCCO VCCO GND 6 MAX9218 30 24 23 22 CNTL_OUT7 CNTL_OUT8 DE_OUT 21 20 CNTL_OUT5 CNTL_OUT6 19 18 17 15 CNTL_OUT0 CNTL_OUT1 CNTL_OUT2 CNTL_OUT3 CNTL_OUT4 16 14 24 23 22 21 20 19 18 17 16 15 14 PWRDWN OUTEN CNTL_OUT0 CNTL_OUT1 CNTL_OUT2 CNTL_OUT3 CNTL_OUT4 CNTL_OUT5 CNTL_OUT6 CNTL_OUT7 CNTL_OUT8 DE_OUT 13 RGB_OUT17 35 REFCLK TQFP 47 36 2 13 7 1 OUTEN 6 R/F RNG1 PWRDWN REFCLK RGB_OUT7 RGB_OUT6 RGB_OUT5 RGB_OUT4 48 37 38 39 40 41 42 43 44 45 46 48 TOP VIEW 47 RGB_OUT17 RGB_OUT16 RGB_OUT15 RGB_OUT14 RGB_OUT13 RGB_OUT12 RGB_OUT11 RGB_OUT10 RGB_OUT9 RGB_OUT8 VCCO VCCOGND Pin Configurations THIN QFN-EP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX9218 General Description MAX9218 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer ABSOLUTE MAXIMUM RATINGS VCC_ to _GND........................................................-0.5V to +4.0V Any Ground to Any Ground...................................-0.5V to +0.5V IN+, IN- to LVDS GND...........................................-0.5V to +4.0V IN+, IN- Short Circuit to LVDS GND or VCCLVDS ......Continuous (R/F, OUTEN, RNG_, REFCLK, PWRDWN) to GND .................................-0.5V to (VCC + 0.5V) (RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT, LOCK) to VCCO GND ...........................-0.5V to (VCCO + 0.5V) Continuous Power Dissipation (TA = +70°C) 48-Lead Thin QFN (derate 37mW/°C above +70°C) .2963mW 48-Lead TQFP (derate 20.8mW/°C above +70°C) ....1667mW ESD Protection Human Body Model (RD = 1.5kΩ, CS = 100pF) All Pins to GND...........................................................±3.0kV ISO 10605 (RD = 2kΩ, CS = 330pF) Contact Discharge (IN+, IN-) to GND ............................±10kV Air Discharge (IN+, IN-) to GND ....................................±30kV Storage Temperature Range .............................-65°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC_ = +3.0V to +3.6V, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.05V to 1.2V, input common-mode voltage VCM = ⏐VID/2⏐ to VCC - ⏐VID/2⏐, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, ⏐VID⏐ = 0.2V, VCM = 1.2V, TA = +25°C.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SINGLE-ENDED INPUTS (R/F, OUTEN, RNG0, RNG1, REFCLK, PWRDWN) High-Level Input Voltage VIH Low-Level Input Voltage VIL Input Current Input Clamp Voltage IIN VCL 2.0 VIN = -0.3V to (VCC + 0.3V), PWRDWN = high or low VCC + 0.3 V -0.3 +0.8 V -70 +70 µA -1.5 V ICL = -18mA SINGLE-ENDED OUTPUTS (RGB_OUT[17:0], CNTL_OUT[8:0], DE_OUT, PCLK_OUT, LOCK) High-Level Output Voltage Low-Level Output Voltage High-Impedance Output Current 2 VOH VOL IOZ IOH = -100µA VCCO - 0.1 IOH = -2mA, RNG1, RNG0 = high VCCO - 0.35 IOH = -2mA, RNG1, RNG0 both not high simultaneously VCCO - 0.4 V IOL = 100µA 0.1 IOL = 2mA, RNG1, RNG0 = high 0.3 IOL = 2mA, RNG1, RNG0 both not high simultaneously 0.35 PWRDWN = low or OUTEN = low, VO = -0.3V to VCCO + 0.3V -10 _______________________________________________________________________________________ +10 V µA 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer (VCC_ = +3.0V to +3.6V, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.05V to 1.2V, input common-mode voltage VCM = ⏐VID/2⏐ to VCC - ⏐VID/2⏐, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, ⏐VID⏐ = 0.2V, VCM = 1.2V, TA = +25°C.) (Notes 1, 2) PARAMETER Output Short-Circuit Current SYMBOL IOS CONDITIONS MIN RNG1, RNG0 = high, VO = 0 -10 TYP MAX -50 RNG1, RNG0 both not high simultaneously, VO = 0 -7 -40 UNITS mA LVDS INPUT (IN+, IN-) Differential Input High Threshold Differential Input Low Threshold Input Current VTH VTL IIN+, IIN- Input Bias Resistor RIB Power-Off Input Current 50 IINO+, IINO- -50 PWRDWN = high or low -20 PWRDWN = high or low 35 VCC_ = 0 or open, PWRDWN = 0 or open, Figure 1 35 VCC_ = 0 or open, PWRDWN = 0 or open -40 mV mV +20 µA 50 65 kΩ 50 65 kΩ +40 µA POWER SUPPLY Worst-Case Supply Current Power-Down Supply Current ICCW ICCZ CL = 8pF, worst-case pattern, Figure 2 (Note 3) RNG1 = low, RNG0 = low 3MHz 20 7MHz 35 RNG1 = high, RNG0 = low 7MHz 25 15MHz 47 RNG1 = high, RNG0 = high 15MHz 37 35MHz 70 50 mA µA _______________________________________________________________________________________ 3 MAX9218 DC ELECTRICAL CHARACTERISTICS (continued) MAX9218 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer AC ELECTRICAL CHARACTERISTICS (VCC_ = +3.0V to 3.6V, CL = 8pF, PWRDWN = high, differential input voltage ⏐VID⏐ = 0.1V to 1.2V, input common-mode voltage VCM = ⏐VID/2⏐ to VCC - ⏐VID/2⏐, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC_ = +3.3V, ⏐VID⏐ = 0.2V, VCM = 1.2V, TA = +25°C.) (Notes 4, 5) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS REFCLK TIMING REQUIREMENTS Period Frequency Frequency Variation Duty Cycle Transition Time tT 28.57 333.00 ns fCLK 3 35 MHz +2.0 % ∆fCLK REFCLK to serializer PCLK_IN DC tTRAN -2.0 40 50 20% to 80% 60 % 6 ns SWITCHING CHARACTERISTICS Output Rise Time Output Fall Time tR Figure 3 RNG1, RNG0 = high 3.2 4.4 RNG1, RNG0 both not high simultaneously 3.8 5.5 RNG1, RNG0 = high 2.7 4.5 RNG1, RNG0 both not high simultaneously 3.6 5.3 ns ns tF Figure 3 PCLK_OUT High Time tHIGH Figure 4 0.4 x tT 0.45 x tT 0.6 x tT ns PCLK_OUT Low Time tLOW Figure 4 0.4 x tT 0.45 x tT 0.6 x tT ns Data Valid Before PCLK_OUT tDVB Figure 5 0.35 x tT 0.4 x tT ns Data Valid After PCLK_OUT tDVA Figure 5 0.35 x tT 0.4 x tT ns Input-to-Output Delay tDELAY Figure 6 2.575 x tT + 8.5 PLL Lock to REFCLK tPLLREF Power-Down Delay Output Enable Time Output Disable Time 2.725 x tT + 12.8 ns Figure 7 16385 x tT ns tPDD Figure 7 100 ns tOE Figure 8 30 ns tOZ Figure 9 30 ns Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH and VTL. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25°C. Note 3: All LVTTL/LVCMOS inputs, except PWRDWN at ≤ 0.3V or ≥ VCC - 0.3V. PWRDWN is ≤ 0.3V. Note 4: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma. Note 5: CL includes probe and test jig capacitance. 4 _______________________________________________________________________________________ 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer WORST-CASE PATTERN SUPPLY CURRENT vs. FREQUENCY OUTPUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (VCCO) 60 50 40 30 20 MAX9218 toc02 tR 5 4 tF 3 2 10 1 0 0 RNG1 = RNG0 = HIGH 3 7 11 15 19 23 27 31 35 1.8 2.1 2.4 2.7 3.0 FREQUENCY (MHz) OUTPUT SUPPLY VOLTAGE (V) OUTPUT TRANSITION TIME vs. OUTPUT SUPPLY VOLTAGE (VCCO) BIT-ERROR RATE vs. CABLE LENGTH 6 10 -14 MAX9218 toc03 7 tR CAT5e 3.3 10 -13 5 BIT-ERROR RATE OUTPUT TRANSITION TIME (ns) 6 MAX9218 toc04 SUPPLY CURRENT (mA) 70 7 OUTPUT TRANSITION TIME (ns) MAX9218 toc01 80 tF 4 3 2 10 -12 10 -11 35MHz CLOCK 700Mbps DATA RATE FOR <12m, BER < 10-12 1 RNG1 = RNG0 = BOTH NOT HIGH 10 -10 0 1.8 2.1 2.4 2.7 3.0 OUTPUT SUPPLY VOLTAGE (V) 3.3 0 4 8 12 16 20 CAT5e CABLE LENGTH (m) _______________________________________________________________________________________ 5 MAX9218 Typical Operating Characteristics (VCC_ = +3.3V, CL = 8pF, TA = +25°C, unless otherwise noted.) 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer MAX9218 Pin Description 6 PIN NAME FUNCTION 1 R/F Rising or Falling Latch Edge Select. LVTTL/LVCMOS input. Selects the edge of PCLK_OUT for latching data into the next chip. Set R/F = high for a rising latch edge. Set R/F = low for a falling latch edge. Internally pulled down to GND. 2 RNG1 LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input frequency. Internally pulled down to GND. 3 VCCLVDS LVDS Supply Voltage. Bypass to LVDS GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 4 IN+ Noninverting LVDS Serial Data Input 5 IN- Inverting LVDS Serial Data Input 6 LVDS GND 7 PLL GND 8 VCCPLL 9 RNG0 LVTTL/LVCMOS Range Select Input. Set to the range that includes the serializer parallel clock input frequency. Internal pulldown to GND. 10 GND Digital Supply Ground 11 VCC Digital Supply Voltage. Supply for LVTTL/LVCMOS inputs and digital circuits. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 12 REFCLK LVTTL/LVCMOS Reference Clock Input. Apply a reference clock that is within ±2% of the serializer PCLK_IN frequency. Internally pulled down to GND. 13 PWRDWN 14 OUTEN 15–23 CNTL_OUT [8:0] 24 DE_OUT 25, 37 VCCO GND 26, 38 VCCO Output Supply Voltage. Bypass to GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. 27 LOCK LVTTL/LVCMOS Lock Indicator Output. Outputs are valid when LOCK is low. 28 PCLK_OUT LVTTL/LVCMOS Parallel Clock Output. Latches data into the next chip on the edge selected by R/F. 29–36, 39–48 RGB_OUT [17:0] LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Outputs. RGB_OUT[17:0] are latched into the next chip on the edge of PCLK_OUT selected by R/F when DE_OUT is high, and are held at the last state when DE_OUT is low. EP GND LVDS Supply Ground PLL Supply Ground PLL Supply Voltage. Bypass to PLL GND with 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. LVTTL/LVCMOS Output Enable Input. High activates the single-ended outputs. Driving low places the single-ended outputs in high impedance. Internally pulled down to GND. LVTTL/LVCMOS Control Data Outputs. CNTL_OUT[8:0] are latched into the next chip on the rising or falling edge of PCLK_OUT as selected by R/F when DE_OUT is low, and are held at the last state when DE_OUT is high. LVTTL/LVCMOS Data Enable Output. High indicates RGB_OUT[17:0] are active. Low indicates CNTL_OUT[8:0] are active. Output Supply Ground Exposed Pad for Thin QFN Package Only. Connect to GND. _______________________________________________________________________________________ 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer R/F OUTEN RGB_OUT[17:0] 1 IN+ DC BALANCE/ DECODE IN- SER-TO-PAR CNTL_OUT[8:0] 0 DE_OUT PCLK_OUT RNG0 RNG1 PLL REFCLK PWRDWN TIMING AND CONTROL LOCK MAX9218 IN+ 0.9VCCO DE_OUT RIB 1.2V LVDS RECEIVER LOCK PCLK_OUT 0.1VCCO RGB_OUT[17:0] RIB CNTL_OUT[8:0] tR tF IN- Figure 1. LVDS Input Bias Figure 3. Output Rise and Fall Times PCLK_OUT PCLK_OUT 2.0V tHIGH ODD RGB_OUT CNTL_OUT 0.8V EVEN RGB_OUT CNTL_OUT tLOW RISING LATCH EDGE SHOWN (R/F = HIGH). Figure 2. Worst-Case Output Pattern Figure 4. High and Low Times _______________________________________________________________________________________ 7 MAX9218 Functional Diagram MAX9218 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer 2.0V PCLK_OUT 0.8V PCLK_OUT SHOWN FOR R/F = HIGH (RISING LATCH EDGE) tDVB tDVA DE_OUT LOCK RGB_OUT[17:0] 2.0V 2.0V 0.8V 0.8V CNTL_OUT[8:0] Figure 5. Synchronous Output Timing 20 SERIAL BITS SERIAL-WORD N IN+, IN- PCLK_OUT SHOWN FOR R/F = HIGH SERIAL-WORD N + 1 tDELAY PCLK_OUT CNTL_OUT RGB_OUT PARALLEL-WORD N - 1 PARALLEL-WORD N Figure 6. Deserializer Delay 8 _______________________________________________________________________________________ 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer MAX9218 2.0V 0.8V PWRDWN tPLLREF TRANSITION WORD FOUND tPDD REFCLK RECOVERED CLOCK PCLK_OUT HIGH IMPEDANCE HIGH IMPEDANCE CLOCK STRETCH VALID DATA RGB_OUT CNTL_OUT DE_OUT HIGH IMPEDANCE HIGH IMPEDANCE LOCK HIGH IMPEDANCE HIGH IMPEDANCE NOTE: R/F = HIGH Figure 7. PLL Lock to REFCLK and Power-Down Delay OUTEN OUTEN 2.0V 0.8V tOE tOZ DE_OUT DE_OUT LOCK RGB_OUT[17:0] LOCK HIGH-Z CNTL_OUT[8:0] ACTIVE RGB_OUT[17:0] ACTIVE HIGH-Z CNTL_OUT[8:0] Figure 8. Output Enable Time Figure 9. Output Disable Time _______________________________________________________________________________________ 9 MAX9218 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer Detailed Description The MAX9218 DC-balanced deserializer operates at a parallel clock frequency of 3MHz to 35MHz, deserializing video data to the RGB_OUT[17:0] outputs when the data enable output DE_OUT is high, or control data to the CNTL_OUT[8:0] outputs when DE_OUT is low. The video phase words are decoded using 2 overhead bits, EN0 and EN1. Control phase words are decoded with 1 overhead bit, EN0. Encoding, performed by the MAX9217 serializer, reduces EMI and maintains DC balance across the serial cable. The serial input word formats are shown in Table 1 and Table 2. Control data inputs C0 to C4, each repeated over 3 serial bit times by the serializer, are decoded using majority voting. Two or three bits at the same state determine the state of the recovered bit, providing single bit-error tolerance for C0 to C4. The state of C5 to C8 is determined by the level of the bit itself (no voting is used). AC-Coupling Benefits AC-coupling increases the input voltage of the LVDS receiver to the voltage rating of the capacitor. Two capacitors are sufficient for isolation, but four capacitors—two at the serializer output and two at the deserializer input—provide protection if either end of the cable is shorted to a high voltage. AC-coupling blocks low-frequency ground shifts and common-mode noise. The MAX9217 serializer can also be DC-coupled to the MAX9218 deserializer. Figure 10 is the AC-coupled serializer and deserializer with two capacitors per link, and Figure 11 is the AC-coupled serializer and deserializer with four capacitors per link. Applications Information Selection of AC-Coupling Capacitors See Figure 12 for calculating the capacitor values for AC-coupling, depending on the parallel clock frequency. The plot shows capacitor values for two- and fourcapacitor-per-link systems. For applications using less than 18MHz clock frequency, use 0.125µF capacitors. Termination and Input Bias The IN+ and IN- LVDS inputs are internally connected to +1.2V through 35kΩ (min) to provide biasing for ACcoupling (Figure 1). Assuming 100Ω interconnect, the LVDS input can be terminated with a 100Ω resistor. Match the termination to the differential impedance of the interconnect. Use a Thevenin termination, providing 1.2V bias, on an AC-coupled link in noisy environments. For interconnect with 100Ω differential impedance, pull each LVDS line up to VCC with 130Ω and down to ground with 82Ω at the deserializer input (Figure 10 and Figure 11). This termination provides both differential and commonmode termination. The impedance of the Thevenin termination should be half the differential impedance of the interconnect and provide a bias voltage of 1.2V. Table 1. Serial Video Phase Word Format 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 EN0 EN1 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 Bit 0 is the LSB and is deserialized first. EN[1:0] are encoding bits. S[17:0] are encoded symbols. Table 2. Serial Control Phase Word Format 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 EN0 C0 C0 C0 C1 C1 C1 C2 C2 C2 C3 C3 C3 C4 C4 C4 C5 C6 C7 C8 Bit 0 is the LSB and is deserialized first. C[8:0] are the mapped control inputs. 10 ______________________________________________________________________________________ 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer OUT IN * CMF DE_IN 82Ω PLL MOD0 TIMING AND CONTROL 1 R/F OUTEN RGB_OUT 0 CNTL_OUT DE_OUT 82Ω PCLK_OUT RNG0 PCLK_IN RNG0 RNG1 DC BALANCE/ DECODE PAR-TO-SER 0 CNTL_IN DC BALANCE/ ENCODE 1 INPUT LATCH RGB_IN * SER-TO-PAR 130Ω 130Ω PLL RNG1 REF_IN MOD1 PWRDWN TIMING AND CONTROL PWRDWN LOCK MAX9217 MAX9218 CERAMIC RF SURFACE-MOUNT CAPACITOR 100Ω DIFFERENTIAL STP CABLE *CAPS CAN BE AT EITHER END. Figure 10. AC-Coupled Serializer and Deserializer with Two Capacitors per Link VCC IN OUT CMF DE_IN 82Ω 82Ω RNG0 PCLK_IN RNG0 RNG1 PLL TIMING AND CONTROL MOD0 SER-TO-PAR 130Ω DC BALANCE/ DECODE 0 PAR-TO-SER CNTL_IN 1 INPUT LATCH RGB_IN DC BALANCE/ ENCODE 130Ω RNG1 1 R/F OUTEN RGB_OUT 0 CNTL_OUT DE_OUT PCLK_OUT PLL REF_IN MOD1 PWRDWN TIMING AND CONTROL PWRDWN MAX9217 CERAMIC RF SURFACE-MOUNT CAPACITOR LOCK MAX9218 100Ω DIFFERENTIAL STP CABLE Figure 11. AC-Coupled Serializer and Deserializer with Four Capacitors per Link ______________________________________________________________________________________ 11 MAX9218 VCC Input Frequency Detection A frequency-detection circuit detects when the LVDS input is not switching. When not switching, all outputs except LOCK are low, LOCK is high, and PCLK_OUT follows REFCLK. This condition occurs, for example, if the serializer is not driving the interconnect or if the interconnect is open. Frequency Range Setting (RNG[1:0]) The RNG[1:0] inputs select the operating frequency range of the MAX9218 and the transition time of the outputs. Select the frequency range that includes the MAX9217 serializer PCLK_IN frequency. Table 3 shows the selectable frequency ranges and the corresponding data rates and output transition times. Power Down Driving PWRDWN low puts the outputs in high impedance and stops the PLL. With PWRDWN ≤ 0.3V and all LVTTL/LVCMOS inputs ≤ 0.3V or ≥ VCC - 0.3V, the supply current is reduced to less than 50µA. Driving PWRDWN high initiates lock to the local reference clock (REFCLK) and afterwards to the serial input. Lock and Loss of Lock (LOCK) When PWRDWN is driven high, the PLL begins locking to REFCLK, drives LOCK from high impedance to high and the other outputs from high impedance to low except PCLK_OUT. PCLK_OUT outputs REFCLK while the PLL is locking to REFCLK. Locking to REFCLK takes a maximum of 16,385 REFCLK cycles. When locking to REFCLK is complete, the serial input is monitored for a transition word. When a transition word is found, LOCK is driven low indicating valid output data, and the parallel rate clock recovered from the serial input is output on PCLK_OUT. PCLK_OUT is stretched on the change from REFCLK to recovered clock (or vice versa). Table 3. Frequency Range Programming PARALLEL CLOCK (MHz) SERIAL DATA RATE (Mbps) 3 to 7 60 to 140 RNG1 RNG0 0 0 0 1 1 0 7 to 15 140 to 300 1 1 15 to 35 300 to 700 12 OUTPUT TRANSITION TIME Slow AC-COUPLING CAPACITOR VALUE vs. PARALLEL CLOCK FREQUENCY 140 125 CAPACITOR VALUE (nF) MAX9218 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer FOUR CAPACITORS PER LINK 110 95 80 65 TWO CAPACITORS PER LINK 50 35 20 18 21 24 27 30 33 36 PARALLEL CLOCK FREQUENCY (MHz) Figure 12. AC-Coupling Capacitor Values vs. Clock Frequency of 18MHz to 35MHz If a transition word is not detected within 220 cycles of PCLK_OUT, LOCK is driven high and the other outputs except PCLK_OUT are driven low. REFCLK is output on PCLK_OUT and the deserializer continues monitoring the serial input for a transition word. See Figure 7 for the synchronization timing diagram. Output Enable (OUTEN) and Busing Outputs The outputs of two MAX9218s can be bused to form a 2:1 mux with the outputs controlled by the output enable. Wait 30ns between disabling one deserializer (driving OUTEN low) and enabling the second one (driving OUTEN high) to avoid contention of the bused outputs. OUTEN controls all outputs. Rising or Falling Output Latch Edge (R/F) The MAX9218 has a selectable rising or falling output latch edge through a logic setting on R/F. Driving R/F high selects the rising output latch edge, which latches the parallel output data into the next chip on the rising edge of PCLK_OUT. Driving R/F low selects the falling output latch edge, which latches the parallel output data into the next chip on the falling edge of PCLK_OUT. The MAX9218 output-latch-edge polarity does not need to match the MAX9217 serializer inputlatch-edge polarity. Select the latch-edge polarity required by the chip being driven by the MAX9218. Fast ______________________________________________________________________________________ 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer RGB_OUT[17:0] are grouped into three groups of six, with each group switching about 1ns apart in the video phase to reduce EMI and ground bounce. CNTL_OUT[8:0] switch during the control phase. Output transition times are slower in the 3MHz-to-7MHz and 7MHz-to-15MHz ranges and faster in the 15MHz-to35MHz range. (VCCLVDS supply and VCCLVDS GND). The grounds are isolated by diode connections. Bypass each V CC , VCCO, VCCPLL, and VCCLVDS pin with high-frequency, surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. The outputs are powered from V CCO , which accepts a 1.71V to 3.6V supply, allowing direct interface to inputs with 1.8V to 3.3V logic levels. Data Enable Output (DE_OUT) Cables and Connectors The MAX9218 deserializes video and control data at different times. Control data is deserialized during the video blanking time. DE_OUT high indicates that video data is being deserialized and output on RGB_OUT[17:0]. DE_OUT low indicates that control data is being deserialized and output on CNTL_OUT[8:0]. When outputs are not being updated, the last data received is latched on the outputs. Figure 13 shows the DE_OUT timing. Interconnect for LVDS typically has a differential impedance of 100Ω. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Power-Supply Circuits and Bypassing There are separate on-chip power domains for digital circuits and LVTTL/LVCMOS inputs (VCC supply and GND), outputs (V CCO supply and V CCO GND), PLL (VCCPLL supply and VCCPLL GND), and the LVDS input CONTROL DATA Twisted-pair and shielded twisted-pair cables offer superior signal quality compared to ribbon cable and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver. Board Layout Separate the LVTTL/LVCMOS outputs and LVDS inputs to prevent crosstalk. A four-layer PC board with separate layers for power, ground, and signals is recommended. VIDEO DATA CONTROL DATA PCLK_OUT CNTL_OUT DE_OUT RGB_OUT PCLK_OUT TIMING SHOWN FOR R/F = HIGH (RISING OUTPUT LATCH EDGE) = OUTPUT DATA HELD Figure 13. Output Timing ______________________________________________________________________________________ 13 MAX9218 Staggered and Transition Time Adjusted Outputs MAX9218 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer ESD Protection The MAX9218 ESD tolerance is rated for the Human Body Model and ISO 10605. ISO 10605 specifies ESD tolerance for electronic systems. The Human Body 1MΩ CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF Model discharge components are CS = 100pF and RD = 1.5kΩ (Figure 14). The ISO 10605 discharge components are CS = 330pF and RD = 2kΩ (Figure 15). RD 1.5kΩ 50Ω TO 100Ω CHARGE-CURRENTLIMIT RESISTOR DISCHARGE RESISTANCE STORAGE CAPACITOR Figure 14. Human Body ESD Test Circuit DEVICE UNDER TEST HIGHVOLTAGE DC SOURCE CS 330pF RD 2kΩ DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST Figure 15. ISO 10605 Contact Discharge ESD Test Circuit Chip Information TRANSISTOR COUNT: 17,782 PROCESS: CMOS 14 ______________________________________________________________________________________ 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer 32L/48L,TQFP.EPS PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm 21-0054 E 1 2 PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.4mm 21-0054 E 2 2 ______________________________________________________________________________________ 15 MAX9218 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) 48L THIN QFN.EPS MAX9218 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Deserializer PACKAGE OUTLINE, 48L THIN QFN 6x6x0.8mm BODY / 0.4mm LEAD PITCH A 21-0160 1 2 NOTE : 1. ALL DIMENSIONS ARE IN mm. ANGLES IN DEGREES. 2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. COPLANARITY SHALL NOT EXCEED 0.08mm. 3. WARPAGE SHALL NOT EXCEED 0.10 mm. 4. PACKAGE LENGTH / PACKAGE WIDTH ARE CONSIDERED AS SPECIAL CHARACTERISTIC. (S) 5. REFER TO JEDEC MO-220. 6. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 7. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. EXPOSED PAD VARIATONS COMMON DIMENSIONS MIN. NOM. MAX. A 0.700 0.750 0.800 A1 0.000 -- -- 0.050 SYMBOLS A2 D2 E2 PKG. CODE MIN. NOM. MAX. MIN. NOM. MAX. T4866-1 4.20 4.30 4.40 4.20 4.30 4.40 0.200 REF. b 0.150 0.200 0.250 D 5.900 6.000 6.100 e 0.400 TYP. E 5.900 6.000 6.050 k 0.250 0.350 0.450 k1 0.350 0.450 0.550 L 0.400 0.500 0.600 L1 0.300 0.400 0.500 N 48 ND 12 NE 12 PACKAGE OUTLINE, 48L THIN QFN 6x6x0.8mm BODY / 0.4mm LEAD PITCH 21-0160 A 2 2 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.