AD AD9547

Dual/Quad Input Network Clock
Generator/Synchronizer
AD9547
FEATURES
APPLICATIONS
Supports Stratum 2 stability in holdover mode
Supports reference switchover with phase build-out
Supports hitless reference switchover
Automatic/manual holdover and reference switchover
2 pairs of reference input pins, with each pair configurable
as a single differential input or as 2 independent singleended inputs
Input reference frequencies from 1 kHz to 750 MHz
Reference validation and frequency monitoring (1 ppm)
Programmable input reference switchover priority
30-bit programmable input reference divider
2 pairs of clock output pins, with each pair configurable as
a single differential LVDS/LVPECL output or as 2 singleended CMOS outputs
Output frequencies up to 450 MHz
20-bit integer and 10-bit fractional programmable feedback
divider
Programmable digital loop filter covering loop bandwidths
from 0.001 Hz to 100 kHz
Optional low noise LC-VCO system clock multiplier
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
Software controlled power-down
64-lead LFCSP package
Network synchronization
Cleanup of reference clock jitter
SONET/SDH clocks up to OC-192, including FEC
Stratum 2 holdover, jitter cleanup, and phase transient
control
Stratum 3E and Stratum 3 reference clocks
Wireless base stations, controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9547 provides synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9547 generates an output clock that is synchronized to one
of two differential or four single-ended external input references.
The digital PLL allows for reduction of input time jitter or phase
noise associated with the external references. The AD9547 continuously generates a clean (low jitter), valid output clock, even
when all references fail, by means of digitally controlled loop and
holdover circuitry.
The AD9547 operates over an industrial temperature range of
−40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
ANALOG
FILTER
STABLE
SOURCE
AD9547
CLOCK
MULTIPLIER
CLOCK DISTRIBUTION
CHANNEL 0
DIVIDER
DIGITAL
PLL
CHANNEL 1
DIVIDER
DAC
REFERENCE INPUTS
AND
MONITOR MUX
SYNC
EEPROM
STATUS AND
CONTROL PINS
08300-001
SERIAL CONTROL INTERFACE
(SPI or I2C)
Figure 1.
Rev. 0
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
AD9547
TABLE OF CONTENTS
Features .............................................................................................. 1 Digital Phase-Locked Loop (DPLL) Core............................... 32 Applications ....................................................................................... 1 Direct Digital Synthesizer (DDS) ............................................. 34 General Description ......................................................................... 1 Tuning Word Processing ........................................................... 35 Functional Block Diagram .............................................................. 1 Loop Control State Machine ..................................................... 36 Revision History ............................................................................... 3 System Clock Inputs................................................................... 37 Specifications..................................................................................... 4 SYSCLK PLL Multiplier............................................................. 38 Supply Voltage ............................................................................... 4 Clock Distribution ..................................................................... 39 Supply Current .............................................................................. 4 Status and Control .......................................................................... 44 Power Dissipation ......................................................................... 4 Multifunction Pins (M0 to M7) ............................................... 44 Logic Inputs (M0 to M7, RESET)............................................... 5 IRQ Pin ........................................................................................ 45 Logic Outputs (M0 to M7, IRQ) ................................................ 5 Watchdog Timer ......................................................................... 45 System Clock Inputs (SYSCLKP, SYSCLKN)............................ 5 EEPROM ..................................................................................... 46 Distribution Clock Inputs (CLKINP, CLKINN) ...................... 6 Serial Control Port ......................................................................... 50 Reference Inputs (REFA/REFAA, REFB/REFBB) .................... 7 SPI/I2C Port Selection ................................................................ 50 Reference Monitors ...................................................................... 7 SPI Serial Port Operation .......................................................... 50 Reference Switchover Specifications .......................................... 8 I2C Serial Port Operation .......................................................... 54 Distribution Clock Outputs (OUT0, OUT1) ........................... 8 I/O Programming Registers .......................................................... 57 DAC Output Characteristics (DACOUTP, DACOUTN) ....... 9 Buffered/Active Registers .......................................................... 57 Time Duration of Digital Functions ........................................ 10 Autoclearing Registers ............................................................... 57 Digital PLL .................................................................................. 10 Register Access Restrictions...................................................... 57 Digital PLL Lock Detection ...................................................... 10 Register Map ................................................................................... 58 Holdover Specifications ............................................................. 10 Register Bit Descriptions ............................................................... 67 Serial Port Specifications—SPI Mode ...................................... 11 Serial Port Configuration and Part Identification
(Register 0x0000 to Register 0x0005) ...................................... 67 Serial Port Specifications—I C Mode ...................................... 12 2
Jitter Generation ......................................................................... 13 Absolute Maximum Ratings.......................................................... 14 ESD Caution ................................................................................ 14 Pin Configuration and Function Descriptions ........................... 15 Typical Performance Characteristics ........................................... 18 Input/Output Termination Recommendations .......................... 23 Getting Started ................................................................................ 24 Power-On Reset .......................................................................... 24 Initial M0 to M7 Pin Programming ......................................... 24 Device Register Programming .................................................. 24 System Clock (SYSCLK) (Register 0x0100 to
Register 0x0108) ......................................................................... 68 General Configuration (Register 0x0200 to
Register 0x0214) ......................................................................... 69 DPLL Configuration (Register 0x0300 to
Register 0x031B)......................................................................... 72 Clock Distribution Output Configuration
(Register 0x0400 to Register 0x0419) ...................................... 74 Reference Input Configuration (Register 0x0500 to
Register 0x0507) .......................................................................... 76 Profile Registers (Register 0x0600 to Register 0x07FF) ........ 78 Theory of Operation ...................................................................... 26 Operational Controls (Register 0x0A00 to
Register 0x0A10) ........................................................................ 88 Overview...................................................................................... 26 Status Readback (Register 0x0D00 to Register 0x0D19) ...... 92 Reference Clock Inputs .............................................................. 27 Reference Monitors .................................................................... 27 Reference Profiles ....................................................................... 28 Reference Switchover ................................................................. 30 Nonvolatile Memory (EEPROM) Control
(Register 0x0E00 to Register 0x0E03) ..................................... 94 EEPROM Storage Sequence (Register 0x0E10 to
Register 0x0E3F) .......................................................................... 95 Rev. 0 | Page 2 of 104
AD9547
Applications Information ...............................................................98 Outline Dimensions ......................................................................102 Power Supply Partitions .............................................................98 Ordering Guide .........................................................................102 Thermal Performance.................................................................98 Calculating the Digital Filter Coefficients ...............................99 REVISION HISTORY
7/09—Revision 0: Initial Version
Rev. 0 | Page 3 of 104
AD9547
SPECIFICATIONS
Minimum and maximum values apply for the full range of supply voltage and operating temperature variation. Typical values apply for
AVDD3 = DVDD3 = 3.3 V, AVDD = DVDD = 1.8 V, TA = 25°C, IDAC = 20 mA (full scale), unless otherwise noted.
SUPPLY VOLTAGE
Table 1.
Parameter
DVDD3
DVDD
AVDD3
3.3 V Supply (Typical)
1.8 V Supply (Alternative)
AVDD
Min
3.135
1.71
3.135
3.135
1.71
1.71
Typ
3.30
1.80
3.30
3.30
1.80
1.80
Max
3.465
1.89
3.465
3.465
1.89
1.89
Unit
V
V
V
V
V
V
Test Conditions/Comments
Pin 7, Pin 58
Pin 1, Pin 6, Pin 8, Pin 10, Pin 11, Pin 53, Pin 59, Pin 64
Pin 16, Pin 33, Pin 43, Pin 49
Pin 25, Pin 31
Pin 25, Pin 31
Pin 17, Pin 18, Pin 23, Pin 28, Pin 32, Pin 36, Pin 39, Pin 42, Pin 46, Pin 50
SUPPLY CURRENT
The test conditions for the maximum supply current are the same as the test conditions for the All Blocks Running section of Table 3. The
test conditions for the typical supply current are the same as the test conditions for the Typical Configuration section of Table 3.
Table 2.
Parameter
IDVDD3
IDVDD
IAVDD3
3.3 V Supply (Typical)
1.8 V Supply (Alternative)
IAVDD
Min
Typ
1.5
190
52
24
24
135
Max
3
215
70
55
55
150
Unit
mA
mA
mA
mA
mA
mA
Test Conditions/Comments
Pin 7, Pin 58
Pin 1, Pin 6, Pin 8, Pin 10, Pin 11, Pin 53, Pin 59, Pin 64
Pin 16, Pin 33, Pin 43, Pin 49
Pin 25, Pin 31
Pin 25, Pin 31
Pin 17, Pin 18, Pin 23, Pin 28, Pin 32, Pin 36, Pin 39, Pin 42, Pin 46, Pin 50
Min
Typ
800
Max
1100
Unit
mW
ALL BLOCKS RUNNING
900
1250
mW
FULL POWER-DOWN
13
mW
−105
mW
Test Conditions/Comments
fSYSCLK = 20 MHz 1 ; fS = 1 GHz 2 ; fDDS = 122.88 MHz 3 ; one LVPECL clock
distribution output running at 122.88 MHz (all others powered
down); one input reference running at 100 MHz (all others
powered down)
fSYSCLK = 20 MHz1; fS = 1 GHz2; fDDS = 399 MHz3; all clock distribution
outputs configured as LVPECL at 399 MHz; all input references
configured as differential at 100 MHz; fractional-N active (R = 10,
S = 39, U = 9, V = 10)
Conditions = typical configuration; no external pull-up or pulldown resistors
Conditions = typical configuration; table values show the change
in power due to the indicated operation
fSYSCLK = 1 GHz1; high frequency direct input mode
7
13
mW
mW
70
75
65
mW
mW
mW
POWER DISSIPATION
Table 3.
Parameter
TYPICAL CONFIGURATION
INCREMENTAL POWER DISSIPATION
SYSCLK PLL Off
Input Reference On
Differential
Single-Ended
Output Distribution Driver On
LVDS
LVPECL
CMOS
1
2
3
Single 3.3 V CMOS output with a 10 pF load
fSYSCLK is the frequency at the SYSCLKP and SYSCLKN pins.
fS is the sample rate of the output DAC.
fDDS is the output frequency of the DDS.
Rev. 0 | Page 4 of 104
AD9547
LOGIC INPUTS (M0 TO M7, RESET)
Table 4.
Parameter
INPUT VOLTAGE
Input High Voltage (VIH)
Input Low Voltage (VIL)
INPUT CURRENT (IINH, IINL)
INPUT CAPACITANCE (CIN)
Min
Typ
Max
Unit
0.8
±200
V
V
μA
pF
Max
Unit
Test Conditions/Comments
0.4
V
V
1
1
μA
μA
IOH = 1 mA
IOL = 1 mA
Open-drain mode
VOH = 3.3 V
VOL = 0 V
Max
Unit
Test Conditions/Comments
1000
MHz
V/μs
%
V
mV p-p
2.1
±80
3
Test Conditions/Comments
LOGIC OUTPUTS (M0 TO M7, IRQ)
Table 5.
Parameter
OUTPUT VOLTAGE
Output High Voltage (VOH)
Output Low Voltage (VOL)
IRQ LEAKAGE CURRENT
Active Low Output Mode
Active High Output Mode
Min
Typ
2.7
SYSTEM CLOCK INPUTS (SYSCLKP, SYSCLKN)
Table 6.
Parameter
SYSTEM CLOCK PLL BYPASSED
Input Frequency Range
Minimum Input Slew Rate
Duty Cycle
Common-Mode Voltage
Differential Input Voltage Sensitivity
Input Capacitance
Input Resistance
SYSTEM CLOCK PLL ENABLED
PLL Output Frequency Range
Phase Frequency Detector (PFD) Rate
Frequency Multiplication Range
VCO Gain
High Frequency Path
Input Frequency Range
Minimum Input Slew Rate
Frequency Divider Range
Common-Mode Voltage
Differential Input Voltage Sensitivity
Input Capacitance
Input Resistance
Min
Typ
500
1000
40
60
1.2
100
2
2.5
900
pF
kΩ
1000
150
255
6
70
100.1
200
1
Internally generated
Minimum voltage across pins is required to ensure
switching between logic states; the instantaneous
voltage on either pin must not exceed the supply rails; ac
ground the unused input to accommodate single-ended
operation
Single-ended, each pin
MHz
MHz
Assumes valid system clock and PFD rates
MHz/V
500
MHz
V/μs
8
1
V
mV pp
3
2.5
pF
kΩ
100
Minimum limit imposed for jitter performance
Rev. 0 | Page 5 of 104
Minimum limit imposed for jitter performance
Binary steps (M = 1, 2, 4, 8)
Internally generated
This is the minimum voltage required across the pins to
ensure switching between logic states; the
instantaneous voltage on either pin must not exceed the
supply rails; ac ground the unused input to accommodate
single-ended operation
Single-ended, each pin
AD9547
Parameter
Low Frequency Path
Input Frequency Range
Minimum Input Slew Rate
Common-Mode Voltage
Differential Input Voltage Sensitivity
Input Capacitance
Input Resistance
Crystal Resonator Path
Crystal Resonator Frequency Range
Maximum Crystal Motional
Resistance
Min
Typ
Max
Unit
100
1.2
MHz
V/μs
V
mV pp
3
4
pF
kΩ
3.5
50
100
10
50
100
MHz
Ω
Max
500
Test Conditions/Comments
Minimum limit imposed for jitter performance
Internally generated
This is the minimum voltage required across the pins to
ensure switching between logic states; the
instantaneous voltage on either pin must not exceed the
supply rails; ac ground the unused input to accommodate
single-ended operation
Single-ended, each pin
Fundamental mode, AT cut
See the System Clock Inputs section for recommendations
DISTRIBUTION CLOCK INPUTS (CLKINP, CLKINN)
Table 7.
Parameter
INPUT FREQUENCY RANGE
MINIMUM SLEW RATE
COMMON-MODE VOLTAGE
DIFFERENTIAL INPUT VOLTAGE SENSITIVITY
Min
62.5
75
100
Unit
MHz
V/μs
mV
mV p-p
DIFFERENTIAL INPUT POWER SENSITIVITY
−15
dBm
INPUT CAPACITANCE
INPUT RESISTANCE
Typ
700
3
5
pF
kΩ
Rev. 0 | Page 6 of 104
Test Conditions/Comments
Minimum limit imposed for jitter performance
Internally generated
Capacitive coupling required; ac ground the unused
input to accommodate single-ended operation; the
instantaneous voltage on either pin must not exceed
the supply rails
Same as voltage sensitivity but specified as power into a
50 Ω load
Each pin has a 2.5 kΩ internal dc bias resistance
AD9547
REFERENCE INPUTS (REFA/REFAA, REFB/REFBB)
Table 8.
Parameter
DIFFERENTIAL OPERATION
Frequency Range
Sinusoidal Input
LVPECL Input
LVDS Input
Minimum Input Slew Rate
Common-Mode Input Voltage
Differential Input Voltage
Sensitivity
Input Resistance
Input Capacitance
Minimum Pulse Width High
Minimum Pulse Width Low
SINGLE-ENDED OPERATION
Frequency Range (CMOS)
Minimum Input Slew Rate
Input Voltage High (VIH)
1.2 V to 1.5 V Threshold Setting
1.8 V to 2.5 V Threshold Setting
3.0 V to 3.3 V Threshold Setting
Input Voltage Low (VIL)
1.2 V to 1.5 V Threshold Setting
1.8 V to 2.5 V Threshold Setting
3.0 V to 3.3 V Threshold Setting
Input Resistance
Input Capacitance
Minimum Pulse Width High
Minimum Pulse Width Low
Min
Typ
10
0.001
0.001
40
Max
Unit
750
750
750
MHz
MHz
MHz
V/μs
V
mV
2
±65
25
3
Minimum limit imposed for jitter performance
Internally generated
This is the minimum voltage required across the pins to
ensure switching between logic states; the instantaneous
voltage on either pin must not exceed the supply rails
kΩ
pF
ps
ps
620
620
10
40
Test Conditions/Comments
250
0.9
1.2
1.9
MHz
V/μs
Minimum limit imposed for jitter performance
V
V
V
0.27
0.5
1.0
V
V
V
kΩ
pF
ns
ns
Max
Unit
Test Conditions/Comments
9.54 × 10
1.2
0.1
NPDP
Δf/fREF
NPDP = nominal phase detector period (NPDP = fREF/R) 1
Programmable (lower bound subject to quality of SYSCLK)
0.001
0.001
65.535
65.535
sec
sec
Programmable in 1 ms increments
Programmable in 1 ms increments
45
3
1.5
1.5
REFERENCE MONITORS
Table 9.
Parameter
REFERENCE MONITOR
Loss of Reference Detection Time
Frequency Out-of-Range Limits
TIMERS
Validation Timer
Redetect Timer
1
Min
Typ
−7
fREF is the frequency of the active reference; R is the frequency division factor determined by the R divider.
Rev. 0 | Page 7 of 104
AD9547
REFERENCE SWITCHOVER SPECIFICATIONS
Table 10.
Parameter
MAXIMUM OUTPUT PHASE
PERTURBATION (PHASE BUILD-OUT
SWITCHOVER)
MAXIMUM TIME/TIME SLOPE
(HITLESS SWITCHOVER)
Min
Max
200
Unit
ps
Test Conditions/Comments
Assumes a jitter-free reference; satisfies
Telcordia GR-1244-CORE requirements
65,535
ns/sec
Minimum/maximum values are programmable upper bounds; a minimum value
ensures <10% error; satisfies Telcordia
GR-1244-CORE requirements
5
NPDP
3
NPDP
NPDP = nominal phase detector period
(NPDP = fREF/R) 1
NPDP = nominal phase detector period
(NPDP = fREF/R)1
315
TIME REQUIRED TO SWITCH TO A NEW
REFERENCE
Hitless Switchover
Phase Build-Out Switchover
1
Typ
40
fREF is the frequency of the active reference; R is the frequency division factor determined by the R divider.
DISTRIBUTION CLOCK OUTPUTS (OUT0, OUT1)
Table 11.
Parameter
LVPECL MODE
Maximum Output Frequency
Rise/Fall Time1 (20% to 80%)
Duty Cycle
Differential Output Voltage Swing
Common-Mode Output Voltage
LVDS MODE
Maximum Output Frequency
Rise/Fall Time 1 (20% to 80%)
Duty Cycle
Differential Output Voltage Swing
Balanced (VOD)
Min
Typ
725
180
Short-Circuit Output Current
CMOS MODE
Maximum Output Frequency
3.3 V Supply
Strong Drive Strength Setting
Weak Drive Strength Setting
1.8 V Supply
Unit
MHz
ps
%
mV
Test Conditions/Comments
Using internal current setting resistor
(nominal 3.12 kΩ)
45
630
770
315
55
910
AVDD3 − 1.5
AVDD3 − 1.3
AVDD3 − 1.05
V
Magnitude of voltage across pins; output
driver static
Output driver static
Using internal current setting resistor
(nominal 3.12 kΩ)
MHz
ps
%
100 Ω termination across the output pins
40
350
60
247
454
mV
50
mV
1.375
50
V
mV
24
mA
725
200
Unbalanced (ΔVOD)
Offset Voltage
Common Mode (VOS)
Common-Mode Difference (ΔVOS)
Max
1.125
13
100 Ω termination across output pins
Voltage swing between output pins;
output driver static
Absolute difference between voltage
swing of normal pin and inverted pin;
output driver static
Output driver static
Voltage difference between pins; output
driver static
Output driver static
Weak drive option not supported for
operating the CMOS drivers using a 1.8 V
supply
10 pF load
250
25
150
MHz
MHz
MHz
Rev. 0 | Page 8 of 104
AD9547
Parameter
Rise/Fall Time1 (20% to 80%)
3.3 V Supply
Strong Drive Strength Setting
Weak Drive Strength Setting
1.8 V Supply
Duty Cycle
Output Voltage High (VOH)
AVDD3 = 3.3 V, IOH = 10 mA
AVDD3 = 3.3 V, IOH = 1 mA
AVDD3 = 1.8 V, IOH = 1 mA
Output Voltage Low (VOL)
Min
Max
Unit
0.5
8
1.5
2
14.5
2.5
60
ns
ns
ns
%
40
2.6
2.9
1.5
Test Conditions/Comments
10 pF load
10 pF load
Output driver static; strong drive
strength setting
V
V
V
Output driver static; strong drive
strength setting
AVDD3 = 3.3 V, IOL = 10 mA
AVDD3 = 3.3 V, IOL = 1 mA
AVDD3 = 1.8 V, IOL = 1 mA
OUTPUT TIMING SKEW
Between LVPECL Outputs
Between LVDS Outputs
Between CMOS (3.3 V) Outputs
Strong Drive Strength Setting
Weak Drive Strength Setting
Between CMOS (1.8 V) Outputs
Between LVPECL Outputs and LVDS
Outputs
Between LVPECL Outputs and
CMOS Outputs
ZERO-DELAY TIMING SKEW
1
Typ
0.3
0.1
0.1
V
V
V
14
13
125
138
ps
ps
23
24
40
14
240
ps
ps
ps
ps
140
10 pF load
Rising edge only; any divide value
Rising edge only; any divide value
Weak drive option not supported at 1.8 V
19
ps
±5
ns
Output relative to active input reference;
output distribution synchronization to
active reference feature enabled;
assumes manual phase offset
compensation of deterministic latency
Max
450
15
Unit
MHz
mV
Test Conditions/Comments
VSS + 0.5
V
Ω
The listed values are for the slower edge (rising or falling).
DAC OUTPUT CHARACTERISTICS (DACOUTP, DACOUTN)
Table 12.
Parameter
FREQUENCY RANGE
OUTPUT OFFSET VOLTAGE
Min
62.5
VOLTAGE COMPLIANCE RANGE
OUTPUT RESISTANCE
VSS − 0.5
OUTPUT CAPACITANCE
FULL-SCALE OUTPUT CURRENT
GAIN ERROR
Typ
0.5
50
5
20
−12
pF
mA
+12
Rev. 0 | Page 9 of 104
% FS
This is the single-ended voltage at either
DAC output pin (no external load) when
the internal DAC code is such that no
current is delivered to that pin
Single-ended; each pin has an internal
50 Ω termination to VSS
Programmable (8 mA to 31 mA; see the
DAC Output section)
AD9547
TIME DURATION OF DIGITAL FUNCTIONS
Table 13.
Parameter
EEPROM-TO-REGISTER DOWNLOAD TIME
Min
Typ
25
Max
Unit
ms
REGISTER-TO-EEPROM UPLOAD TIME
200
ms
MINIMUM POWER-DOWN EXIT TIME
MAXIMUM TIME FROM ASSERTION OF THE RESET PIN
TO THE M0 TO M7 PINS ENTERING HIGH
IMPEDANCE STATE
10.5
45
μs
ns
Test Conditions/Comments
Using default EEPROM storage sequence
(see Register 0x0E10 to Register 0x0E3F)
Using default EEPROM storage sequence
(see Register 0x0E10 to Register 0x0E3F
Dependent on loop filter bandwidth
DIGITAL PLL
Table 14.
Parameter
PHASE FREQUENCY DETECTOR (PFD) INPUT
FREQUENCY RANGE
LOOP BANDWIDTH
PHASE MARGIN
REFERENCE INPUT (R) DIVISION FACTOR
INTEGER FEEDBACK (S) DIVISION FACTOR
FRACTIONAL FEEDBACK DIVIDE RATIO
1
2
3
Min
0.001
Typ
Max
10
Unit
MHz
Test Conditions/Comments
Maximum fPFD = fS/100 1, 2
0.001
1 × 105
Hz
30
1
8
0
89
230
220
0.999
Degrees
Programmable design parameter;
maximum fLOOP = fREF/(20R) 3
Programmable design parameter
1, 2, …1,073,741,824
8, 9, …1,048,576
Maximum value = 1022/1023
fPFD is the frequency at the input to the phase-frequency detector.
fS is the sample rate of the output DAC.
fREF is the frequency of the active reference; R is the frequency division factor determined by the R divider.
DIGITAL PLL LOCK DETECTION
Table 15.
Parameter
PHASE LOCK DETECTOR
Threshold Programming Range
Threshold Resolution
FREQUENCY LOCK DETECTOR
Threshold Programming Range
Threshold Resolution
Min
Typ
0.001
Max
Unit
65.5
ns
ps
16,700
ns
ps
Reference-to-feedback period difference
Max
Unit
ppm
Test Conditions/Comments
Excludes frequency drift of SYSCLK source;
excludes frequency drift of input reference
prior to entering holdover
1
0.001
1
Test Conditions/Comments
HOLDOVER SPECIFICATIONS
Table 16.
Parameter
FREQUENCY ACCURACY
Min
Typ
<0.01
Rev. 0 | Page 10 of 104
AD9547
SERIAL PORT SPECIFICATIONS—SPI MODE
Table 17.
Parameter
CS
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SCLK
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO
As an Input
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
As an Output
Output Logic 1 Voltage
Output Logic 0 Voltage
SDO
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
SCLK
Clock Rate, 1/tCLK
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup, tS
CS to SCLK Hold, tC
CS Minimum Pulse Width High
Min
Typ
Max
Unit
2.0
0.8
30
110
2
V
V
μA
μA
pF
2.0
0.8
1
1
2
V
V
μA
μA
pF
2.0
0.8
1
1
2
V
V
μA
μA
pF
Test Conditions/Comments
Internal 30 kΩ pull-up resistor
Internal 30 kΩ pull-down resistor
2.7
0.4
V
V
1 mA load current
1 mA load current
0.4
V
V
1 mA load current
1 mA load current
2.7
40
8
12
3
0
14
10
0
6
Rev. 0 | Page 11 of 104
MHz
ns
ns
ns
ns
ns
ns
ns
ns
AD9547
SERIAL PORT SPECIFICATIONS—I2C MODE
Table 18.
Parameter
SDA (AS INPUT), SCL
Min
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Current
Hysteresis of Schmitt Trigger Inputs
Pulse Width of Spikes That Must Be
Suppressed by the Input Filter, tSP
SDA (AS OUTPUT)
Output Logic 0 Voltage
Output Fall Time from VIHmin to VILmax
TIMING
SCL Clock Rate
Bus Free Time Between a Stop and Start
Condition, tBUF
Repeated Start Condition Setup Time, tSU;STA
Repeated Hold Time Start Condition, tHD;STA
0.7 × DVDD3
Stop Condition Setup Time, tSU;STO
Low Period of the SCL Clock, tLOW
High Period of the SCL Clock, tHIGH
SCL/SDA Rise Time, tR
SCL/SDA Fall Time, tF
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
Capacitive Load for Each Bus Line, Cb1
1
Typ
Max
Unit
Test Conditions/Comments
No internal pull-up/pull-down
resistor
For VIN = 10% to 90% of DVDD3
50
V
V
μA
V
ns
0.4
250
V
ns
IO = 3 mA
10 pF ≤ Cb ≤ 400 pF
400
1.3
kHz
μs
0.6
0.6
μs
μs
0.6
1.3
0.6
20 + 0.1 Cb1
20 + 0.1 Cb1
100
100
μs
μs
μs
ns
ns
ns
ns
pF
−10
0.015 × DVDD3
20 + 0.1 Cb
1
0.3 × DVDD3
+10
300
300
400
Cb is the capacitance (pF) of a single bus line.
Rev. 0 | Page 12 of 104
After this period, the first clock
pulse is generated
AD9547
JITTER GENERATION
Table 19.
Parameter
CONDITIONS: fREF = 8 kHz 1 , fDDS = 155.52 MHz 2 ,
fLOOP = 100 Hz 3
Min
Typ
Max
Unit
Bandwidth: 100 Hz to 77 MHz
Bandwidth: 5 kHz to 20 MHz
Bandwidth: 20 kHz to 80 MHz
Bandwidth: 50 kHz to 80 MHz
Bandwidth: 4 MHz to 80 MHz
CONDITIONS: fREF = 19.44 MHz1, fDDS = 155.52 MHz2,
fLOOP = 1 kHz3
0.71
0.34
0.43
0.43
0.31
ps rms
ps rms
ps rms
ps rms
ps rms
Bandwidth: 100 Hz to 77 MHz
Bandwidth: 5 kHz to 20 MHz
Bandwidth: 20 kHz to 80 MHz
Bandwidth: 50 kHz to 80 MHz
Bandwidth: 4 MHz to 80 MHz
CONDITIONS: fREF = 19.44 MHz1, fDDS = 311.04 MHz2,
fLOOP = 1 kHz3
1.05
0.34
0.43
0.43
0.32
ps rms
ps rms
ps rms
ps rms
ps rms
0.67
0.31
0.33
0.33
0.16
ps rms
ps rms
ps rms
ps rms
ps rms
Bandwidth: 100 Hz to 100 MHz
Bandwidth: 5 kHz to 20 MHz
Bandwidth: 20 kHz to 80 MHz
Bandwidth: 50 kHz to 80 MHz
Bandwidth: 4 MHz to 80 MHz
1
fREF is the frequency of the active reference.
fDDS is the output frequency of the DDS.
fLOOP is the DPLL digital loop filter bandwidth.
4
fSYSCLK is the frequency at the SYSCLKP and SYSCLKN pins.
5
fS is the sample rate of the output DAC.
2
3
Rev. 0 | Page 13 of 104
Test Conditions/Comments
fSYSCLK = 50 MHz 4 crystal; fS = 1 GHz 5 ;
Q-divider = 1; default SYSCLK PLL charge
pump current; results valid for LVPECL,
LVDS, and CMOS output logic types
Random jitter
Random jitter
Random jitter
Random jitter
Random jitter
fSYSCLK = 50 MHz4 crystal; fS = 1 GHz5;
Q-divider = 1; default SYSCLK PLL charge
pump current; results valid for LVPECL,
LVDS, and CMOS output logic types
Random jitter
Random jitter
Random jitter
Random jitter
Random jitter
fSYSCLK = 50 MHz4 crystal; fS = 1 GHz5;
Q-divider = 1; default SYSCLK PLL charge
pump current; results valid for LVPECL,
LVDS, and CMOS output logic types
Random jitter
Random jitter
Random jitter
Random jitter
Random jitter
AD9547
ABSOLUTE MAXIMUM RATINGS
Table 20.
Parameter
Analog Supply Voltage (AVDD)
Digital Supply Voltage (DVDD)
Digital I/O Supply Voltage
(DVDD3)
DAC Supply Voltage (AVDD3)
Maximum Digital Input Voltage
Storage Temperature Range
Operating Temperature Range
Lead Temperature
(Soldering 10 sec)
Junction Temperature
Rating
2V
2V
3.6 V
3.6 V
−0.5 V to DVDD3 + 0.5 V
−65°C to +150°C
−40°C to +85°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
150°C
Rev. 0 | Page 14 of 104
AD9547
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DVDD
M7
M6
M5
M4
DVDD
DVDD3
M3
M2
M1
M0
DVDD
IRQ
NC
AVDD
AVDD3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
INDICATOR
AD9547
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
REFBB
REFB
AVDD
REFAA
REFA
AVDD3
AVDD
TDC_VRT
TDC_VRB
AVDD
SYSCLKP
SYSCLKN
AVDD
SYSCLK_LF
SYSCLK_VREG
AVDD3
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO GROUND (VSS).
08300-002
AVDD
AVDD
VSS
CLKINN
CLKINP
VSS
AVDD
OUT_RSET
AVDD3
OUT0P
OUT0N
AVDD
OUT1P
OUT1N
AVDD3
AVDD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DVDD
SCLK/SCL
SDIO
SDO
CS/SDA
DVDD
DVDD3
DVDD
RESET
DVDD
DVDD
VSS
DACOUTP
DACOUTN
VSS
AVDD3
Figure 2. Pin Configuration
Table 21. Pin Function Descriptions
Input/
Output
I
Pin Type
Power
Mnemonic
DVDD
Description
1.8 V Digital Supply.
I
3.3 V CMOS
SCLK/SCL
3
I/O
3.3 V CMOS
SDIO
4
O
3.3 V CMOS
SDO
5
I
3.3 V CMOS
CS/SDA
7, 58
9
I
I
Power
3.3 V CMOS
DVDD3
RESET
10, 11
I
Power
DVDD
12, 15, 19, 22
13
O
O
VSS
DACOUTP
14
O
16
17, 18
I
I
Ground
Differential
output
Differential
output
Power
Power
Serial Programming Clock. Data clock for serial programming. SCLK is used for
SPI mode, and SCL is used for I2C® mode.
Serial Data Input/Output. When the device is in 4-wire mode, data is written
via this pin. In 3-wire mode, both data reads and writes occur on this pin.
There is no internal pull-up/pull-down resistor on this pin.
Serial Data Output. Use this pin to read data in 4-wire mode (high impedance
in 3-wire mode). There is no internal pull-up/pull-down resistor on this pin.
SPI Mode.
Chip Select (CS) Input. Active low. When programming a device, this pin must
be held low. In systems where more than one AD9547 is present, this pin enables
individual programming of each AD9547. In SPI mode, this pin has an internal
30 kΩ pull-up resistor.
I2C Mode.
Serial Data Line (SDA) Input/Output. In I2C Mode, this pin is an output during
read operations and an input during write operations. There is no internal
pull-up resistor in I2C mode.
3.3 V I/O Digital Supply.
Chip Reset. Assertion of this pin (active high) resets the device. This pin has an
internal 50 kΩ pull-down resistor.
1.8 V DAC Decode Digital Supply. Isolate the supply associated with these
DVDD pins from the supply associated with the other DVDD pins.
Analog Ground. Connect to ground.
DAC Output. DACOUTP contains an internal 50 Ω pull-down resistor.
Pin No.
1, 6, 8, 53, 59,
64
2
DACOUTN
AVDD3
AVDD
Complementary DAC Output. DACOUTN contains an internal 50 Ω pull-down
resistor.
3.3 V Analog (DAC) Power Supply.
1.8 V Analog (DAC) Power Supply.
Rev. 0 | Page 15 of 104
AD9547
Pin No.
20
Input/
Output
I
21
I
23
24
I
O
25, 31
I
26
O
LVPECL,
LVDS, or
CMOS
OUT0P
27
O
OUT0N
28, 32
29
I
O
LVPECL,
LVDS, or
CMOS
Power
LVPECL,
LVDS, or
CMOS
30
O
OUT1N
33
34
I
I
LVPECL,
LVDS, or
CMOS
Power
35
O
36, 39
37
I
I
Power
Differential
input
AVDD
SYSCLKN
38
I
Differential
input
SYSCLKP
40, 41
I
42
43, 49
44
I
I
I
Power
Power
Differential
input
45
I
46, 50
I
Differential
input
Power
Pin Type
Differential
input
Mnemonic
CLKINN
Differential
input
Power
Current set
resistor
Power
CLKINP
AVDD
OUT_RSET
AVDD3
AVDD
OUT1P
AVDD3
SYSCLK_VREG
SYSCLK_LF
TDC_VRB,
TDC_VRT
AVDD
AVDD3
REFA
REFAA
AVDD
Description
Clock Distribution Input. In standard operating mode, this pin is connected to
the filtered DACOUTN output. This internally biased input is typically ac-coupled,
and, when configured as such, can accept any differential signal with a singleended swing of at least 400 mV.
Clock Distribution Input. In standard operating mode, this pin is connected to
the filtered DACOUTP output.
1.8 V Analog (Input Receiver) Power Supply.
Connect an optional 3.12 kΩ resistor from this pin to ground (see the Output
Current Control with an External Resistor section).
Analog Supply for Output Driver. These pins are normally 3.3 V but can be
1.8 V. Pin 25 powers OUT0. Pin 31 powers OUT1. Apply power to these pins
even if the corresponding outputs (OUT0P/OUT0N, OUT1P/OUT1N) are not
used (see the Power Supply Partitions section).
Output 0. This output can be configured as LVPECL, LVDS, or single-ended
CMOS. LVPECL and LVDS operation require a 3.3 V output driver power
supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output
driver power supply.
Complementary Output 0. This output can be configured as LVPECL, LVDS, or
single-ended CMOS.
1.8 V Analog (Output Divider) Power Supply.
Output 1. This output can be configured as LVPECL, LVDS, or single-ended
CMOS. LVPECL and LVDS operation require a 3.3 V output driver power
supply. CMOS operation can be either 1.8 V or 3.3 V, depending on the output
driver power supply.
Complementary Output 1. This output can be configured as LVPECL, LVDS, or
single-ended CMOS.
3.3 V Analog (System Clock) Power Supply.
System Clock Loop Filter Voltage Regulator. Connect a 0.1 μF capacitor from
this pin to ground. This pin is also the ac ground reference for the integrated
external loop filter of the SYSCLK PLL multiplier (see the SYSCLK PLL Multiplier
section).
System Clock Multiplier Loop Filter. When using the frequency multiplier to
drive the system clock, an external loop filter can be attached to this pin.
1.8 V Analog (System Clock) Power Supply.
Complementary System Clock Input. Complementary signal to SYSCLKP.
SYSCLKN contains internal dc biasing and should be ac-coupled with a 0.01 μF
capacitor, except when using a crystal. When using a crystal, connect it across
SYSCLKP and SYSCLKN.
System Clock Input. SYSCLKP contains internal dc biasing and should be accoupled with a 0.01 μF capacitor, except when using a crystal. When using a
crystal, connect it directly across SYSCLKP and SYSCLKN. Single-ended 1.8 V
CMOS is also an option but can introduce a spur if the duty cycle is not 50%.
When using SYSCLKP as a single-ended input, connect a 0.01 μF capacitor
from SYSCLKN to ground.
Use capacitive decoupling on these pins (see Figure 36).
1.8 V Analog (Time-to-Digital Converter) Power Supply.
3.3 V Analog (Reference Input) Power Supply.
Reference A Input. This internally biased input is typically ac-coupled and,
when configured as such, can accept any differential signal with a singleended swing of up to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.
Complementary Reference A Input. Complementary signal to the input provided on Pin 44. The user can configure this pin as a separate single-ended input.
1.8 V Analog (Reference Input) Power Supply.
Rev. 0 | Page 16 of 104
AD9547
Pin No.
47
Input/
Output
I
48
I
51
52
54, 55, 56, 57,
60, 61, 62, 63
EP
I
O
I/O
O
Pin Type
Differential
input
Mnemonic
REFB
Differential
input
REFBB
Logic
3.3 V CMOS
Exposed
pad
NC
IRQ
M0, M1, M2, M3,
M4, M5, M6, M7
Exposed pad
Description
Reference B Input. This internally biased input is typically ac-coupled and,
when configured as such, can accept any differential signal with a single-ended
swing of up to 3.3 V. If dc-coupled, input can be LVPECL, CMOS, or LVDS.
Complementary Reference B Input. Complementary signal to the input provided
on Pin 47. The user can configure this pin as a separate single-ended input.
No Connection. This pin should be left floating.
Interrupt Request Line.
Configurable I/O Pins. These pins are configured under program control.
The exposed pad must be connected to ground (VSS).
Rev. 0 | Page 17 of 104
AD9547
TYPICAL PERFORMANCE CHARACTERISTICS
fREF = input reference clock frequency, fO = clock frequency, fSYSCLK = SYSCLK input frequency, fS =internal system clock frequency, LBW =
DPLL loop bandwidth, PLL off = SYSCLK PLL bypassed, PLL on = SYSCLK PLL enabled, ICP = SYSCLK PLL charge pump current, LF =
SYSCLK PLL loop filter. AVDD, AVDD3, and DVDD at nominal supply voltage, fS = 1 GHz, ICP = automatic mode, LF = internal, unless
otherwise noted.
–90
PHASE NOISE (dBc/Hz)
–110
–120
–130
–100
–110
–120
–130
–140
–140
–150
–150
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
–160
100
08300-068
PHASE NOISE (dBc/Hz)
–90
–100
–160
100
–80
–70
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 333fs (–69.8dBc)
20kHz TO 80MHz: 430fs (–67.6dBc) (EXTRAPOLATED)
100k
1M
10M
100M
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 310fs (–64.4dBc)
20kHz TO 80MHz: 330fs (–63.9dBc)
–80
–90
PHASE NOISE (dBc/Hz)
–100
–110
–120
–130
–100
–110
–120
–130
–140
–140
–150
–150
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
08300-056
PHASE NOISE (dBc/Hz)
10k
Figure 5. Additive Phase Noise (Output Driver = LVPECL),
fREF = 19.44 MHz, fO = 311.04 MHz,
LBW = 1 kHz, fSYSCLK = 1 GHz, PLL Off
–90
–160
100
1k
FREQUENCY OFFSET (Hz)
Figure 3. Additive Phase Noise (Output Driver = LVPECL),
fREF = 19.44 MHz, fO = 155.52 MHz,
LBW = 1 kHz, fSYSCLK = 1 GHz, PLL Off
–70
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 103fs (–74.0dBc)
20kHz TO 80MHz: 160fs (–70.1dBc)
–80
08300-066
–80
–70
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 173fs (–75.4dBc)
20kHz TO 80MHz: 315fs (–70.2dBc) (EXTRAPOLATED)
Figure 4. Additive Phase Noise (Output Driver = LVPECL),
fREF = 19.44 MHz, fO = 155.52 MHz,
LBW = 1 kHz, fSYSCLK = 50 MHz (Crystal), PLL On
–160
100
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
Figure 6. Additive Phase Noise (Output Driver = LVPECL),
fREF = 19.44 MHz, fO = 311.04 MHz,
LBW = 1 kHz, fSYSCLK = 50 MHz (Crystal), PLL On
Rev. 0 | Page 18 of 104
08300-067
–70
AD9547
–70
–80
–70
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 361fs (–69.0dBc)
20kHz TO 80MHz: 441fs (–67.3dBc) (EXTRAPOLATED)
–80
50MHz CRYSTAL
–100
–110
–120
–130
–120
–130
–140
–150
–150
–160
100
–160
100
1k
10k
100k
1M
10M
100M
ROHDE & SCHWARZ
SMA100 (1GHz)
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
Figure 10. Additive Phase Noise Comparison of SYSCLK Input Options
(Output Driver = LVPECL),
fREF = 19.44 MHz, fO = 311.04 MHz, LBW = 1 kHz
Figure 7. Additive Phase Noise (Output Driver = LVPECL),
fREF = 19.44 MHz, fO = 155.52 MHz,
LBW = 1 kHz, fSYSCLK = 50 MHz, PLL On
–70
–70
INTEGRATED RMS JITTER (PHASE NOISE):
12kHz TO 20MHz: 245fs (–65.0dBc)
20kHz TO 80MHz: 300fs (–64.3dBc)
–80
INTEGRATED RMS JITTER (PHASE NOISE):
5kHz TO 20MHz: 336fs (–69.7dBc)
20kHz TO 80MHz: 425fs (–67.6dBc)
–80
–90
–100
–110
–120
–130
–100
–110
–120
–130
–140
–140
–150
–150
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
–160
100
08300-051
1k
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET (Hz)
08300-052
PHASE NOISE (dBc/Hz)
–90
–160
100
ROHDE & SCHWARZ
SMA100 (50MHz)
–110
–140
FREQUENCY OFFSET (Hz)
PHASE NOISE (dBc/Hz)
–100
08300-058
PHASE NOISE (dBc/Hz)
–90
08300-069
PHASE NOISE (dBc/Hz)
–90
Figure 11. Additive Phase Noise (Output Driver = LVPECL),
fREF = 8 kHz, fO = 155.52 MHz,
LBW = 100 Hz, fSYSCLK = 50 MHz (Crystal), PLL On
Figure 8. Additive Phase Noise (Output Driver = LVPECL),
fREF = 19.44 MHz, fO = 155.52 MHz,
LBW = 1 kHz, fSYSCLK = 50 MHz (Crystal), PLL On with
2× Frequency Multiplier, ICP = 375 μA, LF = External (350 kHz)
–90
10
–100
0
–110
–10
CLOSED-LOOP GAIN (dB)
–120
–130
ROHDE & SCHWARZ
SMA100 (1GHz)
–140
20MHz OCXO
–150
–30
–40
–50
ROHDE & SCHWARZ
SMA100 (50MHz)
1k
10k
100k
1M
FREQUENCY OFFSET (Hz)
10M
Figure 9. Phase Noise of SYSCLK Input Sources
–70
10
100
1k
10k
100k
FREQUENCY OFFSET (Hz)
Figure 12. Jitter Transfer Bandwidth, Output Driver = LVPECL,
fREF = 19.44 MHz, fO = 155.52 MHz,
LBW = 100 Hz (Phase Margin = 88°), fSYSCLK = 1 GHz, PLL Off
Rev. 0 | Page 19 of 104
08300-047
–170
100
–20
–60
–160
08300-053
PHASE NOISE (dBc/Hz)
CLOSED-LOOP PEAKING: 0.04dB
AD9547
2.0
1.0
5pF LOAD
0.8
AMPLITUDE (V)
AMPLITUDE (V)
LVPECL
0.6
0.4
LVDS
1.5
20pF LOAD
1.0
10pF LOAD
0.2
300
400
500
600
700
FREQUENCY (MHz)
0
50
100
200
250
50
200
FREQUENCY (MHz)
Figure 13. Amplitude vs. Toggle Rate,
LVPECL and LVDS
Figure 16. Amplitude vs. Toggle Rate,
1.8 V CMOS
4.0
4.0
3.5
3.5
10pF LOAD
5pF LOAD
3.0
AMPLITUDE (V)
AMPLITUDE (V)
150
08300-062
200
08300-063
100
08300-049
0
08300-061
0.5
0
2.5
20pF LOAD
2.0
3.0
10pF LOAD
2.5
2.0
1.5
1.5
1.0
1.0
100
200
300
400
500
FREQUENCY (MHz)
0
08300-055
0
10
20
30
40
FREQUENCY (MHz)
Figure 17. Amplitude vs. Toggle Rate,
3.3 V CMOS (Weak Mode)
Figure 14. Amplitude vs. Toggle Rate,
3.3 V CMOS (Strong Mode)
40
140
130
20pF LOAD
35
120
10pF LOAD
POWER (mW)
LVPECL
100
90
5pF LOAD
30
25
80
LVDS
70
20
60
15
50
0
100
200
300
400
FREQUENCY (MHz)
500
08300-064
POWER (mW)
110
0
50
100
150
FREQUENCY (MHz)
Figure 18. Power Consumption vs. Frequency,
1.8 V CMOS
Figure 15. Power Consumption vs. Frequency,
LVPECL and LVDS
(Single Channel)
Rev. 0 | Page 20 of 104
AD9547
160
34
140
32
30
10pF LOAD
100
5pF LOAD
10pF LOAD
80
28
20pF LOAD
60
24
40
22
0
50
100
150
200
250
300
350
FREQUENCY (MHz)
20
10
08300-060
20
15
20
25
30
35
40
FREQUENCY (MHz)
Figure 19. Power Consumption vs. Frequency,
3.3 V CMOS (Strong Mode)
Figure 22. Power Consumption vs. Frequency,
3.3 V CMOS (Weak Mode)
1.0
0.5
0.8
0.4
0.6
0.3
DIFFERENTIAL AMPLITUDE (V)
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–1.0
1
2
3
4
5
TIME (ns)
–0.5
08300-050
0
0
1
2
3
4
5
TIME (ns)
Figure 20. Output Waveform,
LVPECL (400 MHz)
08300-048
DIFFERENTIAL AMPLITUDE (V)
5pF LOAD
26
08300-059
20pF LOAD
POWER (mW)
POWER (mW)
120
Figure 23. Output Waveform,
LVDS (400 MHz)
3.5
3.5
10pF LOAD
5pF LOAD
3.0
3.0
20pF LOAD
2.5
AMPLITUDE (V)
2.0
1.5
1.0
2.0
20 pF LOAD
1.5
1.0
0.5
0.5
0
0
0
2
4
6
8
10
12
TIME (ns)
14
16
0
10
20
30
40
50
60
TIME (ns)
Figure 24. Output Waveform,
3.3 V CMOS (20 MHz, Weak Mode)
Figure 21. Output Waveform,
3.3 V CMOS (100 MHz, Strong Mode)
Rev. 0 | Page 21 of 104
70
80
08300-046
–0.5
–0.5
08300-057
AMPLITUDE (V)
2.5
AD9547
2.0
10pF LOAD
1.5
1.0
0.5
0
–0.5
0
2
4
6
8
10
TIME (ns)
12
14
16
08300-065
AMPLITUDE (V)
20pF LOAD
Figure 25. Output Waveform,
1.8 V CMOS (100 MHz)
Rev. 0 | Page 22 of 104
AD9547
INPUT/OUTPUT TERMINATION RECOMMENDATIONS
0.1µF
DOWNSTREAM
DEVICE
100Ω
100Ω
HIGH
IMPEDANCE
INPUT
0.1µF
AD9547
SELF-BIASED
SYSCLKx
INPUT
08300-006
08300-003
0.1µF
(OPTIONAL)
AD9547
3.3V LVDS
OUTPUT
0.1µF
Figure 26. AC-Coupled LVDS or LVPECL Output Driver
Figure 29. SYSCLKx Input
AD9547
100Ω
DOWNSTREAM
DEVICE
100Ω
3.3V
LVPECLCOMPATIBLE
OUTPUT
AD9547
SELF-BIASED
CLKINx
INPUT
08300-007
08300-004
0.1µF
(OPTIONAL)
0.1µF
Figure 27. DC-Coupled LVDS or LVPECL Output Driver
Figure 30. CLKINx Input
AD9547
SELF-BIASED
REFERENCE
INPUT
08300-005
0.1µF
(OPTIONAL)
100Ω
0.1µF
Figure 28. Reference Input
Rev. 0 | Page 23 of 104
AD9547
GETTING STARTED
POWER-ON RESET
The AD9547 monitors the voltage on the power supplies at powerup. When DVDD3 is greater than 2.35 V ± 0.1 V and DVDD
(Pin 1, Pin 6, Pin 8, Pin 53, Pin 59, and Pin 64) is greater than
1.4 V ± 0.05 V, the device generates a 75 ns reset pulse. The
power-up reset pulse is internal and independent of the RESET
pin. This internal power-up reset sequence eliminates the need for
the user to provide external power supply sequencing. Within 45 ns
after the leading edge of the internal reset pulse, the M0 to M7
multifunction pins function as high impedance digital inputs
and continue to do so until programmed otherwise.
INITIAL M0 TO M7 PIN PROGRAMMING
During a device reset (either via the power-up reset pulse or the
RESET pin), the multifunction pins (M0 to M7) function as
high impedance inputs, but upon removal of the reset condition,
level-sensitive latches capture the logic pattern present on the
multifunction pins. The AD9547 requires that the user supply
the desired logic state to the M0 to M7 pins by means of pull-up
and/or pull-down resistors (nominally 10 kΩ to 30 kΩ).
The initial state of the M0 to M7 pins following a reset is referred
to as FncInit, Bits[7:0]. Bits[7:0] of FncInit map directly to the
logic states of M[7:0], respectively. The three LSBs of FncInit
(FncInit, Bits[2:0]) determine whether the serial port interface
functions according to the SPI or the I2C protocol. Specifically,
FncInit, Bits[2:0] = 000 selects the SPI interface. Any other value
selects the I2C port, with the three LSBs of the I2C bus address
set to the value of FncInit, Bits[2:0].
The five MSBs of FncInit (FncInit, Bits[7:3]) determine the operation of the EEPROM loader. On the falling edge of RESET, if
FncInit, Bits[7:3] = 00000, then the EEPROM contents are not
transferred to the control registers and the device registers assume
their default values. However, if FncInit, Bits[7:3] ≠ 00000, then
the EEPROM controller transfers the contents of the EEPROM
to the control registers with CONDITION = FncInit, Bits[7:3]
(see the EEPROM section).
DEVICE REGISTER PROGRAMMING
Initialize the system clock.
After the system clock functionality is programmed, issue an I/O
update using Register 0x0005, Bit 0 to invoke the system clock
settings.
3.
Calibrate the system clock (only if using SYSCLK PLL).
Set the calibrate system clock bit in the cal/sync register
(Address 0x0A02, Bit 0) and issue an I/O update. Then clear the
calibrate system clock bit and issue another I/O update. This
action allows time for the calibration to proceed while programming the remaining device registers.
4.
Program the multifunction pins (optional).
This step is required only if the user intends to use any of the
multifunction pins for status or control. The multifunction pin
parameters reside in the 0x0200 register address space. The
default configuration of the multifunction pins is as undesignated
high impedance input pins.
5.
Program the IRQ functionality (optional).
This step is required only if the user intends to use the IRQ feature.
IRQ control resides in the 0x0200 register address space. It includes
the following:
•
•
IRQ pin mode control
IRQ mask
The IRQ mask default values prevent interrupts from being
generated. The IRQ pin mode default is open-drain NMOS.
6.
Program the watchdog timer (optional).
This step is required only if the user intends to use the watchdog
timer. Watchdog timer control resides in the 0x0200 register
address space. The watchdog timer is disabled by default.
Program the DAC full-scale current (optional).
This step is required only if the user intends to use a full-scale
current setting other than the default value. DAC full-scale
current control resides in the 0x0200 register address space.
8.
Program the digital phase-locked loop (DPLL).
The DPLL parameters reside in the 0x0300 register address
space. They include the following:
Program the system clock functionality.
The system clock parameters reside in the 0x100 register
address space. They include the following:
•
•
•
2.
7.
The initial state of the M0 to M7 pins establishes the serial I/O
port protocol (SPI or I2C). Using the appropriate serial port protocol, and assuming that an EEPROM download is not used,
program the device according to the recommended sequence
that follows.
1.
mended that the system clock stability timer be programmed, as
well. This is especially important when using the system clock PLL
but also applies if using an external system clock source, especially
if the external source is not expected to be completely stable when
power is applied to the AD9547.
System clock PLL controls
System clock period
System clock stability timer
It is essential to program the system clock period because many
of the AD9547 subsystems rely on this value. It is highly recom-
•
•
•
•
•
•
Rev. 0 | Page 24 of 104
Free-run frequency (DDS frequency tuning word)
DDS phase offset
DPLL pull-in range limits
DPLL closed-loop phase offset
Phase slew control (for hitless reference switching)
Tuning word history control (for holdover operation)
AD9547
9.
Program the clock distribution outputs.
12. Generate reference acquisition.
The clock distribution parameters reside in the 0x0400 register
address space. They include the following:
•
•
•
•
•
•
Output power-down control
Output enable (disabled by default)
Output synchronization
Output mode control
Output divider functionality
Program the reference inputs.
10. The reference input parameters reside in the 0x0500
register address space. They include the following:
•
•
•
•
Reference power-down
Reference logic family
Reference profile assignment control
Phase build-out control
11. Program the reference profiles.
The reference profile parameters reside in the 0x0600 and
0x0700 register address spaces. They include the following:
•
•
•
•
•
•
•
•
•
Reference priority
Reference period
Reference period tolerance
Reference validation timer
Reference redetect timer
Digital loop filter coefficients
Reference prescaler (R divider)
Feedback dividers (S, U, and V)
Phase and frequency lock detector controls
After the registers are programmed, issue an I/O update using
Register 0x0005, Bit 0 to invoke all of the register settings that have
been programmed up to this point.
If the settings are programmed for manual profile assignment,
the DPLL locks to the first available reference that has the highest
priority. If the settings are programmed for automatic profile
assignment, then write to the reference profile selection register
(Address 0x0A0D) to select the state machines that require starting.
Next, issue an I/O update (Address 0x0005, Bit 0) to start the
selected state machines. Upon completion of the reference
detection sequence, the DPLL locks to the first available
reference with the highest priority.
13. Generate the output clock.
If the registers are programmed for automatic clock distribution
synchronization via DPLL phase or frequency lock, the synthesized
output signal appears at the clock distribution outputs (assuming
that the output is enabled and the DDS output signal has been
routed to the CLKINx input pins). Otherwise, set and then clear
the sync distribution bit (Address 0x0A02, Bit 1) or use a multifunction pin input (if programmed accordingly) to generate
a clock distribution sync pulse, which causes the synthesized
output signal to appear at the clock distribution outputs.
Rev. 0 | Page 25 of 104
AD9547
THEORY OF OPERATION
AD9547
OUT_RSET
DIFFERENTIAL
OR
SINGLE-ENDED
REFA
POST
DIV
OUT0P
OUT0N
POST
DIV
OUT1P
OUT1N
REFAA
REFB
REFBB
DIGITAL PLL CORE
÷S
CLKINP
TDC/PFD
2 OR 4
÷R
PROG.
DIGITAL
LOOP
FILTER
TW CLAMP
AND
HISTORY
CLKINN
DDS/DAC
EXTERNAL
ANALOG
FILTER
HOLDOVER
LOGIC
PHASE
CONTROLLER
INPUT
REF
MONITOR
M0 TO M7
IRQ
IRQ AND
STATUS
LOGIC
CLOCK
DISTRIBUTION
LOW NOISE
CLOCK
MULTIPLIER
CONTROL
LOGIC
AMP
DIGITAL
INTERFACE
SYSCLKN SYSCLKP
08300-009
SYSCLK PORT
Figure 31. Detailed Block Diagram
OVERVIEW
The AD9547 provides clocking outputs that are directly related
in phase and frequency to the selected (active) reference but with
jitter characteristics primarily governed by the system clock. The
AD9547 supports up to four reference inputs and a wide range of
reference frequencies. The core of this product is a digital phaselocked loop (DPLL). The DPLL has a programmable digital loop
filter that greatly reduces jitter transferred from the active
reference to the output. The AD9547 supports both manual and
automatic holdover modes. While in holdover mode, the AD9547
continues to provide an output as long as the DAC sample clock
is present. The holdover output frequency is a time average of
the output frequency history just prior to the transition to the
holdover condition.
The device offers manual and automatic reference switchover
capability if the active reference is degraded or fails completely.
A direct digital synthesizer (DDS) and integrated DAC constitute
a digitally controlled oscillator (DCO). The DCO output is
a sinusoidal signal (450 MHz maximum) at a frequency that is
determined by the active reference frequency and the programmed
values of the reference prescaler (R) and feedback divider (S).
Although not explicitly shown in Figure 31, the S divider has
both an integer and fractional component, which is similar to
a fractional-N synthesizer.
The SYSCLKx input provides the sample clock for the DAC, which
is either a directly applied high frequency source or a low frequency
source coupled with the integrated PLL-based frequency multiplier.
The low frequency option also allows for the use of a crystal
resonator connected directly across the SYSCLKx inputs.
The DAC output routes directly off chip where an external filter
removes the sampling artifacts before returning the signal on chip
at the CLKINx inputs. Once on chip, an integrated comparator
converts the filtered sinusoidal signal to a clock signal (square
wave) with very fast rise and fall times.
The clock distribution section provides two output drivers. Each
driver is programmable either as a single differential LVPECL/
LVDS output or as a dual single-ended CMOS output. Furthermore, a dedicated 30-bit programmable divider precedes each
driver. The clock distribution section operates at up to 725 MHz.
This enables use of a band-pass reconstruction filter (for example,
a SAW filter) to extract a Nyquist image from the DAC output
spectrum, thereby allowing output frequencies that exceed the
typical 450 MHz limit at the DAC output.
Rev. 0 | Page 26 of 104
AD9547
REFERENCE CLOCK INPUTS
Two pairs of pins provide access to the reference clock receivers.
Each pair is configurable either as a single differential receiver
or as two independent single-ended receivers. To accommodate
input signals with slow rising and falling edges, both the differential
and single-ended input receivers employ hysteresis. Hysteresis also
ensures that a disconnected or floating input does not cause the
receiver to oscillate spontaneously.
When configured for differential operation, the input receivers
accommodate either ac- or dc-coupled input signals. The receiver
is internally dc biased to handle ac-coupled operation.
When configured for single-ended operation, the input receivers
exhibit a pull-down load of 45 kΩ (typical). Three user-programmable threshold voltage ranges are available for each single-ended
receiver.
REFERENCE MONITORS
The reference monitors depend on a known and accurate system
clock period. Therefore, the functioning of the reference monitors
is not reliable until the system clock is stable. To avoid an incorrect
valid indication, the reference monitors indicate fault status until
the system clock stability timer expires (see the System Clock
Stability Timer section).
Reference Period Monitor
Each reference input has a dedicated monitor that repeatedly
measures the reference period. The AD9547 uses the reference
period measurements to determine the validity of the reference
based on a set of user provided parameters in the profile register
area of the register map (see the Profile Registers (Register 0x0600
to Register 0x07FF) section). The AD9547 also uses the reference
period monitor to assign a particular reference to a profile when
the user programs the device for automatic profile assignment.
The monitor works by comparing the measured period of a particular reference input against the parameters stored in the profile
register assigned to that same reference input. The parameters
include the reference period, an inner tolerance, and an outer
tolerance. A 40-bit number defines the reference period in units
of femtoseconds (fs). The 40-bit range allows for a reference period
entry of up to 1.1 ms (909 Hz). A 20-bit number defines the inner
and outer tolerances. The value stored in the register is the reciprocal of the tolerance specification. For example, a tolerance
specification of 50 ppm yields a register value of 1/(50 ppm) =
1/0.000050 = 20,000 (0x04E20).
The use of two tolerance values provides hysteresis for the monitor
decision logic. The inner tolerance applies to a previously faulted
reference and specifies the largest period tolerance that a previously
faulted reference can exhibit before it qualifies as nonfaulted.
The outer tolerance applies to an already nonfaulted reference and
specifies the largest period tolerance that a nonfaulted reference
can exhibit before being faulted.
To produce decision hysteresis, the inner tolerance must be less
than the outer tolerance. That is, a faulted reference must meet
tighter requirements to become nonfaulted than a nonfaulted
reference must meet to become faulted.
Reference Validation Timer
Each reference input has a dedicated validation timer. The
validation timer establishes the amount of time that a previously
faulted reference must remain fault free before the AD9547
declares it to be nonfaulted. The timeout period of the validation
timer is programmable via a 16-bit register (see the validation
register contained within each of the eight profile registers in
the register map, Address 0x0600 to Address 0x07FF). The
16-bit number stored in the validation register represents units
of milliseconds, which yields a maximum timeout period of
65,535 ms.
Note that a validation period of zero must be programmed to
disable the validation timer. With the validation timer disabled,
the user must validate a reference manually via the force validation timeout register (Address 0x0A0E).
Reference Redetect Timer
Each reference input has a dedicated redetect timer. The redetect
timer is useful only when the device is programmed for automatic
profile selection. The redetect timer establishes the amount of
time that a reference must remain faulted before the AD9547
attempts to reassign it to a new profile. The timeout period of
the redetect timer is programmable via a 16-bit register (see the
redetect timer register contained within each of the eight profile
registers in the register map, Address 0x0600 to Address 0x07FF).
The 16-bit number stored in the redetect timer register represents
units of milliseconds, which yields a maximum timeout period
of 65,535 ms.
Note that a timeout period of 0 must be programmed to disable the
redetect timer.
Rev. 0 | Page 27 of 104
AD9547
REGISTER CONTROL BITS
REFERENCE VALIDATION LOGIC
(4 COPIES, 1 PER REFERENCE INPUT)
D Q
VALID
FORCE VALIDATION
TIMEOUT
VALIDATION TIMER
REF MONITOR
BYPASS
REF MONITOR
OVERRIDE
R
1
EN
R
TIMEOUT
FAULTED
REFERENCE
MONITOR
08300-010
0
REF FAULT
Figure 32. Reference Validation Override
Reference Validation Override Control
Register 0x0A0E to Register 0x0A10 provide the user with the
ability to override the reference validation logic, enabling a
certain level of troubleshooting capability. Each of the four
input references has a dedicated block of validation logic, as
shown in Figure 32. The state of the valid signal at the output
defines a particular reference as valid (1) or not valid (0), which
includes the validation period (if activated) as prescribed by the
validation timer. The override controls are the three control bits
on the left side of the diagram.
The main feature to note is that when faulted = 1, the output latch
is reset, which forces valid = 0 (indicating an invalid reference),
regardless of the state of any other signal. Under the default condition (that is, all three control bits are set to 0), the reference
monitor is the primary source of the validation process. This is
because, under the default condition, the ref fault signal from the
reference monitor is identical to the faulted signal.
The function of the faulted signal is fourfold.
•
•
•
•
When faulted = 1, valid = 0, regardless of the state of any
other control signal. Therefore, faulted = 1 indicates an
invalid reference.
When the faulted signal transitions from 0 to 1 (that is, from
not faulted to faulted), the validation timer is momentarily
reset, which means that, when it is enabled, it must exhaust its
full counting sequence before it expires.
When faulted = 0 (that is, the reference is not faulted), the
validation timer is allowed to perform its timing sequence.
When faulted = 1 (that is, the reference is faulted), the
validation timer is reset and halted.
The faulted signal passes through an inverter, which converts
it to a not faulted signal that appears at the input of the valid
latch. This allows the valid latch to capture the state of the
not faulted signal when the validation timer expires.
The reference monitor bypass control bit (Address 0x0A10) enables
bypassing of the reference fault signal generated by the reference
monitor. When the reference monitor bypass bit = 1, the state of the
faulted signal is dictated by the reference monitor override control
bit. This is useful when the user relies on an external reference
monitor rather than the internal monitor resident in the device.
The user programs the reference monitor override bit based on
the status of the external monitor. On the other hand, when the
reference monitor bypass bit = 0, the reference monitor override
control bit (Address 0x0A0F) allows the user to manually test
the operation of both the valid latch and the validation timer.
In this case, the user relies on the signal generated by the internal
reference monitor (reference fault) but uses the reference monitor
override bit to emulate a faulted reference. That is, when the
reference monitor override bit = 1, faulted = 1, but when the
reference monitor override bit = 0, faulted = reference fault.
In addition, the user can emulate a timeout of the validation timer
via the force validation timeout control register at Address 0x0A0E.
Writing a Logic 1 to this autoclearing bit triggers the valid latch,
which is identically equivalent to a timeout of the validation timer.
REFERENCE PROFILES
The AD9547 has eight independent profile registers. A profile
register contains 50 bytes that establish a particular set of device
parameters. Each of the four input references can be assigned to
any one of the eight profiles (that is, more than one reference can
be assigned to the same profile). The profiles allow the user to
prescribe the specific device functionality that should take effect
when one of the input references assigned to a profile becomes the
active reference. Each profile register has the same format and
stores the following device parameters:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Rev. 0 | Page 28 of 104
Reference priority
Reference period value (in femtoseconds (fs))
Inner tolerance value (1/tolerance)
Outer tolerance value (1/tolerance)
Validation timer value (milliseconds (ms))
Redetect timer value (milliseconds (ms))
Digital loop filter coefficients
Reference prescaler setting (R divider)
Feedback divider settings (S, U, and V)
DPLL phase lock detector threshold level
DPLL phase lock detector fill rate
DPLL phase lock detector drain rate
DPLL frequency lock detector threshold level
DPLL frequency lock detector fill rate
DPLL frequency lock detector drain rate
AD9547
Reference-to-Profile Assignment Control
The user can manually assign a reference to a profile or let the
device make the assignment automatically. The manual reference
profile selection register (Address 0x0503 and Address 0x0504)
is used to program whether a reference-to-profile assignment is
manual or automatic. The manual reference profile selection register is a 2-byte register partitioned into four half bytes (or nibbles).
The four nibbles form a one-to-one correspondence with the four
reference inputs: one nibble for REF A, the next for REF AA, and
so on. For a reference configured as a differential input, however,
the device ignores the nibble associated with the two-letter input.
For example, if the B reference is differential, only the REF B nibble
matters (the device ignores the REF BB nibble).
The MSB of each nibble is the manual profile bit, whereas the
three LSBs of each nibble identify one of the eight profiles (0 to 7).
A Logic 1 for the manual profile bit assigns the associated reference to the profile identified by the three LSBs of the nibble.
A Logic 0 for the manual profile bit configures the associated
reference for automatic reference-to-profile assignment (the
three LSBs are ignored in this case). Note that references
configured for automatic reference-to-profile assignment
require activation (see the Reference-to-Profile Assignment
State Machine section).
Reference-to-Profile Assignment State Machine
The functional flexibility of the AD9547 resides in the way that
it assigns a particular input reference to one of the eight reference
profiles. The reference-to-profile assignment state machine effectively builds a reference-to-profile table that maps the index of
each input reference to a profile (see Table 22).
Table 22. Reference-to-Profile Table
Reference Input
A
Reference Index
0
Profile
Profile # (or null)
AA
1
Profile # (or null)
B
2
Profile # (or null)
BB
3
Profile # (or null)
Each entry in the profile column consists of a profile number
(0 to 7) or a null value. A null value appears when a referenceto-profile assignment does not exist for a particular reference
input (following a reset, for example). The information in Table 22
appears in the register map (Register 0x0D0C to Register 0x0D0F)
so that the user has access to the reference-to-profile assignments
on a real-time basis. Register 0x0D0C contains the information for
REF A, Register 0x0D0D contains the information for REF AA,
Register 0x0D0E for REF B, and Register 0x0D0F for REF BB. Bit 7
of each register is the null indicator for that particular reference.
If Bit 7 = 0, the pro-file assignment for that particular reference is
null. If Bit 7 = 1, that particular reference is assigned to the profile
(0 to 7) identified by Bits[6:4]. Note that Bits[6:4] are meaningless unless Bit 7 = 1.
Following a reset, the reference-to-profile assignment state machine
is inactive to avoid improperly assigning a reference to a profile
before the system clock stabilizes. The state machine relies on
accurate information from the reference monitors, which, in turn,
rely on a stable system clock. Because the reference-to-profile
assignment state machine is inactive at power-up, the user must
initiate it manually by writing to the reference profile selection
register (Address 0x0A0D). The state machine activates immediately, unless the system clock is not stabilized. In that case,
activation occurs upon expiration of the system clock stability
timer. Note that initialization of the state machine is on a perreference basis. That is, each reference input is associated with an
independent initialization control bit.
When initialized for processing a reference, the state machine
continuously monitors that reference until the occurrence of a
device reset. This is true even when the user programs a reference
for manual profile selection, in which case the state machine
associated with that particular reference operates with its activity
masked. The masked background activity allows for seamless
operation if the user subsequently reprograms the reference for
automatic profile selection.
Reference-to-Profile Assignment
When a reference is programmed for manual profile assignment
(see Register 0x0503 to Register 0x0504), the reference-to-profile
assignment state machine puts the programmed manual profile
number into the profile column of the reference-to-profile table
(see Table 22) in the row associated with the appropriate reference.
However, when the user programs a reference for automatic profile
assignment, the state machine must determine which profile to
assign to the reference, as explained in the following paragraphs.
If a null entry appears in the reference-to-profile table for a particular input reference, the validation logic for that reference enters
a period estimation mode. Note that a null entry is the default
state following a reset, but it also occurs when a reference redetect
timer expires. The period estimation mode enables the validation
logic to make a blind estimate of the period of the input reference
with a tolerance of 0.1%. The validation logic remains in the period
estimation mode until it successfully estimates the reference period.
Upon a successful reference period measurement by the validation logic, the state machine compares the measured period
to the nominal reference period programmed into each of the
eight profiles. The state machine assigns the reference to the
profile with the closest match to the measured period. If more
than one profile exactly matches the reference period, the state
machine chooses the profile with the lowest numeric index. For
example, if the reference period in both Profile 3 and Profile 5
matches the measured period, Profile 3 is given the assignment.
To safeguard against making a poor reference-to-profile assignment, the state machine ensures that the measured reference period
is within 6.25% of the nominal reference period that appears in
the closest match profile. Otherwise, the state machine does not
make a profile assignment and leaves the null entry in the reference-to-profile table.
Rev. 0 | Page 29 of 104
AD9547
As long as there are input references programmed for automatic
profile assignment, and for which the profile assignment is null,
the state machine continues to cycle through those references
searching for a profile match. Furthermore, unless an input
reference is assigned to a profile, it is considered invalid and
excluded as a candidate for a reference switchover.
REFERENCE SWITCHOVER
An attractive feature of the AD9547 is its versatile reference
switchover capability. The flexibility of the reference switchover
functionality resides in a sophisticated prioritization algorithm
coupled with register-based controls. This scheme provides the
user with maximum control over the state machine that handles
reference switchover.
The main reference switchover control resides in the loop mode
register (Address 0x0A01). The user selection mode bits (Bits[4:3])
allow the user to select one of the reference switchover state
machine’s four operating modes, as follows:
•
•
•
•
Automatic mode (Address 0x0A01, Bits[4:3] = 00)
Fallback mode (Address 0x0A01, Bits[4:3] = 01)
Holdover mode (Address 0x0A01, Bits[4:3] = 10)
Manual mode (Address 0x0A01, Bits[4:3] = 11)
In automatic mode, a fully automatic, priority-based algorithm
selects the active reference. When programmed for automatic
mode, the device ignores the user reference selection bits (Register
0x0A01, Bits[1:0]). However, when programmed for any of the
other three modes, the device uses the user reference bits. They
specify a particular input reference (00 = REF A, 01 = REF AA ,
10 = REF B, 11 = REF BB).
In fallback mode, the user reference is the active reference when
it is valid. Otherwise, the device switches to a new reference using
the automatic priority-based algorithm.
In holdover mode, the user reference is the active reference when
it is valid. Otherwise, the device switches to holdover mode.
In manual mode, the user reference is the active reference whether
it is valid or not. Note that, when using this mode, the user must
program the reference-to-profile assignment (see Register 0x0503
and Register 0x0504) as manual for the particular reference that
is declared as the user reference. The reason is that if the user reference fails and its redetect timer expires, its profile assignment
(shown in Table 22) becomes null. This means that the active
reference (user reference) does not have an assigned profile, which
places the AD9547 into an undefined state.
The user also has the option to force the device directly into
holdover or free-run operation via the user holdover and user
free-run bits (Register 0x0A01, Bits[6:5]). In free-run mode, the
free-running frequency tuning word register (Address 0x0300
to Address 0x0305) defines the DDS output frequency.
Automatic Priority-Based Reference Switchover
The AD9547 has a two-tiered, automatic, priority-based algorithm
that is in effect for both automatic and fallback reference switchover. The algorithm relies on the fact that each reference profile
contains both a selection priority and a promoted priority. The
selection and promoted priority values range from 0 (highest
priority) to 7 (lowest priority). The selection priority determines
the order in which references are chosen as the active reference.
The promoted priority is a separate priority value given to a
reference only after it becomes the active reference.
An automatic reference switchover occurs on failure of the active
reference or when a previously failed reference becomes valid
and its selection priority is higher than the promoted priority
of the currently active reference (assuming that the automatic or
fallback reference switchover is in effect). When performing an
automatic reference switchover, the AD9547 chooses a reference
based on the priority settings within the profiles. That is, the device
switches to the reference with the highest selection priority (lowest
numeric priority value). It does so by using the reference-to-profile
table (see Table 22) to determine the reference associated with
the profile exhibiting the highest priority.
If multiple references share the same profile, the device chooses
the reference having the lowest index value. For example, if the
A, B, and BB references (Index 0, Index 2, and Index 3, respectively)
share the same profile, a switchover to Reference A occurs because
Reference A has the lowest index value. Note, however, that only
valid references are included in switchover of the selection process.
The switchover control logic ignores any reference with a status
indication of invalid.
The promoted priority parameter allows the user to assign a higher
priority to a reference after it becomes the active reference. For
example, suppose that two references have a selection priority of 3
and a promoted priority of 1, and the remaining references have
a selection priority of 2 and a promoted priority of 2. Now, assume
that one of the Priority 3 references becomes active because all
of the Priority 2 references have failed. Sometime later, however,
a Priority 2 reference becomes valid. The switchover logic normally
attempts to automatically switch over to the Priority 2 reference
because it has higher priority than the presently active Priority 3
reference. However, because the Priority 3 reference is active, its
promoted priority of 1 is in effect. This is a higher priority than
the newly validated reference’s priority of 2, so the switchover does
not occur. This mechanism enables the user to give references
preferential treatment while they are selected as the active reference. An example of promoted vs. nonpromoted priority switching
appears in state diagram form in Figure 33. Figure 34 shows a block
diagram of the interrelationship between the reference inputs,
monitors, validation logic, profile selection, and priority selection
functionality.
In holdover mode, the DDS output frequency depends on the
holdover control settings (see the Holdover section).
Rev. 0 | Page 30 of 104
AD9547
A
ACTIVE
A VALID
PRIORITY TABLE
INPUT
PRIORITY
PROMOTED
A
0
0
AA
1
0
B
2
1
BB
3
2
A FAULTED
AA
ACTIVE
AA VALID
COMMON
WITHOUT PROMOTION
WITH PROMOTION
A VALID
AA FAULTED
B
ACTIVE
AA VALID
08300-011
ALL VALID
INITIAL
STATE
Figure 33. Example of Priority Promotion
PROFILE
SELECTION
VALIDATION
LOGIC
PRIORITY
SELECTION
LOOP
CONTROLLER
… …
MONITORS
÷R
TDC
08300-012
…
REF A/REF AA
REF B/REF BB
Figure 34. Reference Clock Block Diagram
Phase Build-Out Reference Switching
Phase build-out reference switching is the term given to a reference switchover that completely masks any phase difference
between the previous reference and the new reference. That is,
there is virtually no phase change that can be detected at the
output when a phase build-out switchover occurs.
The AD9547 handles phase build-out switching based on whether
the new reference is a phase master. A phase master is any reference
with a selection priority value that is less than the phase master
threshold priority value (that is, higher priority). The phase master
threshold priority value resides in the phase build-out switching
register (Address 0x0507), and the selection priority resides in the
profile registers (Address 0x0600 to Address 0x07FF). By default,
the phase master threshold priority is 0; therefore, no references
can be phase masters until the user changes the phase master
threshold priority.
When the AD9547 switches from one reference to another, it
compares the selection priority value that is stored in the profile
that is assigned to the new reference with the phase master
threshold priority. The AD9547 performs a phase build-out
switchover only if the new reference is not a phase master.
Hitless Reference Switching (Phase Slew Control)
Hitless reference switching is the term given to a reference switchover that limits the rate of change of the phase of the output clock
while the PLL is in the process of acquiring phase lock. This
prevents the output frequency offset from becoming excessive.
The all-digital nature of the DPLL core (see the Digital PhaseLocked Loop (DPLL) Core section) gives the user numerical
control of the rate at which phase changes occur at the DPLL
output. When enabled, a phase slew controller monitors the
phase difference between the feedback and reference inputs to the
DPLL. The phase slew controller can place a user-specified limit on
the rate of change of phase, thus providing a mechanism for
hitless reference switching.
The user sets a limit on the rate of change of phase by storing
the appropriate value in the 16-bit phase slew rate limit register
(Address 0x0316 and Address 0x0317). The 16-bit word, which
represents units of ns/sec, puts an upper bound on the rate of
change of the phase at the output of the DPLL during a reference
switchover. A phase slew rate value of 0 (default) disables the
phase slew controller.
The accuracy of the phase slew controller depends on both the
phase slew limit value and the system clock frequency. Generally,
an increase in the phase slew rate limit value or a decrease in
the system clock frequency tends to reduce the error. Therefore,
the accuracy is best for the largest phase slew rate limit value and
the lowest system clock frequency. For example, assuming the
use of a 1 GHz system clock, a phase slew rate limit value of
315 ns/sec (or more) ensures an error of <10%, whereas a phase
slew rate limit value above ~3100 ns/sec ensures an error of <1%.
On the other hand, assuming the use of a 500 MHz system clock,
the same phase slew rate limit values ensure an error of <5% or
0.5%, respectively.
Rev. 0 | Page 31 of 104
AD9547
DPLL Overview
A diagram of the digital PLL core of the AD9547 appears in
Figure 35. The phase/frequency detector, feedback path, lock
detectors, phase offset, and phase slew rate limiting that make
up this second-generation DPLL are all digital implementations.
LOCK
DETECT
PHASE SLEW
LIMIT
f DDS =
DPPL CORE
CLOSED-LOOP
PHASE OFFSET
REF A
R+1
REF BB
fTDC
TDC
AND
PFD
DIGITAL
LOOP
FILTER
DDS/ fDDS
DAC
2
S + 1 + U/V
DACOUT
08300-013
fREF
Figure 35. Digital PLL Core
The start of the DPLL signal chain is the reference signal, fREF,
which is the frequency of the reference input. A reference
prescaler reduces the frequency of this signal by an integer
factor, R + 1, where R is the 30-bit value stored in the profile
register and 0 ≤ R ≤ 1,073,741,823. Therefore, the frequency at
the output of the R divider (or the input to the time-to-digital
converter (TDC)) is
f TDC =
f REF
R +1
The TDC samples the output of the R divider. The TDC/PFD
produces a time series of digital words and delivers them to the
digital loop filter. The digital loop filter offers the following
advantages:
•
•
•
•
The DPLL includes a feedback divider that causes the DDS to
operate at an integer-plus-fractional multiple (S + 1 + U/V) of
fTDC. S is the 20-bit value stored in the profile register and has a
range of 7 ≤ S ≤ 1,048,576. U and V are the 10-bit numerator
and denominator values of the optional fractional divide
component, also stored in the profile register. Together they
establish the nominal DDS frequency (fDDS), given by
Normally, fractional-N designs exhibit distinctive phase noise
and spurious artifacts resulting from the modulation of the
integer divider based on the fractional value. This is not the
case for the AD9547 because it uses a purely digital means to
determine phase errors. Because the phase errors incurred by
modulating the feedback divider are deterministic, it is possible
to compensate for them digitally. The result is a fractional-N
PLL with no discernible modulation artifacts.
Time-to-Digital Converter (TDC)/Phase Frequency
Detector (PFD)
The TDC is a highly integrated functional block that incorporates
both analog and digital circuitry. There are two pins associated
with the TDC that the user must connect to external components.
Figure 36 shows the recommended component values and their
connections.
For best performance, place components as close as possible to
the device pins. Components with low effective series resistance
(ESR) and low parasitic inductance yield the best results.
AD9547
Determination of the filter response by numeric
coefficients rather than by discrete component values
Absence of analog components (R/L/C), which eliminates
tolerance variations due to aging
Absence of thermal noise associated with analog
components
Absence of control node leakage current associated with
analog components (a source of reference feed-through
spurs in the output spectrum of a traditional analog PLL)
The digital loop filter produces a time series of digital words
at its output and delivers them to the frequency tuning input of
a direct digital synthesizer (DDS), with the DDS replacing the
function of the VCO in an analog PLL. The digital words from
the loop filter tend to steer the DDS frequency toward frequency
and phase lock with the input signal (fTDC). The DDS provides
an analog output signal via an integrated DAC, effectively
mimicking the operation of an analog VCO.
f REF ⎛
U⎞
⎜S +1+ ⎟
R +1 ⎝
V⎠
41
40
TDC_VRB
TDC_VRT
0.1µF
10µF
0.1µF
0.1µF
08300-014
DIGITAL PHASE-LOCKED LOOP (DPLL) CORE
Figure 36. TDC Pin Connections
The PFD is an all-digital block. It compares the digital output
from the TDC (which relates to the active reference edge) with
the digital word from the feedback block (which relates to the
rollover edge of the DDS accumulator after division by the feedback divider). The PFD uses a digital code pump and digital
integrator (rather than a conventional charge pump and capacitor)
to generate the error signal that steers the DDS frequency toward
phase lock.
Rev. 0 | Page 32 of 104
AD9547
In addition, the user can adjust the closed-loop phase offset (positive or negative) in incremental fashion. To do so, program the
desired step size in the incremental phase lock offset step size
bits (Address 0x0314 and Address 0x0315). This is an unsigned
number that represents units of picoseconds (ps). The programmed step size is added to the current closed-loop phase offset each
time the user writes a Logic 1 to the increment phase offset bit
(Register 0x0A0C, Bit 0). Conversely, the programmed step size
is subtracted from the current closed-loop phase offset each time
the user writes a Logic 1 to the decrement phase offset bit
(Register 0x0A0C, Bit 1). The serial I/O port control logic clears
both of these bits automatically. The user can remove the incrementally accumulated phase by writing a Logic 1 to the reset
incremental phase offset bit (Register 0x0A0C, Bit 2), which is
also cleared automatically. Alternatively, rather than using the
serial I/O port, the multifunction pins can be set up to perform
the increment, decrement, and clear functions.
Note that the incremental phase offset is completely independent of
the offset programmed into the fixed phase lock offset register.
However, if the phase slew limiter is active (see the Hitless
Reference Switching (Phase Slew Control) section), any instantaneous change in closed-loop phase offset (fixed or incremental)
is subject to possible slew limitation by the action of the phase
slew limiter.
Programmable Digital Loop Filter
The AD9547 loop filter is a third-order digital IIR filter that is
analogous to the third-order analog loop shown in Figure 37.
C1
R2
C2
C3
08300-015
R3
Thus, the β, γ, and δ coefficients always represent values less than
unity. The α coefficient, however, has two additional exponential
components, but the hardware interprets these as a positive
exponent of two (that is, 2x). This allows the α coefficient to take
on values that are greater than unity. To provide sufficient dynamic
range, the positive exponent appears as two separate terms.
α
FRACTIONAL
(16-BIT)
α0
1/2x
(6-BIT)
α1
2x
(3-BIT)
α2
FRACTIONAL
(17-BIT)
α3
1/2x
2x
(4-BIT)
β
(6-BIT)
51
β1
σ
0
1
FRACTIONAL
(17-BIT)
σ0
FRACTIONAL
(15-BIT)
1/2x
σ1
1/2x
(5-BIT)
(6-BIT)
48
LOOP FILTER
(THIRD-ORDER IIR)
IN
OUT
Figure 38. Third-Order Digital IIR Loop Filter
DPLL Phase Lock Detector
The DPLL contains an all-digital phase lock detector. The user
controls the threshold sensitivity and hysteresis of the phase
lock detector via the profile registers.
The phase lock detector behaves in a manner that is analogous
to water in a tub (see Figure 39). The total capacity of the tub is
4096 units with −2048 denoting empty, 0 denoting the 50% point,
and +2048 denoting full. The tub also has a safeguard to prevent
overflow. Furthermore, the tub has a low water mark at −1024
and a high water mark at +1024. To change the water level, the
user adds water with a fill bucket or removes water with a drain
bucket. The user specifies the size of the fill and drain buckets via
the 8-bit fill rate and drain rate values in the profile registers.
The phase lock detector uses the water level in the tub to determine
the lock and unlock conditions. When the water level is below
the low water mark (−1024), the detector indicates an unlock
con-dition. Conversely, when the water level is above the high
water mark (+1024), the detector indicates a lock condition.
When the water level is between the marks, the detector holds its
last condition. This concept appears graphically in Figure 39, with
an overlay of an example of the instantaneous water level (vertical)
vs. time (horizontal) and the resulting lock/unlock states.
PREVIOUS
STATE
Figure 37. Third-Order Analog Loop Filter
The filter requires four coefficients, as shown in Figure 38. The
AD9547 evaluation board software automatically generates the
required loop filter coefficient values based on user design criteria. The Calculating the Digital Filter Coefficients section
contains the design equations for calculating the loop filter
coefficients manually.
β0
08300-016
The all-digital nature of the TDC/PFD provides for numerical
control of the phase offset between the reference and feedback
edges. This allows the user to adjust the relative timing of the
distribution output edges relative to the reference input edges by
programming the fixed phase lock offset bits (Address 0x030F to
Address 0x0313). The 40-bit word is a signed (twos complement)
number that represents units of picoseconds (ps).
LOCKED
UNLOCKED
2048
LOCK LEVEL
1024
Each coefficient has a fractional component representing a value
from 0 up to, but not including, unity. Each also has an exponential component representing a power of 2 with a negative
exponent. That is, the user enters a positive number (x) that the
hardware interprets as a negative exponent of two (2−x).
Rev. 0 | Page 33 of 104
0
–1024
FILL
RATE
DRAIN
RATE
UNLOCK LEVEL
–2048
Figure 39. Phase Lock Detector Diagram
08300-017
Closed-Loop Phase Offset
AD9547
During any given PFD phase error sample, the detector either adds
water with the fill bucket or removes water with the drain bucket
(one or the other but not both). The decision on whether to add or
remove water depends on the threshold level specified by the user.
The phase lock threshold value is a 16-bit number stored in the
profile registers and carries units of picoseconds (ps). Thus, the
phase lock threshold extends from 0 ns to ±65.535 ns and represents the magnitude of the phase error at the output of the PFD.
It represents the magnitude of the difference in period between
the reference and feedback signals at the input to the DPLL. For
example, if the reference signal is 1.25 MHz and the feedback
signal is 1.38 MHz, the period difference is approximately 75.36 ns
(|1/1,250,000 − 1/1,380,000| ≈ 75.36 ns).
DIRECT DIGITAL SYNTHESIZER (DDS)
DDS Overview
One of the primary building blocks of the digital PLL is a direct
digital synthesizer (DDS). The DDS behaves like a sinusoidal
signal generator. The frequency of the sinusoid generated by the
DDS is determined by a frequency tuning word (FTW), which
is a digital (that is, numeric) value. Unlike an analog sinusoidal
generator, a DDS uses digital building blocks and operates as a
sampled system. Thus, it requires a sampling clock (fS) that serves
as the fundamental timing source of the DDS. The accumulator
behaves as a modulo-248 counter with a programmable step size
(FTW). A block diagram of the DDS appears in Figure 40.
The phase lock detector compares each phase error sample at the
output of the PFD to the programmed phase threshold value. If the
absolute value of the phase error sample is less than or equal to
the programmed phase threshold value, the detector control logic
dumps one fill bucket into the tub. Otherwise, it removes one
drain bucket from the tub. Note that it is not the polarity of the
phase error sample but, rather, its magnitude relative to the phase
threshold value that determines whether to fill or drain. If more
filling is taking place than draining, the water level in the tub
eventually rises above the high water mark (+1024), which causes
the phase lock detector to indicate lock. If more draining is taking
place than filling, the water level in the tub eventually falls below
the low water mark (−1024), which causes the phase lock detector
to indicate unlock. The ability to specify the threshold level, fill
rate, and drain rate enables the user to tailor the operation of
the phase lock detector to the statistics of the timing jitter
associated with the input reference signal.
The input to the DDS is the 48-bit FTW. The FTW serves as
a step size value. On each cycle of fS, the accumulator adds the
value of the FTW to the running total at its output. For example,
given that FTW = 5, the accumulator counts by fives, incrementing on each fS cycle. Over time, the accumulator reaches
the upper end of its capacity (248 in this case), at which point,
it rolls over but retains the excess. The average rate at which the
accumulator rolls over establishes the frequency of the output
sinusoid. The average rollover rate of the accumulator establishes
the output frequency (fDDS) of the DDS and is given by
Note that when the AD9547 enters the free-run or holdover
mode, the DPLL phase lock detector indicates unlocked. Also,
when the AD9547 performs a reference switchover, the state of
the lock detector prior to the switch is preserved during the
transition period.
⎛ FTW ⎞
f DDS = ⎜ 48 ⎟ f S
⎝ 2 ⎠
DPLL Frequency Lock Detector
Solving this equation for FTW yields
The operation of the frequency lock detector is identical to that
of the phase lock detector. The only difference is that the fill or
drain decision is based on the period deviation between the
reference and feedback signals of the DPLL instead of the phase
error at the output of the PFD.
⎡ ⎛f
FTW = round ⎢2 48 ⎜ DDS
⎢⎣ ⎜⎝ f S
For example, given that fS = 1 GHz and fDDS = 155.52 MHz, then
FTW = 43,774,988,378,041 (0x27D028A1DFB9).
The frequency lock detector uses a 24-bit frequency threshold
register specified in units of picoseconds (ps). Thus, the frequency threshold value extends from 0 μs to ±16.777215 μs.
48-BIT ACCUMULATOR
48
48
Note that the minimum DAC output frequency is 62.5 MHz;
therefore, normal operation requires an FTW that yields an
output frequency in excess of this lower bound.
PHASE
OFFSET
16
19
48
D
Q
19
ANGLE TO
AMPLITUDE
CONVERSION
14
DAC+
DAC
(14-BIT)
DAC–
fS
Figure 40. DDS Block Diagram
Rev. 0 | Page 34 of 104
08300-018
FREQUENCY
TUNING WORD
(FTW)
⎞⎤
⎟⎥
⎟⎥
⎠⎦
AD9547
The relative phase of the sinusoid generated by the DDS is numerically controlled by adding a phase offset word to the output of the
DDS accumulator. This is accomplished via the open loop phase
offset register (Address 0x030D to Address 0x030E), which is a
programmable 16-bit value (Δphase). The resulting phase offset,
ΔΦ (radians), is given by
⎛ Δphase ⎞
ΔΦ = 2π⎜
⎟
⎝ 216 ⎠
The output of the digital core of the DDS is a time series of
numbers representing a sinusoidal waveform. The DAC
translates the numeric values to an analog signal. The DAC
output signal appears at two pins that constitute a balanced
current source architecture (see Figure 41).
16
CURRENT
MIRROR
CURRENT
SWITCH
ARRAY
DACOUTP 13
IFS 1–
UPPER
TUNING
WORD
The user controls the frequency clamp boundaries via the pullin range limit registers (Address 0x0307 to Address 0x030C).
These registers allow the user to fix the DDS output frequency
between an upper and lower bound with a granularity of 24 bits.
Note that these upper and lower bounds apply regardless of the
frequency tuning word that appears at the input to the DDS.
The register value relates to the absolute upper or lower
frequency bound (fCLAMP) as
CODE
214 – 1
14 DACOUTN
SWITCH
CONTROL
50Ω
LOWER
TUNING
WORD
Frequency Clamp
IFS
CODE
IFS
214 – 1
FROM DIGITAL
LOOP FILTER
TO DDS
However, regardless of the operating mode, the DDS output
frequency is ultimately subject to the boundary conditions
imposed by the frequency clamp logic as explained in the
Frequency Clamp section.
AVDD3
10
TUNING
WORD
CLAMP
TUNING
WORD
ROUTING
CONTROL
TUNING WORD
UPDATE
When the DPLL is in free-run mode, the DDS tuning word
is the value stored in the free-running frequency tuning word
register (Address 0x0300 to Address 0x0305). When the DPLL
is operating normally (closed loop), the DDS tuning word comes
from the output of the digital loop filter, which changes dynamically to maintain phase lock with the input reference signal
(assuming that the device has not performed an automatic switch
to holdover mode). When the DPLL is in holdover mode, the DDS
tuning word depends on a historical record of past tuning words
during the time that the DPLL operated in closed-loop mode.
DAC Output
ISCALE
FREE-RUN
TUNING WORD
Figure 42. Tuning Word Processing
Phase offset and relative time offset are directly related. The
time offset is (Δphase/216)/fDDS (seconds), where fDDS is the
output frequency of the DDS (Hz).
14
50Ω
fCLAMP = fS × (N/224)
GND
GND
08300-019
CODE
where N is the value stored in the upper- or lower-limit register,
and fS is the system sample rate.
Figure 41. DAC Output Pins
The value of IFS is programmable via the 10-bit DAC full-scale
current word in the DAC current register (Address 0x0213 and
Address 0x0214). The value of the 10-bit word (ISCALE) sets IFS
according to the following formula:
3
IFS = 120 μA × (72 + ⎛⎜ ⎞⎟ × ISCALE)
⎝ 16 ⎠
The frequency tuning words that dictate the output frequency
of the DDS come from one of three sources (see Figure 42).
The free-running frequency tuning word register
The output of the digital loop filter
The output of the tuning word history processor
Even though the frequency clamp limits put a bound on the
DDS output frequency, the DPLL is still free to steer the DDS
frequency within the clamp limits. The default register values
set the clamp range from 0 Hz (dc) to fS, effectively eliminating
the frequency clamp functionality until the user alters the
register values.
Frequency Tuning Word History
TUNING WORD PROCESSING
•
•
•
TUNING WORD
HISTORY
PROCESSOR
TUNING WORD
HISTORY
08300-070
DDS Phase Offset
The AD9547 has the ability to track the history of the tuning
word samples generated by the DPLL digital loop filter output.
It does so by periodically computing the average tuning word
value over a user-specified interval. The user programs the
interval via the 24-bit history accumulation timer register
(Address 0x0318 to Address 0x031A). This 24-bit value represents a time interval (TAVG) in units of milliseconds (ms) that
extends from 1 ms to a maximum of 4:39:37.215 (hr:min:sec).
Rev. 0 | Page 35 of 104
AD9547
Note that history accumulation timer = 0 should not be programmed because it may cause improper device operation.
The control logic performs a calculation of the average tuning
word during the TAVG interval and stores the result in the holdover
history register (Address 0x0D14 to Address 0x0D19). Computation of the average for each TAVG interval is independent of the
previous interval (that is, the average is a memoryless average as
opposed to a true moving average). In addition, at the end of each
TAVG interval, the device generates an internal strobe pulse. The
strobe pulse sets the history updated bit in the IRQ monitor
register (assuming that the bit is enabled via the IRQ mask register).
Furthermore, the strobe pulse is available as an output signal via
the multifunction pins (see the Multifunction Pins (M0 to M7)
section).
History accumulation begins when the device switches to a new
reference. By default, the device clears any previous history when
it switches to a new reference. Furthermore, the user can clear
the tuning word history under software control using Bit 2 of
Register 0x0A03 or under hardware control via the multifunction
pins (see the Multifunction Pins (M0 to M7) section). However,
the user has the option of programming the device to retain
(rather than clear) the old history by setting the persistent
history bit (Register 0x031B, Bit 3).
When the tuning word history is nonexistent (that is, after
a power-up, reset, or switchover to a new reference with the
persistent history bit cleared), the device waits for the history
accumulation timer (TAVG) to expire before storing the first
history value in the holdover history register.
In cases where TAVG is quite large (4½ hours, for example), a
problem arises in that the first averaged result does not become
available until the full TAVG interval passes. Thus, it is possible
that as much as 4½ hours can elapse before the first averaged
result is available. If the device must switch to holdover during
this time, a tuning word history is not available.
To alleviate this problem, the user can access the incremental
average bits in the history mode register (Register 0x031B,
Bits[2:0]). If the history has been cleared, this 3-bit value, K
(0 ≤ K ≤ 7), specifies the number of intermediate averages to take
during the first, and only the first, TAVG interval. When K = 0, no
intermediate averages are calculated; therefore, the first average
occurs after Interval TAVG (the default operating mode). However,
if K = 4, for example, four intermediate averages are taken during
the first TAVG interval.
These average computations occur at TAVG/16, TAVG/8, TAVG/4,
TAVG/2, and TAVG (note that the denominator exhibits a sequence
of powers of 2 beginning with TAVG/2K). The calculation of intermediate averages occurs only during the first TAVG interval. All
subsequent average computations occur at evenly spaced
intervals of TAVG.
LOOP CONTROL STATE MACHINE
The loop control state machine is responsible for monitoring,
initiating, and sequencing changes to the DPLL loop. Generally,
it automatically controls the transition between input references
and the entry and exit of holdover mode. In controlling loop state
changes, the state machine also arbitrates the application of new
loop filter coefficients, divider settings, and phase detector offsets
based on the profile settings. The user can manually force the
device into holdover or free-run mode via the loop mode register
(Address 0x0A01), as well as force the selection of a specific
input reference.
Switchover
Switchover occurs when the loop controller switches directly
from one input reference to another. Functionally, the AD9547
handles a reference switchover by briefly entering holdover mode
then immediately recovering. During the switchover event,
however, the AD9547 preserves the status of the lock detectors
in order to avoid phantom unlock indications.
Holdover
The holdover state of the DPLL is an open-loop operating mode;
that is, the device no longer operates as a closed-loop system.
Instead, the output frequency remains constant and is dependent
on the device programming and availability of the tuning word
history as explained in the following paragraphs.
If a tuning word history exists (see the Frequency Tuning Word
History section), the holdover frequency is the average frequency
just prior to entering the holdover state. If there is no tuning word
history, the holdover frequency depends on the state of the single
sample fallback bit in the history mode register (Register 0x031B,
Bit 4). If the single sample fallback bit is Logic 0, the holdover
frequency is the frequency defined in the free-running frequency
tuning word register (Address 0x0300 to Address 0x0305). If the
single sample fallback bit is Logic 1, the holdover frequency is the
last instantaneous frequency output by the DDS just prior to the
device entering holdover mode (note that this is not the average
frequency prior to holdover).
The initial holdover frequency accuracy depends on the loop
bandwidth of the DPLL and the time elapsed to compute a tuning
word history. The longer the historical average, the more accurate
the initial holdover frequency (assuming a drift-free system clock).
Furthermore, the stability of the system clock establishes the
stability and long-term accuracy of the holdover output frequency.
Another consideration is the 48-bit frequency tuning resolution
of the DDS and its relationship to fractional frequency error, ΔfO/fO.
f
Δf O
= 49 S
fO
2 fO
In this equation, fS is the sample rate of the output DAC and fO
is the DDS output frequency. The worst-case scenario is maximum
fS (1 GHz) and minimum fO (62.5 MHz), which yields ΔfO/fO =
2.8 × 10−14, which is less than one part in ten trillion.
Rev. 0 | Page 36 of 104
AD9547
Recovery from Holdover
System Clock Period
When in holdover, if a valid reference becomes available, the
device exits holdover operation. The loop state machine restores
the DPLL to closed-loop operation, locks to the selected reference,
and sequences the recovery of all the loop parameters based on
the profile settings for the active reference.
Many of the user-programmable parameters of the AD9547 have
absolute time units. To make this possible, the AD9547 requires
a priori knowledge of the period of the system clock. To accommodate this requirement, the user programs the 21-bit nominal
system clock period in the nominal SYSCLK period register
(Address 0x0103 to Address 0x0105). The contents of this register
reflect the actual period of the system clock in units of femtoseconds (fs). The user must program this register properly to
ensure proper operation of the device because many of its
subsystems rely on this value.
Note that if the user holdover bit (Register 0x0A01, Bit 6) is set,
the device does not automatically exit holdover when a valid
reference is available. However, automatic recovery can occur
after clearing the user holdover bit.
SYSTEM CLOCK INPUTS
System Clock Details
Functional Description
The system clock circuit provides a low jitter, stable, high frequency clock for use by the rest of the chip. The user has the
option of directly driving the SYSCLKx inputs with a high
frequency clock source at the desired system clock rate.
Alternatively, the SYSCLKx input can be configured to operate
in conjunction with the internal SYSCLK PLL. The SYSCLK
PLL can synthesize the system clock by means of a crystal
resonator connected across the SYSCLKx input pins or by
means of direct application of a low frequency clock source.
The SYSCLKx inputs are internally biased to a dc level of ~1 V.
Take care to ensure that any external connections do not disturb
the dc bias because such a disturbance can significantly degrade
performance. Generally, the SYSCLKx inputs should be ac-coupled
to the signal source (except when using a crystal resonator).
LF
SYSCLKN 37
A block diagram of the system clock appears in Figure 43. The
signal at the SYSCLKx input pins becomes the internally
buffered DAC sampling clock (fS) via one of three paths.
•
•
•
High frequency direct (HF)
Low frequency synthesized (LF)
Crystal resonator synthesized (XTAL)
Note that both the LF and XTAL paths require the use of the
SYSCLK PLL (see the SYSCLK PLL Multiplier section).
The main purpose of the HF path is to allow the direct use of
a high frequency (500 MHz to 1 GHz) external clock source for
clocking the AD9547. This path is optimized for high frequency
and low noise floor. Note that the HF input also provides a path
to SYSCLK PLL (see the SYSCLK PLL Multiplier section), which
includes an input divider (M) programmable for divide-by −1,
−2, −4, or −8. The purpose of the divider is to limit the frequency
at the input to the PLL to less than 150 MHz, which is the maximum PFD rate.
SYSCLK_VREG
SYSCLK_LF
34
35
2×
LOCK
DETECT
÷M
PFD
AND
CHARGE
PUMP
XTAL
SYSCLKP 38
VCO
CALIBRATION
LOOP
FILTER
÷N
SYSTEM
CLOCK
08300-020
HF
Figure 43. System Clock Block Diagram
Rev. 0 | Page 37 of 104
AD9547
The LF path permits the user to provide an LVPECL, LVDS,
CMOS, or sinusoidal low frequency clock for multiplication
by the integrated SYSCLK PLL. The LF path handles input
frequencies from 3.5 MHz up to 100 MHz. However, when
using a sinusoidal input signal, it is best to use a frequency in
excess of 20 MHz. Otherwise, the resulting low slew rate can
lead to substandard noise performance. Note that the LF path
includes an optional 2× frequency multiplier to double the rate
at the input to the SYSCLK PLL and potentially reduce the PLL
in-band noise. However, to avoid exceeding the maximum PFD
rate of 150 MHz, use of the 2× frequency multiplier is valid only
for input frequencies below 125 MHz.
The XTAL path enables the connection of a crystal resonator
(typically 10 MHz to 50 MHz) across the SYSCLKx input pins.
An internal amplifier provides the negative resistance required
to induce oscillation. The internal amplifier expects a 3.2 mm ×
2.5 mm AT cut, fundamental mode crystal with a maximum
motional resistance of 100 Ω. The following crystals, listed in
alphabetical order, may meet these criteria. Note that, although
these crystals meet the preceding criteria according to their data
sheets, Analog Devices, Inc., does not guarantee their opera-tion
with the AD9547, nor does Analog Devices endorse one crystal
manufacturer/supplier over another.
AVX/Kyocera CX3225SB
ECS ECX-32
Epson/Toyocom TSX-3225
NDK NX3225SA
Siward SX-3225
SYSCLK PLL MULTIPLIER
The SYSCLK PLL multiplier is an integer-N design and relies on
an integrated LC tank and VCO. It provides a means to convert
a low frequency clock input to the desired system clock frequency,
fS (900 MHz to 1 GHz). The SYSCLK PLL multiplier accepts input
signals between 3.5 MHz and 500 MHz, but frequencies in excess
of 150 MHz require the M-divider to ensure compliance with
the maximum PFD rate (150 MHz). The PLL contains a feedback
divider (N) that is programmable for divide values between 6 and
255. The nominal VCO gain is 70 MHz/V.
Lock Detector
The SYSCLK PLL phase detector operates at the PFD rate, which is
fVCO/N. Each PFD sample indicates whether the reference and feedback signals are phase aligned (within a certain threshold range).
While the PLL is in the process of acquiring a lock condition,
the PFD samples typically consist of an arbitrary sequence of
in-phase and out-of-phase indications. As the PLL approaches
complete phase lock, the number of consecutive in-phase PFD
samples grows larger. Thus, one way of indicating a locked
condition is to count the number of consecutive in-phase PFD
samples and, if it exceeds a certain value, declare the PLL locked.
This is exactly the role of the lock detect divider bits. When the
lock detector is enabled (Register 0x0100, Bit 2 = 0), the lock detect
divider bits determine the number of consecutive in-phase decisions that are required (128, 256, 512, or 1024) before the lock
detector declares a locked condition. The default setting is 128.
Charge Pump
The charge pump operates in either automatic or manual mode,
based on the charge pump mode bit (Register 0x0100, Bit 6).
When Register 0x0100, Bit 6 = 0, the AD9547 automatically selects
the appropriate charge pump current based on the N divider value.
Note that the user does not have control of the charge pump current bits (Register 0x0100, Bits[5:3]) in automatic mode. When
Register 0x0100, Bit 6 = 1, the user determines the charge pump
current via the charge pump current bits (Register 0x0100,
Bits[5:3]). The charge pump current varies from 125 μA to 1 mA
in 125 μA steps. The default setting is 500 μA.
SYSCLK PLL Loop Filter
The AD9547 has an internal second-order loop filter that establishes the loop dynamics for input signals between 12.5 MHz and
100 MHz. By default, the device uses the internal loop filter.
However, an external loop filter option is available by setting
the external loop filter enable bit (Register 0x0100, Bit 7). This
bit bypasses the internal loop filter and allows the device to use
an externally connected second-order loop filter, as shown in
Figure 44.
AD9547
The SYSCLK PLL has a built-in lock detector. Register 0x0100,
Bit 2 determines whether the lock detector is active. When it
is active (default), the user controls the sensitivity of the lock
detector via the lock detect divider bits (Register 0x0100, Bits[1:0]).
SYSCLK_VREG
SYSCLK_LF
34
35
R1
C1
C2
08300-021
•
•
•
•
•
Note that a value of zero must be written to the system clock
stability timer (Register 0x0106 to Register 0x0108) whenever
the lock detector is disabled (Register 0x0100, Bit 2 = 1).
Figure 44. External Loop Filter Schematic
Rev. 0 | Page 38 of 104
AD9547
To determine the external loop filter components, the user decides
on the desired open loop bandwidth (fOL) and phase margin (φ).
These parameters allow calculation of the loop filter components,
as follows:
C2 =
Note that the monitors/detectors associated with the input
references (REF A/REF AA and REF B/REF BB) are internally
disabled until the SYSCLK PLL indicates that it is stable.
I CP K VCO tan(φ)
2N (πf OL ) 2
I CP K VCO
N (2πf OL )2
CLOCK DISTRIBUTION
The clock distribution block of the AD9547 provides an integrated
solution for generating multiple clock outputs based on frequency
dividing the DPLL output. The distribution output consists of
two channels (OUT0 and OUT1). Each channel has a dedicated
divider and output driver section, as shown in Figure 45.
⎛ 1 − sin(φ) ⎞
⎜⎜
⎟⎟
⎝ cos(φ) ⎠
where:
KVCO = 7 × 107 V/ns (typical).
ICP is the programmed charge pump current (amperes).
N is the programmed feedback divider value.
fOL is the desired open-loop bandwidth (Hz).
Φ is the desired phase margin (radians).
CLKINP
CLKINN
SYNC
CONTROL
ENABLE
For example, assuming that N = 40, ICP = 0.5 mA, fOL = 400 kHz,
and Φ = 50°, then the loop filter calculations yield R1 = 3.31 kΩ,
C1 = 330 pF, and C2 = 50.4 pF.
System Clock Stability Timer
4
The system clock stability timer, located in Register 0x0106 to
Register 0x0108, is a 20-bit value programmed in units of milliseconds (ms). If the programmed timer value is 0, the timer
immediately indicates that it has timed out. If the programmed
timer value is nonzero and the SYSCLK PLL is enabled, the timer
starts timing when the SYSCLK PLL lock detector indicates lock
and times out after the prescribed period. However, when the user
disables the SYSCLK PLL, the timer ignores the SYSCLK PLL
lock detector and starts timing the instant that the SYSCLK PLL
is disabled. The user can monitor the status of the stability timer
at Register 0x0D01, Bit 4, via the multifunction pins or via the IRQ
pin.
Note that the system clock stability timer must be programmed
before the SYSCLK PLL is either activated or disabled.
SYSCLK PLL Calibration
When using the SYSCLK PLL, it is necessary to calibrate the
LC-VCO to ensure that the PLL can remain locked to the system
clock input signal. Assuming the presence of either an external
SYSCLK input signal or a crystal resonator, the calibration process
executes after the user sets and then clears the calibrate system
clock bit in the cal/sync register (Register 0x0A02, Bit 0). During
the calibration process, the device calibrates the VCO amplitude
and frequency. The status of the system clock calibration process
is user accessible via the system clock status register (Register
0x0D01, Bit 1). It is also available via the IRQ monitor register
(Bit 1 of Register 0x0D02), provided that the status bit is enabled
via the IRQ mask register (Register 0x0209 and Register 0x0210).
SYNC SOURCE
ENABLEn/MODEn
4
4
Q0
OUT_RSET
OUT0P
OUT0N
OUT0
OUT1
OUT1P
OUT1N
08300-022
C1 =
πNf OL ⎛
1 ⎞
⎜⎜1 +
⎟
sin(φ) ⎟⎠
I CP K VCO ⎝
RESET
R1 =
When the calibration sequence is complete, the SYSCLK PLL
eventually attains a lock condition, at which point the system
clock stability timer begins its countdown sequence. Expiration
of the timer indicates that the SYSCLK PLL is stable, which is
reflected in the system clock status register (Register 0x0D01, Bit 4).
Figure 45. Clock Distribution
Clock Input (CLKINx)
The clock input handles input signals from a variety of logic
families (assuming proper terminations and sufficient voltage
swing). It also handles sine wave input signals such as those
delivered by the DAC reconstruction filter. Its default operating
frequency range is 62.5 MHz to 500 MHz.
Super-Nyquist Operation
Typically, the maximum usable frequency at the DAC output is
about 45% of the system clock frequency. However, because it is
a sampled DAC, its output spectrum contains Nyquist images.
Of particular interest are the images appearing in the first Nyquist
zone (50% to 100% of the system clock frequency). Super-Nyquist
operation takes advantage of these higher frequencies, but this
implies that the CLKINx input operates in excess of 500 MHz,
which is outside its default operating limits.
The CLKINx receiver actually consists of two separate receivers:
the default receiver and an optional high frequency receiver,
which handles input signals up to 800 MHz. To select the high
frequency receiver, write a Logic 1 to Register 0x0400, Bit4.
Rev. 0 | Page 39 of 104
AD9547
Super-Nyquist operation requires a band-pass filter at the DAC
output instead of the usual low-pass reconstruction filter. SuperNyquist operation is viable as long as the image frequency does
not exceed the 800 MHz input range of the receiver. Furthermore,
to provide acceptable jitter performance, which is a consideration
for image signals with low amplitude, the signal at the CLKINx
inputs must meet the minimum slew rate requirements.
Output Enable
Clock Dividers
Output Mode
The output clock distribution dividers are referred to as Q0 and Q1,
corresponding to the OUT0 and OUT1 output channels, respectively. Each divider is programmable with 30 bits of division depth.
The actual divide ratio is one more than the programmed register
value; therefore, a register value of 3, for example, results in a
divide ratio of 4. Thus, each divider offers a range of divide ratios
from 1 to 230 (1 to 1,073,741,824).
The user has independent control of the operating mode of each of
the two output channels via the distribution channel modes register
(Address 0x0404 and Address 0x0405). The operating mode
control includes
With an even divide ratio, the output signal always exhibits a
50% duty cycle. When the clock divider is bypassed (a divide
ratio of 1), the output duty cycle is the same as the input duty
cycle. Odd output divide ratios (excluding 1) exhibit automatic
duty cycle correction given by
Output Duty Cycle =
N + 2X −1
2N
For example, if N = 5 and the input duty cycle is 20% (X = 0.2),
then the output duty cycle is 44%. Note that, when the user
programs an output as noninverting, then the device adjusts the
falling edge timing to accomplish the duty cycle cor-rection.
Conversely, the device adjusts the rising edge timing for an
inverted output.
Output Power-Down
Each output channel offers independent control of power-down
functionality via the distribution settings register (Address 0x0400).
Each output channel has a dedicated power-down bit for powering
down the output driver. However, if both channels are powered
down, the entire distribution output enters a deep sleep mode.
Even though each channel has a channel power-down control
signal, it may sometimes be desirable to power down an output
driver while maintaining the divider’s synchronization with the
other channel dividers. This is accomplished by either of the
following methods:
•
•
•
•
Logic family and pin functionality
Output drive strength
Output polarity
The three LSBs of both distribution channel mode registers comprise the mode bits. The mode value selects the desired logic
family and pin functionality of an output channel, as listed in
Table 23.
Table 23. Output Channel Logic Family and Pin Functionality
where:
N (which must be an odd number) is the divide ratio.
X is the normalized fraction of the high portion of the input period
(that is, 0 < X < 1).
•
Each output channel offers independent control of enable/
disable functionality using the distribution enable register
(Address 0x0401). The distribution outputs use synchronization
logic to control enable/disable activity to avoid the production
of runt pulses and to ensure that outputs with the same divide
ratios become active/inactive in unison.
In CMOS mode, use the divider output enable control bit
to stall an output. This provides power savings while maintaining dc drive at the output.
In LVDS/LVPECL mode, place the output in tristate mode
(this works in CMOS mode as well).
Mode Bits [2:0]
000
001
010
011
100
101
110
111
Logic Family and Pin Functionality
CMOS (both pins)
CMOS (positive pin), tristate (negative pin)
Tristate (positive pin), CMOS (negative pin)
Tristate (both pins)
LVDS
LVPECL
Unused
Unused
Regardless of the selected logic family, each is capable of dc
operation. However, the upper frequency is limited by the load
conditions, drive strength, and impedance matching inherent in
each logic family. Practical limitations set the maximum CMOS
frequency to approximately 250 MHz, whereas LVPECL and
LVDS are capable of 725 MHz.
In addition to the three mode bits, both distribution channel
mode registers include the following control bits:
•
•
•
Polarity invert
CMOS phase invert
Drive strength
The polarity invert bit enables the user to choose between normal
polarity and inverted polarity. Normal polarity is the default
state. Inverted polarity reverses the representation of Logic 0
and Logic 1 regardless of the logic family.
The CMOS phase invert bit applies only when the mode bits select
the CMOS logic family. In CMOS mode, both output pins of the
channel have a dedicated CMOS driver. By default, both drivers
deliver identical signals. However, setting the CMOS phase invert
bit causes the signal on an OUTxN pin to be the opposite of the
signal appearing on the OUTxP pin.
Rev. 0 | Page 40 of 104
AD9547
The drive strength bit allows the user to control whether the
output uses weak (0) or strong (1) drive capability (applies to
CMOS and LVDS but not LVPECL). For the CMOS family, the
strong setting implies normal CMOS drive capability, whereas
the weak setting implies low capacitive loading and allows for
reduced EMI. For the LVDS family, the weak setting provides
3.5 mA drive current for standard LVDS operation, whereas the
strong setting provides 7 mA for double terminated or double
voltage LVDS operation. Note that 3.5 mA and 7 mA are the
nominal drive current values when using the internal current
setting resistor.
Clock Distribution Synchronization
A block diagram of the distribution synchronization functionality
appears in Figure 46. The synchronization sequence begins with
the primary synchronization signal, which ultimately results in
delivery of a synchronization strobe to the clock distribution logic.
As indicated, the primary synchronization signal originates
from the following four possible sources:
•
•
Output Current Control with an External Resistor
By default, the output drivers have an internal current setting
resistor (3.12 kΩ nominal) that establishes the nominal drive
current for the LVDS and LVPECL operating modes. Instead of
using the internal resistor, the user can elect to set the external
distribution resistor bit (Register 0x0400, Bit 5) and connect an
external resistor to the OUT_RSET pin. Note that this feature
supports an external resistor value of 3.12 kΩ only, allowing for
tighter control of the output current than is possible by using
the internal current setting resistor. However, if the user elects
to use a nonstandard external resistance, the following equations
provide the output drive current as a function of the external
resistance (R):
I LVDS0
10.8325
=
R
I LVDS1 =
21.665
R
I LVPECL =
24.76
R
The numeric subscript associated with the LVDS output current corresponds to the logic state of the drive strength bit in the
distribution channel modes registers (Address 0x0404, Bit 3 and
Address 0x0405, Bit 3). For R = 3.12 kΩ, the equations yield
ILVDS0 = 3.5 mA, ILVDS1 = 7.0 mA, and ILVPECL = 8.0 mA. Note that
the device maintains a constant 1.238 V (nominal) across the
external resistor.
•
•
Direct synchronization source via the sync distribution bit
(Register 0x0A02, Bit 1)
Automatic synchronization source based on frequency or
phase lock detection, as controlled via the automatic synchronization register (Address 0x0403)
Multifunction pin synchronization source via one of the
multifunction pins (M0 to M7)
EEPROM synchronization source via the EEPROM
All four sources of the primary synchronization signal are logic
OR’d, so any one of them can synchronize the clock distribution
output at any time. When using the multifunction pins, the synchronization event is the falling edge of the selected signal. When
using the sync distribution bit, the user first sets then clears the bit.
The synchronization event is the clearing operation; that is, the
Logic 1 to Logic 0 transition of the bit.
The primary synchronization signal can synchronize the distribution output directly, or it can enable a secondary synchronization
signal. This functionality depends on the two sync source bits
in the distribution synchronization register (Register 0x0402,
Bits[5:4]).
When sync source = 00 (direct), the falling edge of the primary
synchronization signal directly synchronizes the distribution
output.
When sync source = 01, the rising edge of the primary synchronization signal triggers the circuitry that detects a rising edge of the
active input reference. The detection of the rising edge synchronizes the distribution output.
When sync source = 10, the rising edge of the primary synchronization signal triggers the circuitry that detects a rollover of the
DDS accumulator (after processing by the DPLL feedback divider).
This corresponds to the zero crossing of the output of the phase-toamplitude converter in the DDS (less the open-loop phase offset
stored in Register 0x030D and Register 0x030E). The detection
of the DPLL feedback edge synchronizes the distribution output.
Rev. 0 | Page 41 of 104
AD9547
Active Reference Synchronization (Zero Delay)
Active reference synchronization is the term applied to the case
when sync source = 01 (Register 0x0402, Bits[5:4]). Referring to
Figure 46, this means that the active reference sync path is active
because Bit 4 = 1, enabling the lower AND gate and disabling
the upper AND gate. The edge detector in the active reference
sync block monitors the rising edges of the active reference
(the mux selects the active reference automatically). The edge
detector is armed via the primary synchronization signal, which
is one of the four inputs to the OR gate (typically the direct sync
source). As soon as the edge detector is armed, its output goes high,
which stalls the output dividers in the clock distribution block.
Furthermore, once armed, a rising edge from the active reference
forces the output of the edge detector low. This restarts the output
dividers, thereby synchronizing the clock distribution block.
The term zero delay applies because it provides a means to edgealign the output signal with the active input reference signal.
Typically, zero-delay architectures use the output signal in the
feedback loop of a PLL to track input/output edge alignment.
REGISTER
0x0402[5]
PRIMARY
SYNCHRONIZATION
SIGNAL
DIRECT SYNC
AUTOMATIC SYNC
SOURCE
(REGISTER DX 0x0403)
EEPROM SYNC
SOURCE
TO MULTIFUNCTION
PIN STATUS LOGIC
0
TO CLOCK
DISTRIBUTION
SYNCHRONIZATION
CONTROL
1
EDGE
DETECT
MULTIFUNCTION PIN
SYNC SOURCE
The fact that an active reference edge triggers the falling edge of
the synchronization pulse means that the falling edge is asynchronous to the signal that clocks the distribution output dividers
(CLKINx). Therefore, the output clock distribution logic reclocks
the internal synchronization pulse to synchronize it with the
CLKINx signal. This means that the output dividers restart after
a deterministic delay associated with the reclocking circuitry.
This deterministic delay has two components. The first deterministic delay component is four or five periods of the CLKINx
signal. The one period uncertainty is due to the unknown position
of the asynchronous reference clock edge relative to the CLKINx
signal. The second deterministic delay component is one output
period of the distribution divider.
DPLL
FEEDBACK
EDGE
ARM
STALL
DIVIDERS
SYNC OUTPUT
DISTRIBUTION
EDGE
DETECT
SYSCLK/4
DPLL EDGE SYNC
REGISTER
0x0402[4]
RESET
ARM
REF A
EDGE
DETECT
REF BB
ACTIVE REFERENCE SYNC
Figure 46. Output Synchronization Block Diagram
Rev. 0 | Page 42 of 104
08300-023
DIRECT SYNC
SOURCE
(ADDRESS DX 0x0A02[1])
Active reference synchronization, however, operates open loop.
That is, synchronization of the output via the distribution
synchronization logic occurs on a single edge of the active
reference.
AD9547
The deterministic delay, expressed as tLATENCY in the following
equation, is a function of the frequency division factor (Qn) of
the channel divider associated with the zero-delay channel.
tLATENCY = (Qn + 4) × tCLK_IN or tLATENCY = (Qn + 5) × tCLK_IN
In addition to deterministic delay, there is random delay (tPROP)
associated with the propagation of the reference signal through
the input reference receiver, as well as the propagation of the
clock signal through the clock distribution logic. The total delay is
tDELAY = tLATENCY + tPROP
The user can compensate for tDELAY by using the device’s phase
offset controls to move the edge timing of the distribution output
signal relative to the input reference edge. One method is to
use the open-loop phase offset registers (Address 0x030D and
Address 0x030E) for timing adjustment. However, be sure to
use sufficiently small phase increments to make the adjustment.
Too large a phase step can result in the clock distribution logic
missing a CLKINx edge, thus disrupting the edge alignment
process. The appropriate phase increment depends on the
transient response of any external circuitry connected between
the DACOUTx and CLKINx pins.
The other method is to use the closed-loop phase offset registers
(Address 0x030F to Address 0x0315) for timing adjustment.
However, be sure to use a sufficiently small phase vs. time profile.
Changing the phase too quickly can cause the DPLL to lose lock,
thus ruining the edge alignment process. Note that the AD9547
phase slew limit register (Address 0x0316 and 0x0317) can be
used to limit the rate of change of phase automatically, thereby
mitigating the potential loss-of-lock problem.
To guarantee synchronization of the output dividers, it is
important to make any edge timing adjustments after the
synchronization event. Furthermore, when making timing
adjustments, the distribution outputs can be disabled and then
renabled after the adjustment is complete. This prevents the
device from generating output clock signals during the timing
adjustment process.
Note that the form of zero-delay synchronization described here
does not track propagation time variations within the distribution
clock input path or the reference input path (on or off chip) over
temperature, supply, and so on. It is strictly a one-time synchronization event.
Synchronization Mask
Each output channel has a dedicated synchronization mask bit
(Register 0x0402, Bits[1:0]). When the mask bit associated with
a particular channel is set, that channel does not respond to the
synchronization signal. This allows the device to operate with
the masked channels active and the unmasked channels stalled
while they wait for a synchronization pulse.
Rev. 0 | Page 43 of 104
AD9547
STATUS AND CONTROL
MULTIFUNCTION PINS (M0 TO M7)
The AD9547 has eight digital CMOS I/O pins (M0 to M7) that are
configurable for a variety of uses. The function of these pins is
programmable via the register map. Each pin can control or monitor an assortment of internal functions, based on the contents of
Register 0x0200 to Register 0x0207. To monitor an internal
function with a multifunction pin, write a Logic 1 to the MSB
of the register associated with the desired multifunction pin. The
value of the seven LSBs of the register defines the control function,
as shown in Table 24.
Table 24. Multifunction Pin Output Functions (D7 = 1)
D[6:0]
Value
0
1
2
3
4
5
6
7
8
9
10
11
12 to 15
16
17
18
19
20
21
22
23
24
25
26
27 to 31
32
33
34
35
36 to 47
48
49
50
51
52 to 63
64
Output Function
Static Logic 0
Static Logic 1
System clock divided by 32
Watchdog timer output
EEPROM upload in progress
EEPROM download in progress
EEPROM fault detected
SYSCLK PLL lock detected
SYSCLK PLL calibration in
progress
Unused
Unused
SYSCLK PLL stable
Unused
DPLL free running
DPLL active
DPLL in holdover
DPLL in reference switchover
Active reference: phase master
DPLL phase locked
DPLL frequency locked
DPLL phase slew limited
DPLL frequency clamped
Tuning word history available
Tuning word history updated
Unused
Reference A fault
Reference AA fault
Reference B fault
Reference BB fault
Unused
Reference A valid
Reference AA valid
Reference B valid
Reference BB valid
Unused
Reference A active reference
65
66
Reference AA active reference
Reference B active reference
67
68 to 79
Reference BB active reference
Unused
D[6:0]
Value
80
81 to
127
Output Function
Clock distribution sync pulse
Unused
Source Proxy
Register 0x0D03, Bit 3
To control an internal function with a multifunction pin, write a
Logic 0 to the most significant bit of the register associated with
the desired multifunction pin. The monitored function depends
on the value of the seven least significant bits of the register, as
shown in Table 25. Note that the default setting is M0 through
M7 configured as inputs and the input function set to unused
(the first entry in Table 25).
Table 25. Multifunction Pin Input Functions (D7 = 0)
Source Proxy
Register 0x0D00, Bit 0
Register 0x0D00, Bit 1
Register 0x0D00, Bit 2
Register 0x0D01, Bit 0
Register 0x0D01, Bit 1
Unused
Unused
Register 0x0D01, Bit 4
Unused
Register 0x0D0A, Bit 0
Register 0x0D0A, Bit 1
Register 0x0D0A, Bit 2
Register 0x0D0A, Bit 3
Register 0x0D0A, Bit 6
Register 0x0D0A, Bit 4
Register 0x0D0A, Bit 5
Register 0x0D0A, Bit 7
Register 0x0D0B, Bit 7
Register 0x0D0B, Bit 6
Register 0x0D05, Bit 4
Unused
Register 0x0D0C, Bit 2
Register 0x0D0D, Bit 2
Register 0x0D0E, Bit 2
Register 0x0D0F, Bit 2
Unused
Register 0x0D0C, Bit 3
Register 0x0D0D, Bit 3
Register 0x0D0E, Bit 3
Register 0x0D0F, Bit 3
Unused
Register 0x0D0B, Bits[1:0]
Register 0x0D0B, Bits[1:0}
Register 0x0D0B, Bits[1:0]
Register 0x0D0B, Bits[1:0]
Unused
D[6:0]
Value
0
1
2
3
4
5
6 to 15
16
17
18
19
20
21 to 31
32
33
34
35
36 to 47
48
49
50
51
52 to 63
64
65
66, 67
68
69
70 to 127
Input Function
Unused (default)
I/O update
Full power-down
Watchdog reset
IRQ reset
Tuning word history reset
Unused
Holdover
Free run
Reset incremental phase
offset
Increment incremental phase
offset
Decrement incremental
phase offset
Unused
Override Reference Monitor A
Override Reference Monitor AA
Override Reference Monitor B
Override Reference Monitor BB
Unused
Force Validation Timeout A
Force Validation Timeout AA
Force Validation Timeout B
Force Validation Timeout BB
Unused
Enable OUT0
Enable OUT1
Unused
Enable OUT0, OUT1
Sync clock distribution
outputs
Unused
Destination Proxy
Unused
Register 0x0005, Bit 0
Register 0x0A00, Bit 0
Register 0x0A03, Bit 0
Register 0x0A03, Bit 1
Register 0x0A03, Bit 2
Unused
Register 0x0A01, Bit 6
Register 0x0A01, Bit 5
Register 0x0A0C, Bit 2
Register 0x0A0C, Bit 0
Register 0x0A0C, Bit 1
Unused
Register 0x0A0F, Bit 0
Register 0x0A0F, Bit 1
Register 0x0A0F, Bit 2
Register 0x0A0F, Bit 3
Unused
Register 0x0A0E, Bit 0
Register 0x0A0E, Bit 1
Register 0x0A0E, Bit 2
Register 0x0A0E, Bit 3
Unused
Register 0x0401, Bit 0
Register 0x0401, Bit 1
Unused
Register 0x0401, Bits[1:0]
Register 0x0A02, Bit 1
Unused
If more than one multifunction pin operates on the same control
signal, then internal priority logic ensures that only one multifunction pin serves as the signal source. The selected pin is the
one with the lowest numeric suffix. For example, if both M3
and M7 operate on the same control signal, M3 is used as the
signal source and the redundant pin is ignored.
Rev. 0 | Page 44 of 104
AD9547
At power-up, the multifunction pins can be used to force the device
into certain configurations as defined in the Initial M0 to M7 Pin
Programming section. This functionality, however, is valid only
during power-up or following a reset, after which the pins can
be reconfigured via the serial programming port or via the
EEPROM.
IRQ PIN
The AD9547 has a dedicated interrupt request (IRQ) pin. The
IRQ pin output mode register (Register 0x0208, Bits[1:0]) controls
how the IRQ pin asserts an interrupt based on the value of the
two bits, as shown in Table 26.
Table 26. IRQ Pin Control—Register 0x0208, Bits[1:0]
Setting
00
01
10
11
Description
The IRQ pin is high impedance when deasserted and
active low when asserted and requires an external
pull-up resistor (this is the default operating mode).
The IRQ pin is high impedance when deasserted and
active high when asserted and requires an external
pull-down resistor.
The IRQ pin is Logic 0 when deasserted and Logic 1
when asserted.
The IRQ pin is Logic 1 when deasserted and Logic 0
when asserted.
The AD9547 asserts the IRQ pin when any of the bits in the IRQ
monitor registers (Address 0x0D02 to Address 0x0D09) are
Logic 1. Each bit in these registers is associated with an internal
function that is capable of producing an interrupt. Furthermore,
each bit of the IRQ monitor register is the result of a logical AND
of the associated internal interrupt signal and the corresponding
bit in the IRQ mask register (Address 0x0209 to Address 0x0210).
That is, the bits in the IRQ mask register have a one-to-one correspondence with the bits in the IRQ monitor register. When an
internal function produces an interrupt signal and the associated
IRQ mask bit is set, the corresponding bit in the IRQ monitor
register is set.
The user should be aware that clearing a bit in the IRQ mask
register removes only the mask associated with the internal
interrupt signal. It does not clear the corresponding bit in the
IRQ monitor register.
The IRQ pin is the result of a logical OR of all the IRQ monitor
register bits. Thus, the AD9547 asserts the IRQ pin as long as any of
the IRQ monitor register bits are Logic 1. Note that it is possible
to have multiple bits set in the IRQ monitor register. Therefore,
when the AD9547 asserts the IRQ pin, it may indicate an interrupt
from several different internal functions. The IRQ monitor register
provides the user with a means to interrogate the AD9547 to
determine which internal function(s) produced the interrupt.
Typically, when the AD9547 asserts the IRQ pin, the user interrogates the IRQ monitor register to identify the source of the
interrupt request. After servicing an indicated interrupt, the user
should clear the associated IRQ monitor register bit via the IRQ
clearing registers (Address 0x0A04 to Address 0x0A0B). The bits
in the IRQ clearing register have a one-to-one correspondence
with the bits in the IRQ monitor register. Note that the IRQ
clearing register is autoclearing. The IRQ pin remains asserted
until the user clears all of the bits in the IRQ monitor register
that indicate an interrupt.
It is also possible to collectively clear all of the IRQ monitor
register bits by setting the reset all IRQs bit in the reset functions
register (Register 0x0A03, Bit 1). Note that this is an autoclearing
bit. Setting this bit results in deassertion of the IRQ pin. Alternatively, the user can program any of the multifunction pins to
clear all IRQs. This allows the user to clear all IRQs by means of
a hardware pin rather than by a serial I/O port operation.
WATCHDOG TIMER
The watchdog timer is a general-purpose, programmable timer.
To set its timeout period, the user writes to the 16-bit watchdog
timer register (Address 0x0211 and Address 0x0212). A value of
zero in this register disables the timer. A nonzero value sets the
timeout period in units of milliseconds (ms), giving the watchdog
timer a range of 1 ms to 65,535 ms. The relative accuracy of the
timer is approximately 0.1% with an uncertainty of 0.5 ms.
If enabled, the timer runs continuously and generates a timeout
event whenever the timeout period expires. The user has access
to the watchdog timer status via the IRQ mechanism and the
multifunction pins (M0 to M7). In the case of the multifunction
pins, the timeout event of the watchdog timer is a pulse that
lasts 32 system clock periods.
There are two ways to reset the watchdog timer (thereby preventing it from causing a timeout event). The first is by writing
a Logic 1 to the autoclearing reset watchdog bit in the reset
functions register (Register 0x0A03, Bit 0). Alternatively, the
user can program any of the multifunction pins to reset the
watchdog timer. This allows the user to reset the timer by means
of a hardware pin rather than by a serial I/O port operation.
Rev. 0 | Page 45 of 104
AD9547
EEPROM
EEPROM Overview
The AD9547 contains an integrated 2048-byte electrically erasable
programmable read-only memory (EEPROM). The AD9547
can be configured to perform a download at power-up via the
multifunction pins (M3 to M7), but uploads and downloads
can also be done on demand via the EEPROM control registers
(Address 0x0E00 to Address 0x0E03).
The EEPROM provides the ability to upload and download
configuration settings to and from the register map. Figure 47
shows a functional diagram of the EEPROM.
Register 0x0E10 to Register 0x0E3F represent a 48-byte scratch
pad that enables the user to store a sequence of instructions for
transferring data to the EEPROM from the device settings portion
of the register map. Note that the default values for these registers
provide a sample sequence for saving/retrieving all of the AD9547
EEPROM-accessible registers. Figure 47 shows the connectivity
between the EEPROM and the controller that manages data
transfer between the EEPROM and the register map.
The controller oversees the process of transferring EEPROM data
to and from the register map. There are two modes of operation
handled by the controller: saving data to the EEPROM (upload
mode) or retrieving data from the EEPROM (download mode).
In either case, the controller relies on a specific instruction set.
DATA
EEPROM
ADDRESS
POINTER
DATA
DEVICE SETTINGS
(0x0100 TO 0x0A10)
CONDITION
(0x0E01 [4:0])
DEVICE
SETTINGS
ADDRESS
POINTER
DATA
EEPROM
CONTROLLER
EEPROM
(0x000 TO 0x7FF)
SCRATCH PAD
ADDRESS
POINTER
SCRATCH PAD
(0x0E10 TO 0x0E3F)
REGISTER MAP
Note that, in the EEPROM scratch pad, the two registers that
make up the address portion of a data instruction have the MSB of
the address in the D7 position of the lower register address. The
bit weight increases left to right, from the lower register address
to the higher register address. Furthermore, the starting address
always indicates the lowest numbered register map address in the
range of bytes to transfer. That is, the controller always starts at
the register map target address and counts upward, regardless of
whether the serial I/O port is operating in I2C, SPI LSB first, or
SPI MSB first mode.
As part of the data transfer process during an EEPROM upload,
the controller calculates a 1-byte checksum and stores it as the final
byte of the data transfer. As part of the data transfer process during
an EEPROM download, however, the controller again calculates
a 1-byte checksum value but compares the newly calculated checksum with the one that was stored during the upload process. If an
upload/download checksum pair does not match, the controller
sets the EEPROM fault status bit (Register 0x0D03, Bit 1). If the
upload/download checksums match for all data instructions
encountered during a download sequence, the controller sets
the EEPROM complete status bit (Register 0x0D03, Bit 0).
Condition instructions are those that have a value from 0xB0 to
0xCF. Condition Instruction 0xB1 to Condition Instruction 0xCF
represent Condition 1 to Condition 31, respectively. Condition
Instruction 0xB0 is special because it represents the null condition
(see the EEPROM Conditional Processing section).
08300-024
M7
M6
M5
M4
M3
The controller decodes the number of bytes to transfer directly
from the data instruction itself by adding one to the value of the
instruction. For example, the data instruction, 0x1A, has a decimal
value of 26; therefore, the controller knows to transfer 27 bytes
(one more than the value of the instruction). Whenever the controller encounters a data instruction, it knows to read the next
two bytes in the scratch pad because these bytes contain the
register map target address.
SERIAL
INPUT/OUTPUT
PORT
Figure 47. EEPROM Functional Diagram
EEPROM Instructions
Table 27 lists the EEPROM controller instruction set. The
controller recognizes all instruction types, whether it is in
upload or download mode, except for the pause instruction,
which it recognizes only in upload mode.
The I/O update, calibrate, distribution sync, and end instructions are mostly self-explanatory. The others, however, warrant
further detail, as described in the following paragraphs.
A pause instruction, like an end instruction, is stored at the end
of a sequence of instructions in the scratch pad. When the controller encounters a pause instruction during an upload sequence,
it keeps the EEPROM address pointer at its last value. This way,
the user can store a new instruction sequence in the scratch pad
and upload the new sequence to the EEPROM. The new sequence
is stored in the EEPROM address locations immediately following
the previously saved sequence. This process is repeatable until
an upload sequence contains an end instruction. The pause
instruction is also useful when used in conjunction with condition
processing. It allows the EEPROM to contain multiple occurrences
of the same register(s), with each occurrence linked to a set of
conditions (see the EEPROM Conditional Processing section).
Data instructions are those that have a value from 0x00 to 0x7F.
A data instruction tells the controller to transfer data between
the EEPROM and the register map. The controller needs the
following two parameters to carry out the data transfer:
•
•
The number of bytes to transfer
The register map target address
Rev. 0 | Page 46 of 104
AD9547
Table 27. EEPROM Controller Instruction Set
Instruction
Value (Hex)
0x00 to 0x7F
Instruction Type
Data
Bytes
Required
3
0x80
I/O update
1
0xA0
Calibrate
1
0xA1
Distribution sync
1
0xB0 to 0xCF
Condition
1
0xFE
Pause
1
0xFF
End
1
Description
A data instruction tells the controller to transfer data to or from the device settings
part of the register map. A data instruction requires two additional bytes that,
together, indicate a starting address in the register map. Encoded in the data
instruction is the number of bytes to transfer, which is one more than the
instruction value.
When the controller encounters this instruction while downloading from the
EEPROM, it issues a soft I/O update (see Register 0x0005 in Table 42).
When the controller encounters this instruction while downloading from the EEPROM,
it initiates a system clock calibration sequence (see Register 0x0A02 in Table 120).
When the controller encounters this instruction while downloading from the
EEPROM, it issues a sync pulse to the output distribution synchronization (see
Register 0x0A02 in Table 120).
0xB1 to 0xCF are condition instructions and correspond to Condition 1 to Condition 31,
respectively. 0xB0 is the null condition instruction. See the EEPROM Conditional
Processing section for details.
When the controller encounters this instruction in the scratch pad while uploading
to the EEPROM, it resets the scratch pad address pointer and holds the EEPROM
address pointer at its last value. This allows storage of more than one instruction
sequence in the EEPROM. Note that the controller does not copy this instruction to
the EEPROM during upload.
When the controller encounters this instruction in the scratch pad while uploading
to the EEPROM, it resets both the scratch pad address pointer and the EEPROM
address pointer and then enters an idle state.
When the controller encounters this instruction while downloading from the
EEPROM, it resets the EEPROM address pointer and then enters an idle state.
EEPROM Upload
To upload data to the EEPROM, the user must first ensure that
the write enable bit (Register 0x0E00, Bit 0) is set. Then, on setting the autoclearing save to EEPROM bit (Register 0x0E02, Bit 0),
the controller initiates the EEPROM data storage process.
Uploading EEPROM data requires that the user first write an
instruction sequence into the scratch pad registers. During the
upload process, the controller reads the scratch pad data byte by
byte, starting at Register 0x0E10 and incrementing the scratch
pad address pointer as it goes, until it reaches a pause or end
instruction.
As the controller reads the scratch pad data, it transfers the
data from the scratch pad to the EEPROM (byte by byte) and
increments the EEPROM address pointer accordingly, unless it
encounters a data instruction. A data instruction tells the controller to transfer data from the device settings portion of the
register map to the EEPROM. The number of bytes to transfer
is encoded within the data instruction, and the starting address
for the transfer appears in the next two bytes in the scratch pad.
When the controller encounters a data instruction, it stores the
instruction in the EEPROM, increments the EEPROM address
pointer, decodes the number of bytes to be transferred, and
increments the scratch pad address pointer. Then it retrieves
the next two bytes from the scratch pad (the target address) and
increments the scratch pad address pointer by 2. Next, the controller transfers the specified number of bytes from the register
map (beginning at the target address) to the EEPROM.
When it completes the data transfer, the controller stores an extra
byte in the EEPROM to serve as a checksum for the transferred
block of data. To account for the checksum byte, the controller
increments the EEPROM address pointer by one more than the
number of bytes transferred. Note that, when the controller
transfers data associated with an active register, it actually
transfers the buffered contents of the register (see the
Buffered/Active Registers section for details on the difference
between buffered and active registers). This allows for the
transfer of nonzero autoclearing register contents.
Note that conditional processing does not occur during an
upload sequence (see the EEPROM Conditional Processing
section).
EEPROM Download
An EEPROM download results in a transfer of data from the
EEPROM to the device register map. To download data, the user
sets the autoclearing load from EEPROM bit (Register 0x0E03,
Bit 1). This commands the controller to initiate the EEPROM
download process. During download, the controller reads the
EEPROM data byte by byte, incrementing the EEPROM address
pointer as it goes, until it reaches an end instruction. As the controller reads the EEPROM data, it executes the stored instructions,
which includes transferring stored data to the device settings
portion of the register map whenever it encounters a data
instruction.
Note that conditional processing is applicable only when downloading (see the EEPROM Conditional Processing section).
Rev. 0 | Page 47 of 104
AD9547
Automatic EEPROM Download
The condition originates from one of two sources (see Figure 48),
as follows:
Following power-up, assertion of the RESET pin, or a soft reset
(Register 0x0000, Bit 5 = 1), if FncInit[7:3] ≠ 0 (see the Initial M0 to
M7 Pin Programming section), the instruction sequence stored in
the EEPROM executes automatically with condition = FncInit[7:3].
In this way, a previously stored set of register values downloads
automatically on power-up or with a hard or soft reset. See the
EEPROM Conditional Processing section for details regarding
conditional processing and the way that it modifies the download process.
•
FncInit, Bits[7:3], which is the state of multifunction pins
M3 to M7 at power-up (see the Initial M0 to M7 Pin
Programming section)
Register 0x0E01, Bits[4:0]
•
If Register 0x0E01, Bits[4:0] ≠ 0, then the condition is the value
stored in Register 0x0E01, Bits[4:0]; otherwise, the condition is
FncInit, Bits[7:3]. Note that a nonzero condition that is present
in Register 0x0E01, Bits[4:0] takes precedence over FncInit,
Bits[7:3].
EEPROM Conditional Processing
The condition instructions allow conditional execution of
EEPROM instructions during a download sequence. During
an upload sequence, however, they are stored as is and have
no effect on the upload process.
The condition tag board is a table that is maintained by the
EEPROM controller. When the controller encounters a condition
instruction, it decodes Condition Instruction 0xB1 through Condition Instruction 0xCF as condition = 1 through condition = 31,
respectively, and tags that particular condition in the condition
tag board. However, Condition Instruction 0xB0 decodes as the
null condition, for which the controller clears the condition tag
board; subsequent download instructions execute unconditionally
(until the controller encounters a new condition instruction).
Note that, during EEPROM downloads, the condition instructions
themselves and the end instruction always execute unconditionally.
Conditional processing makes use of two elements: the condition
(from Condition 1 to Condition 31) and the condition tag board.
The relationships among the condition, the condition tag board,
and the EEPROM controller appear schematically in Figure 48.
During download, the EEPROM controller executes or skips
instructions, depending on the value of the condition and the
contents of the condition tag board. Note, however, that condition
instructions and the end instruction always execute unconditionally during download. If condition = 0, all instructions during
download execute unconditionally. If condition ≠ 0 and there
are any tagged conditions in the condition tag board, the controller
executes instructions only if the condition is tagged.
Condition is a 5-bit value with 32 possibilities. Condition = 0 is the
null condition. When the null condition is in effect, the EEPROM
controller executes all instructions unconditionally. The remaining
31 possibilities, condition = 1 through condition = 31, modify the
EEPROM controller’s handling of a download sequence.
CONDITION
TAG BOARD
EXAMPLE
CONDITION 3 AND
CONDITION 13
ARE TAGGED
M7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
REGISTER
0x0E01, BITS[4:0]
FncInit, BITS[7:3]
5
IF B1 ≤ INSTRUCTION ≤ CF,
THEN TAG DECODED CONDITION
IF INSTRUCTION = B0,
THEN CLEAR ALL TAGS
EEPROM
STORE CONDITION
INSTRUCTIONS AS
THEY ARE READ FROM
THE SCRATCH PAD.
WATCH FOR
OCCURRENCE OF
CONDITION
INSTRUCTIONS
DURING
DOWNLOAD.
UPLOAD
PROCEDURE
5
IF {0x0E01, BITS[4:0] ≠ 0}
CONDITION = 0x0E01, BITS[4:0]
ELSE
CONDITION = FncInit, BITS[7:3]
ENDIF
5
CONDITION
CONDITION
HANDLER
SCRATCH
PAD
M3
EXECUTE/SKIP
INSTRUCTION(S)
DOWNLOAD
PROCEDURE
EEPROM CONTROLLER
Figure 48. EEPROM Conditional Processing
Rev. 0 | Page 48 of 104
IF {NO TAGS} OR {CONDITION = 0}
EXECUTE INSTRUCTIONS
ELSE
IF {CONDITION IS TAGGED}
EXECUTE INSTRUCTIONS
ELSE
SKIP INSTRUCTIONS
ENDIF
ENDIF
AD9547
If the condition is not tagged, the controller skips instructions
until it encounters a condition instruction that decodes as a
tagged condition. Note that the condition tag board allows
for multiple conditions to be tagged at any given moment.
This conditional processing mechanism enables the user to
have one download instruction sequence with many possible
outcomes, depending on the value of the condition and the
order in which the controller encounters the condition
instructions.
With the upload sequence written to the scratch pad, perform
an EEPROM upload (Register 0x0E02, Bit 0).
Table 28 lists a sample EEPROM download instruction
sequence. It illustrates the use of condition instructions
and how they alter the download sequence. The table
begins with the assumption that no conditions are in effect.
That is, the most recently executed condition instruction is
0xB0, or no conditional instructions have been processed.
3.
Table 28. EEPROM Conditional Processing Example
Instruction
0x08
0x01
0x00
0xB1
0x19
0x04
0x00
0xB2
0xB3
0x07
0x05
0x00
0x0A
0xB0
0x80
0x0A
Action
Transfer the system clock register contents
regardless of the current condition
Tag Condition 1
Transfer the clock distribution register
contents only if condition = 1
Tag Condition 2
Tag Condition 3
Transfer the reference input register contents
only if condition = 1, 2, or 3
Calibrate the system clock only if condition =
1, 2, or 3
Clear the condition tag board
Execute an I/O update, regardless of the value
of the condition
Calibrate the system clock, regardless of the
value of the condition
Storing Multiple Device Setups in EEPROM
Conditional processing makes it possible to create a number
of different device setups, store them in EEPROM, and
download a specific setup on demand. To do so, first program the device control registers for a specific setup. Then,
store an upload sequence in the EEPROM scratch pad with
the following general form:
1.
2.
3.
Now reprogram the device control registers for the next desired
setup. Then store a new upload sequence in the EEPROM scratch
pad with the following general form:
1.
2.
4.
Condition Instruction 0xB0
The next desired condition instruction (0xB1 to 0xCF, but
different from the one used during the previous upload to
identify a new setup)
Data instructions (to save the register contents) along with
any required calibrate and/or I/O update instructions
Pause instruction (FE)
With the upload sequence written to the scratch pad, perform
an EEPROM upload (Register 0x0E02, Bit 0).
Repeat the process of programming the device control registers
for a new setup, storing a new upload sequence in the EEPROM
scratch pad (Step 1 through Step 4) and executing an EEPROM
upload (Register 0x0E02, Bit 0) until all of the desired setups are
uploaded to the EEPROM.
Note that, on the final upload sequence stored in the scratch pad,
the pause instruction (FE) must be replaced with an end instruction (FF).
To download a specific setup on demand, first store the condition
associated with the desired setup in Register 0x0E01, Bits[4:0].
Then perform an EEPROM download (Register 0x0E03, Bit 1).
Alternatively, to download a specific setup at power-up, apply
the required logic levels necessary to encode the desired condition
on the M3 to M7 multifunction pins. Then power up the device,
and an automatic EEPROM download occurs. The condition
(as established by the M3 to M7 multifunction pins) guides the
download sequence and results in a specific setup.
Keep in mind that the number of setups that can be stored in the
EEPROM is limited. The EEPROM can hold a total of 2048 bytes.
Each nondata instruction requires one byte of storage. Each data
instruction, however, requires N + 4 bytes of storage, where N
is the number of transferred register bytes. The other four bytes
include the data instruction itself (one byte), the target address
(two bytes), and the checksum calculated by the EEPROM controller during the upload sequence (one byte).
Condition instruction (0xB1 to 0xCF) to identify the
setup with a specific condition (1 to 31)
Data instructions (to save the register contents) along
with any required calibrate and/or I/O update
instructions
Pause instruction (0xFE)
Rev. 0 | Page 49 of 104
AD9547
SERIAL CONTROL PORT
SERIAL CONTROL ARBITER
13-BIT ADDRESS
SPACE
SPI
READ-ONLY
REGION
I2C
EEPROM
EEPROM
CONTROLLER
400kHz
M7
M6
M5
M4
M3
M2
M1
M0
MULTIFUNCTION
PIN CONTROL
LOGIC
READ/WRITE
REGION
ANALOG BLOCKS AND
DIGITAL CORE
08300-026
SCLK/SCL
CS/SDA
SDIO
SDO
POWER-ON RESET
Figure 49. Serial Port Functional Diagram
The AD9547 serial control port is a flexible, synchronous serial
communications port that provides a convenient interface to many
industry-standard microcontrollers and microprocessors. The
AD9547 serial control port is compatible with most synchronous
transfer formats, including Philips I2C, Motorola® SPI, and
Intel® SSR protocols. The serial control port allows read/write
access to the AD9547 register map.
In SPI mode, single or multiple byte transfers are supported.
The SPI port configuration is programmable via Register 0x0000.
This register is integrated into the SPI control logic rather than
the register map and is distinct from the I2C Register 0x0000.
It is also inaccessible to the EEPROM controller.
A functional diagram of the serial control port, including its
relationship to the EEPROM, appears in Figure 49.
Although the AD9547 supports both the SPI and I2C serial port
protocols, only one is active following power-up (as determined
by the multifunction pins, M0 to M2, during the startup sequence).
That is, the only way to change the serial port protocol is to reset
the device (or cycle the device power supply). Both protocols
use a common set of control pins as shown in Figure 50.
2
AD9547
SDIO
3
SDO
4
SERIAL
CONTROL
PORT
CS/SDA
5
Figure 50. Serial Control Port
Because the AD9547 supports both the SPI and I2C protocols,
the active serial port protocol depends on the logic state of the
three multifunction pins, M0 to M2, at startup. If all three pins
are set to Logic 0 at startup, the SPI protocol is active. Otherwise,
the I2C protocol is active with seven different I2C slave address
settings that are based on the startup logic pattern on the M0 to
M2 pins (see Table 29). Note that the four MSBs of the slave
address are hardware coded as 1001.
Table 29. Serial Port Mode Selection
M2
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
Serial Port Mode
SPI
I²C (address = 1001001)
I²C (address = 1001010)
I²C (address = 1001011)
I²C (address = 1001100)
I²C (address = 1001101)
I²C (address = 1001110)
I²C (address = 1001111)
SPI SERIAL PORT OPERATION
Pin Descriptions
08300-027
SCLK/SCL
SPI/I2C PORT SELECTION
The SCLK (serial clock) pin (SCLK/SCL) serves as the serial
shift clock. This pin is an input. SCLK synchronizes serial
control port read and write operations. The rising edge SCLK
registers write data bits, and the falling edge registers read data
bits. The SCLK pin supports a maximum clock rate of 40 MHz.
The SDIO (serial data input/output) pin is a dual-purpose pin
and acts either as an input only (unidirectional mode) or as both
an input and an output (bidirectional mode). The AD9547
default SPI mode is bidirectional.
The SDO (serial data out) pin is useful only in unidirectional
I/O mode. It serves as the data output pin for read operations.
The CS (chip select) pin (CS/SDA) is an active low control that
gates read and write operations. This pin is internally connected
to a 30 kΩ pull-up resistor. When CS is high, the SDO and
SDIO pins go into a high impedance state.
Rev. 0 | Page 50 of 104
AD9547
SPI Mode Operation
Write
The SPI port supports both 3-wire (bidirectional) and 4-wire
(unidirectional) hardware configurations and both MSB-first
and LSB-first data formats. Both the hardware configuration
and data format features are programmable. By default, the
AD9547 uses the bidirectional MSB-first mode. The bidirectional
mode is the default mode so that the user can still write to the
device to switch to unidirectional mode, if it is wired for
unidirectional operation.
If the instruction word indicates a write operation, the payload
is written into the serial control port buffer of the AD9547. Data
bits are registered on the rising edge of SCLK. The length of the
transfer (1, 2, or 3 bytes or streaming mode) depends on the W0
and W1 bits (see Table 30) in the instruction byte. When not
streaming, CS can be deasserted after each sequence of eight
bits to stall the bus (except after the last byte, where it ends the
cycle). When the bus is stalled, the serial transfer resumes when
CS is asserted. Deasserting the CS pin on a nonbyte boundary
resets the serial control port. Reserved or blank registers are not
skipped over automatically during a write sequence. Therefore,
the user must know what bit pattern to write to the reserved
registers to preserve proper operation of the part. Generally, it
does not matter what data is written to blank registers, but it is
customary to write 0s.
Assertion (active low) of the CS pin initiates a write or read
operation to the AD9547 SPI port. For data transfers of three
bytes or fewer (excluding the instruction word), the device
supports the CS stalled high mode (see Table 30). In this mode,
the CS pin can be temporarily deasserted on any byte boundary,
allowing time for the system controller to process the next byte.
CS can be deasserted only on byte boundaries, however. This
applies to both the instruction and data portions of the transfer.
Table 30. Byte Transfer Count
W1
0
0
1
1
W0
0
1
0
1
Bytes to Transfer
1
2
3
Streaming mode
During stall high periods, the serial control port state machine
enters a wait state until all data is sent. If the system controller
decides to abort a transfer midstream, the state machine must be
reset either by completing the transfer or by asserting the CS
pin for at least one complete SCLK cycle (but less than eight
SCLK cycles). Deasserting the CS pin on a nonbyte boundary
terminates the serial transfer and flushes the buffer.
In streaming mode (see Table 30), any number of data bytes can
be transferred in a continuous stream. The register address is
automatically incremented or decremented. CS must be deasserted at the end of the last byte transferred, thereby ending the
stream mode.
Communication Cycle—Instruction Plus Data
The SPI protocol consists of a two-part communication cycle.
The first part is a 16-bit instruction word that is coincident with
the first 16 SCLK rising edges and a payload. The instruction word
provides the AD9547 serial control port with information regarding the payload. The instruction word includes the R/W bit that
indicates the direction of the payload transfer (that is, a read or
write operation). The instruction word also indicates the number
of bytes in the payload and the starting register address of the
first payload byte.
Most of the serial port registers are buffered. Refer to the
Buffered/Active Registers section for details on the difference
between buffered and active registers. Therefore, data written
into buffered registers does not immediately take effect. An additional operation is needed to transfer buffered serial control port
contents to the registers that actually control the device. This is
accomplished with an I/O update operation that is performed
in one of two ways: by writing a Logic 1 to Register 0x0005, Bit 0
(this bit is self-clearing) or by using an external signal via an
appropriately programmed multifunction pin. The user can
change as many register bits as desired before executing an I/O
update. The I/O update operation transfers the buffer register
contents to their active register counterparts.
Read
The AD9547 supports the long instruction mode only. If the
instruction word indicates a read operation, the next N × 8
SCLK cycles clock out the data from the address specified in the
instruction word. N is the number of data bytes read and depends
on the W0 and W1 bits of the instruction word. The readback
data is valid on the falling edge of SCLK. Blank registers are not
skipped over during readback.
A readback operation takes data from either the serial control
port buffer registers or the active registers, as determined by
Register 0x0004, Bit 0.
Rev. 0 | Page 51 of 104
AD9547
SPI Instruction Word (16 Bits)
When Register 0x0000, Bit 6 = 1 (LSB first), the instruction and
data bytes must be written from LSB to MSB. Multibyte data transfers in LSB-first format start with an instruction byte that includes
the register address of the least significant payload byte, followed
by multiple data bytes. The serial control port internal byte address
generator increments for each byte of the multibyte transfer cycle.
The MSB of the 16-bit instruction word is R/W, which indicates
whether the instruction is a read or a write. The next two bits, W1
and W0, indicate the number of bytes in the transfer (see Table 30).
The final 13 bits are the register address (A12 to A0), which indicates the starting register address of the read/write operation
(see Table 32).
For multibyte MSB-first (default) I/O operations, the serial control
port register address decrements from the specified starting address
toward Address 0x0000. For multibyte LSB-first I/O operations,
the serial control port register address increments from the starting
address toward Address 0x1FFF. Unused addresses are not skipped
during multibyte I/O operations; therefore, the user should
write the default value to a reserved register and 0s to unmapped
registers. Note that it is more efficient to issue a new write
command than to write the default value to more than two
consecutive reserved (or unmapped) registers.
SPI MSB/LSB First Transfers
The AD9547 instruction word and payload can be MSB first or
LSB first. The default for the AD9547 is MSB first. The LSB-first
mode can be set by writing a 1 to Register 0x0000, Bit 6. Immediately after the LSB-first bit is set, subsequent serial control port
operations are LSB first.
When MSB-first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB-first format start with an instruction byte that includes the
register address of the most significant payload byte. Subsequent
data bytes must follow in order from high address to low address.
In MSB-first mode, the serial control port internal address
generator decrements for each data byte of the multibyte
transfer cycle.
Table 31. Streaming Mode (No Addresses Are Skipped)
Write Mode
LSB First
MSB First
Address Direction
Increment
Decrement
Stop Sequence
0x0000 ... 0x1FFF
0x1FFF ... 0x0000
Table 32. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
LSB
I0
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CS
SCLK DON'T CARE
SDIO DON'T CARE
R/W W1 W0 A12 A11 A10 A9
A8
A7
A6 A5
A4 A3 A2
A1 A0
D7 D6 D5
16-BIT INSTRUCTION HEADER
D4 D3
D2 D1
D0
REGISTER (N) DATA
D7
D6 D5
D4 D3 D2
D1 D0
DON'T CARE
REGISTER (N – 1) DATA
08300-029
DON'T CARE
Figure 51. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data
CS
SCLK
DON'T CARE
SDIO
DON'T CARE
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
SDO DON'T CARE
REGISTER (N) DATA
REGISTER (N – 1) DATA
REGISTER (N – 2) DATA
REGISTER (N – 3) DATA
DON'T
CARE
Figure 52. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes of Data
tDS
tS
CS
DON'T CARE
SDIO
DON'T CARE
tC
tCLK
tLOW
DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
Figure 53. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
Rev. 0 | Page 52 of 104
D0
DON'T CARE
08300-031
SCLK
tHIGH
tDH
08300-030
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
16-BIT INSTRUCTION HEADER
AD9547
CS
SCLK
DATA BIT N
08300-032
tDV
SDIO
SDO
DATA BIT N – 1
Figure 54. Serial Control Port Timing—Read
CS
SCLK DON'T CARE
A0 A1 A2 A3
A4
A5 A6
A7
A8
A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4
16-BIT INSTRUCTION HEADER
D5 D6
REGISTER (N) DATA
D7
D0
D1 D2
D3 D4 D5
D6
D7
REGISTER (N + 1) DATA
Figure 55. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data
CS
tS
tC
tCLK
tHIGH
tLOW
tDS
SCLK
BIT N
BIT N + 1
Figure 56. Serial Control Port Timing—Write
Table 33. Serial Control Port Timing
Parameter
tDS
tDH
tCLK
tS
tC
tHIGH
tLOW
tDV
Description
Setup time between data and the rising edge of SCLK
Hold time between data and the rising edge of SCLK
Period of the clock
Setup time between the CS falling edge and SCLK rising edge (start of the communication cycle)
Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle)
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
SCLK to valid SDIO and SDO (see Figure 54)
Rev. 0 | Page 53 of 104
08300-034
tDH
SDIO
DON'T CARE
08300-033
SDIO DON'T CARE
DON'T CARE
AD9547
The transfer of data appears graphically in Figure 57. One clock
pulse is generated for each data bit transferred. The data on the
SDA line must be stable during the high period of the clock.
The high or low state of the data line can change only when the
clock signal on the SCL line is low.
I²C SERIAL PORT OPERATION
The I2C interface has the advantage of requiring only two
control pins and is a de facto standard throughout the I2C
industry. However, its disadvantage is programming speed,
which is 400 kbps maximum. The AD9547 I2C port design is
based on the I2C fast mode standard from Philips, so it supports
both the 100 kHz standard mode and the 400 kHz fast mode.
Fast mode imposes a glitch tolerance requirement on the control
signals; that is, the input receivers ignore pulses of less than
50 ns duration.
SDA
SCL
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
08300-035
The AD9547 I2C port consists of a serial data line (SDA) and
a serial clock line (SCL). In an I2C bus system, the AD9547 is
connected to the serial bus (data bus SDA and clock bus SCL)
as a slave device; that is, no clock is generated by the AD9547.
The AD9547 uses direct 16-bit memory addressing instead of
traditional 8-bit memory addressing.
Figure 57. Valid Bit Transfer
Start/stop functionality appears graphically in Figure 58. The
start condition is characterized by a high-to-low transition on
the SDA line while SCL is high. The start condition is always
generated by the master to initialize data transfer. The stop
condition is characterized by a low-to-high transition on the
SDA line while SCL is high. The stop condition is always
generated by the master to terminate data transfer.
The AD9547 allows for up to seven unique slave devices to occupy
the I2C bus. These are accessed via a 7-bit slave address that is
transmitted as part of an I2C packet. Only the device with a matching slave address responds to subsequent I2C commands. The
device slave address is 1001xxx (the last three bits are determined
by the M0 to M2 pins). The four MSBs (1001) are hardwired,
whereas the three LSBs (xxx, determined by the M0 to M2 pins)
are programmable via the power-up state of the multifunction
pins (see the Initial M0 to M7 Pin Programming section).
SCL
S
P
START CONDITION
I2C Bus Characteristics
STOP CONDITION
Figure 58. Start and Stop Condition
A summary of the various I2C protocols appears in Table 34.
Every byte on the SDA line must be eight bits long. Each byte
must be followed by an acknowledge bit. Bytes are sent MSB first.
Table 34. I2C Bus Abbreviation Definitions
Abbreviation
Definition
S
Start
The acknowledge bit (A) is the ninth bit attached to any 8-bit
data byte. An acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has been received. It is done by pulling the SDA line low
during the ninth clock pulse after each 8-bit data byte.
Sr
Repeated start
P
Stop
A
Acknowledge
A
No acknowledge
W
Write
R
Read
The no acknowledge bit (A) is the ninth bit attached to any 8-bit
data byte. A no acknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the
byte has not been received. It is done by leaving the SDA line
high during the ninth clock pulse after each 8-bit data byte.
MSB
ACK FROM
SLAVE RECEIVER
1
SCL
2
3 TO 7
8
9
ACK FROM
SLAVE RECEIVER
1
S
Figure 59. Acknowledge Bit
Rev. 0 | Page 54 of 104
2
3 TO 7
8
9
10
P
08300-037
SDA
08300-036
SDA
AD9547
bytes immediately after the slave address byte are the internal
memory (control registers) address bytes with the high address
byte first. This addressing scheme gives a memory address up to
216 − 1 = 65,535. The data bytes after these two memory address
bytes are register data written into or read from the control registers. In read mode, the data bytes after the slave address byte are
register data written into or read from the control registers.
Data Transfer Process
The master initiates data transfer by asserting a start condition.
This indicates that a data stream follows. All I2C slave devices
connected to the serial bus respond to the start condition.
The master then sends an 8-bit address byte over the SDA line,
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 =
write, 1 = read).
When all data bytes are read or written, stop conditions are established. In write mode, the master (transmitter) asserts a stop
condition to end data transfer during the 10th clock pulse following
the acknowledge bit for the last data byte from the slave device
(receiver). In read mode, the master device (receiver) receives the
last data byte from the slave device (transmitter) but does not pull
SDA low during the ninth clock pulse. This is known as a no
acknowledge bit. When receiving the no acknowledge bit, the slave
device knows the data transfer is finished and enters idle mode.
The master then takes the data line low during the low period
before the 10th clock pulse, and high during the 10th clock pulse
to assert a stop condition.
The peripheral whose address corresponds to the transmitted
address responds by sending an acknowledge bit. All other devices
on the bus remain idle while the selected device waits for data to be
read from or written to it. If the R/W bit = 0, the master (transmitter) writes to the slave device (receiver). If the R/W bit = 1,
the master (receiver) reads from the slave device (transmitter).
See the Data Transfer Format section for the command format.
Data is then sent over the serial bus in the format of nine clock
pulses, one data byte (eight bits) from either master (write mode)
or slave (read mode) followed by an acknowledge bit from the
receiving device. The number of bytes that can be transmitted
per transfer is unrestricted. In write mode, the first two data
A start condition can be used in place of a stop condition.
Furthermore, a start or stop condition can occur at any time,
and partially transferred bytes are discarded.
MSB
ACK FROM
SLAVE RECEIVER
1
SCL
3 TO 7
2
8
9
ACK FROM
SLAVE RECEIVER
1
3 TO 7
2
8
9
10
S
P
08300-038
SDA
Figure 60. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration)
SDA
ACK FROM
MASTER RECEIVER
1
3 TO 7
2
8
9
1
3 TO 7
2
8
9
10
S
P
08300-039
SCL
NO ACK FROM
MASTER RECEIVER
Figure 61. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration)
Data Transfer Format
In write byte format, the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.
S
Slave
Address
A
W
RAM Address
High Byte
A
RAM Address
Low Byte
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
A
P
In send byte format, the send byte protocol is used to set up the register address for subsequent reads.
S
Slave Address
W
A
RAM Address High Byte
A
RAM Address Low Byte
A
P
In receive byte format, the receive byte protocol is used to read the data bytes from RAM starting from the current address.
S
Slave Address
R
A
RAM Data 0
A
RAM Data 1
A
RAM Data 2
P
A
Read byte format combines the format of the send byte and the receive byte formats.
S
Slave
Address
W
A
RAM
Address
High Byte
A
RAM
Address
Low Byte
A
Sr
Slave
Address
Rev. 0 | Page 55 of 104
R
A
RAM
Data
0
A
RAM
Data
1
A
RAM
Data
2
A
P
AD9547
I²C Serial Port Timing
SDA
tLOW
tF
tR
tSU;DAT
tHD;STA
tSP
tBUF
tR
tF
tHD;STA
S
tHD;DAT
tHIGH
tSU;STO
tSU;STA
Sr
Figure 62. I²C Serial Port Timing
Table 35. I2C Timing Definitions
Parameter
fSCL
tBUF
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tSU;DAT
tLOW
tHIGH
tR
tF
tSP
Description
Serial clock
Bus free time between stop and start conditions
Repeated hold time start condition
Repeated start condition setup time
Stop condition setup time
Data hold time
Data setup time
SCK clock low period
SCK clock high period
Minimum/maximum receive SCL and SDA rise time
Minimum/maximum receive SCL and SDA fall time
Pulse width of voltage spikes that must be suppressed by the input filter
Rev. 0 | Page 56 of 104
P
S
08300-040
SCL
AD9547
BUFFERED/ACTIVE REGISTERS
There are two broad categories of registers on the AD9547:
buffered and active (see Figure 63). Buffered registers are those
that can be written to directly from the serial port. They do
not need an I/O update to apply their contents to the internal
device functions. In contrast, active registers require an I/O
update to transfer data between the buffered registers and
the internal device functions. In operation, the user programs
as many buffered registers as desired and then issues an I/O
update. The I/O update is performed by writing to Register
0x0005, Bit 0 = 1 (or by the external application of the necessary logic level to one of the multifunction pins previously
programmed as an I/O update input). The contents of the
buffered registers that are connected directly to the internal
device functions affect those functions immediately. The
contents of buffered registers that connect to active registers
do not affect the internal device functions until the I/O
update event occurs.
An S or C in the Opt column of the register map identifies
an active register (otherwise, it is a buffered register). An S
entry means that the I/O update signal to the active register is
synchronized with the serial port clock or with an input signal
driving one of the multifunction pins. On the other hand, a
C entry means that the I/O update signal to the active register
is synchronized with a clock signal derived from the internal
system clock (fS/32), as shown in Figure 63.
When reading back a register that has both buffered and
active contents, Register 0x0004, Bit 0 can be used to select
whether to read back the buffered or active contents. Readback of the active contents occurs when Register 0x0004, Bit 0
= 0, whereas readback of the buffered contents occurs when
Register 0x0004, Bit 0 = 1. Note that a read-only active register
requires an I/O update before its contents can be read.
EDGE
DETECT
5
SDIO
3
SDO
4
SCLK/SCL
2
08300-041
CS/SDA
TO INTERNAL DEVICE FUNCTIONS
SERIAL
CONTROL
PORT
ACTIVE C
REGISTERS
fS/32
ACTIVE S
REGISTERS
In general, when a group of registers defines a control parameter, the LSB of the value resides in the D0 position of the
register with the lowest address. The bit weight increases from
right to left, from the lowest register address to the highest
register address. For example, the default value of the incremental phase lock offset step size register (Address 0x0314
to Address 0x0315) is the 16-bit hexadecimal number, 0x03E8
(not 0xE803). Note that the EEPROM storage sequence registers (Address 0x0E10 to Address 0x0E3F) are an exception
to this convention (see the EEPROM Instructions section).
FROM
MULTIFUNCTION
PIN LOGIC
BUFFERED REGISTERS
The register map spans an address range from 0x0000 through
0x0E3F (0 to 3647, decimal). Each address provides access to
one byte (eight bits) of data. Each individual register is identified by its four-digit hexadecimal address (for example,
Register 0x0A10). In some cases, a group of addresses
collectively define a register (for example, the IRQ mask
register consists of Register 0x0209, Register 0x020A,
Register 0x020B, Register 0x020C, Register 0x020D,
Register 0x020E, Register 0x020F, and Register 0x0210).
I/O UPDATE
I/O PROGRAMMING REGISTERS
Figure 63. Buffered and Active Registers
AUTOCLEARING REGISTERS
An A in the Opt column of the register map identifies an autoclearing register. Typically, the active value for an autoclearing
register takes effect following an I/O update. The bit is cleared by
the internal device logic upon completion of the prescribed action.
REGISTER ACCESS RESTRICTIONS
Read and write access to the registers may be restricted, depending
on the register in question, the source and direction of access,
and the current state of the device. Each register can be classified
into one or more access types. When more than one type applies,
the most restrictive condition that applies at that time is used.
When access is denied to a register, all attempts to read the register
return a 0 byte, and all attempts to write to the register are ignored.
Access to nonexistent registers is handled in the same way as for
a denied register.
Regular Access
Registers with regular access do not fall into any other category.
Both read and write access to registers of this type can be from
the serial port or the EEPROM controller. However, only one of
these sources can have access to a register at any given time (access
is mutually exclusive). When the EEPROM controller is active,
either in load or store mode, it has exclusive access to the registers.
Read-Only Access
An R in the Opt column of the register map identifies read-only
registers. Access is available at all times, including when the
EEPROM controller is active.
Exclusion from EEPROM Access
An E in the Opt column of the register map identifies a register
with contents that are inaccessible to the EEPROM. That is, the
contents of this type of register cannot be transferred directly to
the EEPROM or vice versa. Note that read-only registers (R) are
inaccessible to the EEPROM, as well.
Rev. 0 | Page 57 of 104
AD9547
REGISTER MAP
The register addresses and defaults are hexadecimal values. Use the default value when writing to registers and/or bits marked as unused.
Table 36.
Addr
Opt 1
Name
D7
D6
Serial Port Configuration and Part Identification
0x0000
E
SPI control
UnidirecLSB first/
tional
IncAddr
0x0000
Dup
I2C control
Unused
0x0001
E
Reserved
0x0002
R
Silicon
revision level
0x0003
R
Device ID
0x0004
E
Register
readback
0x0005
A, E
I/O update
System Clock (SYSCLK)
0x0100
S
Charge pump/
External
Charge
lock detect
loop filter
pump
control
enable
mode
(auto/man)
0x0101
S
N divider
0x0102
S
Unused
System clock
M divider
input options
reset
0x0103
C
Nominal
system clock
0x0104
C
period
0x0105
C
0x0106
C
System clock
stability
0x0107
C
period
0x0108
C
General Configuration
0x0200
S
M0 control
0x0201
S
M1 control
0x0202
S
M2 control
0x0203
S
M3 control
0x0204
S
M4 control
0x0205
S
M5 control
0x0206
S
M6 control
0x0207
S
M7 control
0x0208
C
IRQ pin
output mode
0x0209
C
IRQ mask
D5
D4
Soft reset
Long
instruction
D3
D2
D1
Unused
Soft reset
Unused
0x00
0x01
Device ID
Unused
Read buffer
register
I/O update
Unused
Charge pump current[2:0]
Lock detect
timer
disable
N divider[7:0]
PLL enable
2×
frequency
multiplier
enable
Nominal SYSCLK period[15:0] (in fs)
(1 ns at 1 ppm accuracy)
M divider[1:0]
SYSCLK source[1:0]
0x28
0x45
M0 function[6:0]
M1 function[6:0]
M2 function[6:0]
M3 function[6:0]
M4 function[6:0]
M5 function[6:0]
M6 function[6:0]
M7 function[6:0]
Unused
Unused
SYSCLK
unlocked
Unused
0x020A
C
0x020B
C
0x020C
C
0x020D
C
Ref AA
new profile
Ref AA
validated
Ref AA fault
cleared
0x020E
C
Ref BB
new profile
Ref BB
validated
Ref BB
fault
cleared
0x020F
0x0210
0x0211
0x0212
0x0213
0x0214
C
C
C
C
S
S
Closed
Free run
Unused
SYSCLK
locked
Holdover
History
updated
Ref AA fault
Ref BB
fault
IRQ pin output mode[1:0]
Unused
Distribution
sync
Frequency
unlocked
Frequency
unclamped
Ref A
new profile
Watchdog
timer
Frequency
locked
Frequency
clamped
Ref A
validated
Ref B
new profile
Ref B
validated
SYSCLK cal
complete
EEPROM
fault
Phase
unlocked
Phase slew
unlimited
Ref A
fault
cleared
Ref B
fault
cleared
DAC current
DAC
shutdown
DAC full-scale current[7:0]
Unused
Rev. 0 | Page 58 of 104
0x40
0x42
0x0F
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
SYSCLK cal
started
EEPROM
complete
Phase
locked
Phase slew
limited
Ref A
fault
0x00
Ref B
fault
0x00
Unused
Unused
Watchdog timer [15:0] (in ms up to 65,535 ms)
Watchdog
timer
0x00
0x18
System clock stability period[19:16] (in ms)
M0 in/out
M1 in/out
M2 in/out
M3 in/out
M4 in/out
M5 in/out
M6 in/out
M7 in/out
0x31
0x00
Lock detect timer[1:0]
Nominal SYSCLK period[20:16]
SYSCLK stability period[15:0] (in ms)
Unused
Def
0x10
Unused
Silicon revision number
Unused
Switching
D0
DAC full-scale current[9:8]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0x01
AD9547
Addr
DPLL
0x0300
0x0301
0x0302
0x0303
0x0304
0x0305
0x0306
0x0307
0x0308
0x0309
0x030A
0x030B
0x030C
0x030D
0x030E
0x030F
0x0310
0x0311
0x0312
0x0313
0x0314
0x0315
Opt 1
Name
C
C
C
C
C
C
A, C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
Free-running
frequency
tuning word
Free-running frequency tuning word[47:0]
Update TW
Pull-in range
lower limit
Unused
Pull-in range lower limit[23:0]
Pull-in range
upper limit
Pull-in range upper limit[23:0]
Open-loop
phase offset
Open-loop phase offset word[15:0]
Fixed closedloop phase
lock offset
Fixed phase lock offset[39:0] (in ps; signed)
Incremental phase lock offset step size[15:0] (in ps/step)
0x0316
0x0317
0x0318
0x0319
0x031A
0x031B
C
C
C
C
C
C
Incremental
closed-loop
phase lock
offset step size
Phase slew
rate limit
History
accumulation
timer
History accumulation timer[23:0] (in ms)
D7
History mode
Clock Distribution Output Configuration
0x0400
S
Distribution
settings
0x0401
S
0x0402
S
0x0403
C
0x0404
S
0x0405
S
0x0406
0x0407
0x0408
0x0409
0x040A
0x040B
0x040C
0x040D
0x040E
0x040F
S
S
S
S
S
S
S
S
S
S
Distribution
enable
Distribution
synchronization
Automatic
synchronization
Distribution
channel
modes
D6
D5
D4
D3
D2
D1
D0
Update TW
Phase slew rate limit[15:0] (in ns/sec)
Unused
Unused
Unused
Single
sample
fallback
Persistent
history
Unused
External
Receiver
distribution
mode
resistor
Unused
Sync source[1:0]
Unused
Unused
Unused
Unused
Unused
OUT0
CMOS
phase invert
OUT1
CMOS
phase invert
OUT0
polarity
invert
OUT1
polarity
invert
OUT0
drive
strength
OUT1
drive
strength
Unused
Q0[23:0]
Distribution
channel
divider, Q0
Unused
Q0[29:24]
Q1[23:0]
Distribution
channel
divider, Q1
Unused
Q1[29:24]
Rev. 0 | Page 59 of 104
Incremental average[2:0]
Def
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xE8
0x03
0x00
0x00
0x30
0x75
0x00
0x00
0x0C
OUT1
OUT0
powerpowerdown
down
OUT1
OUT0
enable
enable
OUT1
OUT0
sync mask
sync mask
Automatic sync mode[1:0]
0x00
OUT0 mode
0x03
OUT1 mode
0x03
0x00
0x00
0x03
0x03
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
AD9547
Addr
Opt 1
Name
0x0410
S
Reserved
0x0411
S
0x0412
S
0x0413
S
0x0414
S
0x0415
S
0x0416
S
0x0417
S
Reference Input Configuration
0x0500
S
Reference
power-down
0x0501
0x0502
0x0503
S
S
C
0x0504
C
0x0505
0x0506
0x0507
C
C
C
Reference
logic family
Manual
reference
profile
selection
Phase buildout switching
Profile Registers—Profile 0
0x0600
Priorities
0x0601
Reference
period
0x0602
0x0603
0x0604
0x0605
0x0606
0x0607
0x0608
Tolerance
0x0609
0x060A
0x060B
0x060C
0x060D
0x060E
Validation
timer
0x060F
0x0610
Redetect
timer
0x0611
0x0612
0x0613
0x0614
0x0615
0x0616
0x0617
0x0618
0x0619
0x061A
0x061B
0x061C
0x061D
D7
D6
D5
D4
D3
Unused
D2
D1
D0
Unused
Ref BB
Ref B
Ref AA
Ref A
powerpowerpowerpowerdown
down
down
down
Ref BB logic family[1:0]
Ref B logic family[1:0]
Ref AA logic family[1:0]
Ref A logic family[1:0]
Unused
Ref AA manual profile[2:0]
Ref A manual profile[2:0]
Enable
Enable Ref A
Ref AA
manual
manual
profile
profile
Ref BB manual profile[2:0]
Ref B manual profile[2:0]
Enable
Enable Ref B
Ref BB
manual
manual
profile
profile
Unused
Unused
Unused
Phase master threshold priority[2:0]
Unused
Promoted priority[2:0]
Nominal reference period[39:0] (in fs up to 1.1 ms)
Selection priority[2:0]
Unused (write 0s to these bits)
Inner tolerance[15:0] (1/tolerance) (removes fault status; 10% down to 1 ppm)
Unused
Inner tolerance[19:16]
Outer tolerance[15:0] (1/tolerance) (indicates fault status; 10% down to 1 ppm)
Unused
Outer tolerance[19:16]
Validation timer[15:0] (in ms up to 65,535 ms)
Redetect timer[15:0] (in ms up to 65,535 ms)
Alpha-0 linear[15:0]
Digital loop
filter coefficients
Alpha-2 exponent[1:0]
Alpha-1 exponent[5:0]
Beta-0 linear[6:0]
Alpha-2
exponent[2]
Beta-0 linear[14:7]
Beta-1 exponent[4:0]
Gamma-0 linear[15:0]
Unused
Unused
Beta-0 linear[16:15]
Gamma-1 exponent[4:0]
Delta-0 linear[7:0]
Delta-0 linear[14:8]
Delta-1
exponent[0]
Alpha-3 exponent[3:0]
Rev. 0 | Page 60 of 104
Gamma-0
linear[16]
Def
0xF0
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Delta-1 exponent[4:1]
0x00
AD9547
Addr
Opt 1
Name
0x061E
R divider
0x061F
0x0620
0x0621
0x0622
S divider
0x0623
0x0624
0x0625
0x0626
Fractional
feedback
0x0627
divider
0x0628
0x0629
Lock
detectors
0x062A
0x062B
0x062C
0x062D
0x062E
0x062F
0x0630
0x0631
Profile Registers—Profile 1
0x0632
Priorities
0x0633
Reference
period
0x0634
0x0635
0x0636
0x0637
0x0638
0x0639
0x063A
0x063B
0x063C
0x06CD
0x063E
0x063F
0x0640
0x0641
0x0642
0x0643
0x0644
0x0645
0x0646
0x0647
0x0648
0x0649
0x064A
0x064B
0x064C
0x064D
0x064E
0x064F
D7
D6
D5
D4
D3
R[23:0]
Unused
D2
D1
D0
R[29:24]
S[15:0]
Unused
S[19:16]
Unused
V[7:0]
U[3:0]
Unused
U[9:4]
Phase lock threshold[15:0] (in ps)
Unused
V[9:8]
Phase lock fill rate[7:0]
Phase lock drain rate[7:0]
Frequency lock threshold[23:0] (in ps)
Frequency lock fill rate[7:0]
Frequency lock drain rate[7:0]
Unused
Promoted priority[2:0]
Selection priority[2:0]
Nominal reference period[39:0] (in units of fs up to 1.1 ms)
Unused (write 0s to these bits)
Tolerance
Inner tolerance[15:0] (1/tolerance) (removes fault status; 10% down to 1 ppm)
Unused
Inner tolerance[19:16]
Outer tolerance[15:0] (1/tolerance) (indicates fault status; 10% down to 1 ppm)
Unused
Validation
timer
Redetect timer[15:0] (in units of ms up to 65.5 sec)
Redetect
timer
Digital loop
filter coefficients
Outer tolerance[19:16]
Validation timer[15:0] (in units of ms up to 65.5 sec)
Alpha-0 linear[15:0]
Alpha-2 exponent[1:0]
Alpha-1 exponent[5:0]
Beta-0 linear[6:0]
Beta-0 linear[14:7]
Beta-1 exponent[4:0]
Gamma-0 linear[15:0]
Unused
Unused
Alpha-2
exponent[2]
Beta-0 linear[16:15]
Gamma-1 exponent[4:0]
Gamma-0
linear[16]
Delta-0 linear[7:0]
Delta-0 linear[14:8]
Delta-1 exponent[0]
Alpha-3 exponent[3:0]
Rev. 0 | Page 61 of 104
Def
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Delta-1 exponent[4:1]
0x00
AD9547
Addr
Opt 1
Name
0x0650
R divider
0x0651
0x0652
0x0653
0x0654
S divider
0x0655
0x0656
0x0657
0x0658
Fractional
feedback
0x0659
divider
0x065A
0x065B
Lock
detectors
0x065C
0x065D
0x065E
0x065F
0x0660
0x0661
0x0662
0x0663
Unused
0x0664
to
0x067F
Profile Registers—Profile 2
0x0680
Priorities
0x0681
Reference
period
0x0682
0x0683
0x0684
0x0685
0x0686
0x0687
0x0688
0x0689
0x068A
0x068B
0x068C
0x068D
0x068E
0x068F
0x0690
0x0691
0x0692
0x0693
0x0694
0x0695
0x0696
0x0697
0x0698
0x0699
0x069A
0x069B
0x069C
0x069D
D7
D6
D5
D4
D3
R[23:0]
Unused
D2
D1
D0
R[29:24]
S[15:0]
Unused
S[19:16]
Unused
V[7:0]
U[3:0]
Unused
Unused
U[9:4]
Phase lock threshold[15:0] (in units of ps)
V[9:8]
Phase lock fill rate[7:0]
Phase lock drain rate[7:0]
Frequency lock threshold[23:0] (in ps)
Frequency lock fill rate[7:0]
Frequency lock drain rate[7:0]
Unused
Unused
Promoted priority[2:0]
Nominal period[39:0] (in units of fs up to 1.1 ms)
Selection priority[2:0]
Unused (write 0s to these bits)
Tolerance
Inner tolerance[15:0] (1/tolerance) (removes fault status; 10% down to 1 ppm)
Unused
Inner tolerance[19:16]
Outer tolerance[15:0] (1/tolerance) (indicates fault status; 10% down to 1 ppm)
Unused
Outer tolerance [19:16]
Validation timer[15:0] (ms) (up to 65,535 ms)
Validation
timer
Redetect timer[15:0] (ms) (up to 65,535 ms)
Redetect
timer
Digital loop
filter coefficients
Alpha-0 linear[15:0]
Alpha-2 exponent[1:0]
Alpha-1 exponent[5:0]
Beta-0 linear[6:0]
Beta-0 linear[14:7]
Beta-1 exponent[4:0]
Gamma-0 linear[15:0]
Unused
Unused
Alpha-2
exponent[2]
Beta-0 linear[16:15]
Gamma-1 exponent[4:0]
Gamma-0
linear[16]
Delta-0 linear[7:0]
Delta-0 linear[14:8]
Delta-1 exponent[0]
Alpha-3 exponent[3:0]
Rev. 0 | Page 62 of 104
Def
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Delta-1 exponent[4:1]
0x00
AD9547
Addr
Opt 1
Name
0x069E
R divider
0x069F
0x06A0
0x06A1
0x06A2
S divider
0x06A3
0x06A4
0x06A5
0x06A6
Fractional
feedback
0x06A7
divider
0x06A8
0x06A9
Lock
detectors
0x06AA
0x06AB
0x06AC
0x06AD
0x06AE
0x06AF
0x06B0
0x06B1
Profile Registers—Profile 3
0x06B2
Priorities
0x06B3
Reference
period
0x06B4
0x06B5
0x06B6
0x06B7
0x06B8
0x06B9
0x06BA
0x06BB
0x06BC
0x06BD
0x06BE
0x06BF
0x06C0
0x06C1
0x06C2
0x06C3
0x06C4
0x06C5
0x06C6
0x06C7
D6
D5
D4
D3
R[23:0]
Unused
D2
D1
D0
R[29:24]
S[15:0]
Unused
S[19:16]
Unused
V[7:0]
U[3:0]
Unused
U[9:4]
Phase lock threshold[15:0] (in ps)
Unused
V[9:8]
Phase lock fill rate[7:0]
Phase lock drain rate[7:0]
Frequency lock threshold[23:0] (in ps)
Frequency lock fill rate[7:0]
Frequency lock drain rate[7:0]
Unused
Promoted priority[2:0]
Nominal period[39:0] (in fs up to 1.1 ms)
Selection priority[2:0]
Unused (write 0s to these bits)
Tolerance
Inner tolerance[15:0] (1/tolerance) (removes fault status; 10% down to 1 ppm)
Unused
Inner tolerance[19:16]
Outer tolerance[15:0] (1/tolerance) (indicates fault status; 10% down to 1 ppm)
Unused
Validation
timer
Digital loop
filter coefficients
Outer tolerance[19:16]
Validation timer[15:0] (in ms up to 65,535 ms)
Redetect timer[15:0] (in ms up to 65,535 ms)
Redetect
timer
Alpha-0 linear[15:0]
Alpha-2 exponent[1:0]
Alpha-1 exponent[5:0]
Beta-0 linear[6:0]
0x06C8
0x06C9
0x06CA
0x06CB
0x06CC
Alpha-2 exponent[2]
Beta-0 linear[14:7]
Beta-1 exponent[4:0]
Gamma-0 linear[15:0]
Unused
Unused
0x06CD
0x06CE
0x06CF
0x06D0
0x06D1
0x06D2
0x06D3
D7
Beta-0 linear [16:15]
Gamma-1 exponent[4:0]
Delta-0 linear[7:0]
Delta-0 linear[14:8]
Delta-1 exponent[0]
Alpha-3 exponent[3:0]
R divider
Gamma-0
linear[16]
Unused
R[29:24]
Rev. 0 | Page 63 of 104
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Delta-1 exponent[4:1]
R[23:0]
Def
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
AD9547
Addr
Opt 1
Name
D7
D6
D5
D4
D3
D2
D1
D0
0x06D4
S divider
S[15:0]
0x06D5
0x06D6
Unused
S[19:16]
0x06D7
Unused
0x06D8
V[7:0]
Fractional
feedback
0x06D9
U[3:0]
Unused
V[9:8]
divider
0x06DA
Unused
U[9:4]
0x06DB
Phase lock threshold[15:0] (in ps)
Lock
detectors
0x06DC
Phase lock fill rate[7:0]
0x06D
D
0x06DE
Phase lock drain rate[7:0]
0x06DF
Frequency lock threshold[23:0] (in ps)
0x06E0
0x06E1
0x06E2
Frequency lock fill rate[7:0]
0x06E3
Frequency lock drain rate[7:0]
Unused
0x06E4
to
0x06FF
Profile Registers—Profile 4 through Profile 7
0x0700
Profile 4
The functionality of the Profile 4 through Profile 7 address locations (Address 0x0700 to Address 0x07FF) is identical to
to
through
that of the Profile 0 through Profile 3 address locations (Address 0x0600 to Address 0x06FF)
0x07FF
Profile 7
Operational Controls
0x0A00 S
Unused
General
Reset sans
SYSCLK
Reference
TDC
DAC
Dist
Full
power-down
regmap
powerpowerpowerpowerpowerpowerdown
down
down
down
down
down
0x0A01 C
Loop mode
Unused
User selection mode[1:0]
User
User
Unused
User reference
holdover
free run
(write a 0
selection[1:0]
to this bit)
0x0A02 S
Cal/sync
Unused
Sync
Calibrate
distribution
SYSCLK
0x0A03 A, C
Unused
Clear LF
Clear CCI
Reset
Clear phase
Reset auto
Reset
Reset
Reset
functions
accumulator
sync
TW history
all IRQs
watchdog
0x0A04 A, C
IRQ clearing
Unused
Unused
SYSCLK
SYSCLK
SYSCLK cal
SYSCLK cal
unlocked
locked
complete
started
0x0A05 A, C
Unused
DistribuWatchdog
EEPROM
EEPROM
tion sync
timer
fault
complete
0x0A06 A, C
Switching
Closed
Free run
Holdover
Frequency
Frequency
Phase
Phase
unlocked
locked
unlocked
locked
0x0A07 A, C
Unused
History
Frequency
Frequency
Phase slew
Phase slew
updated
unclamped
clamped
unlimited
limited
0x0A08 A, C
Ref AA
Ref AA
Ref AA fault Ref AA fault
Ref A
Ref A
Ref A
Ref A
new profile
validated
cleared
new profile
validated
fault cleared
fault
0x0A09 A, C
Ref BB
Ref BB
Ref BB
Ref BB
Ref B
Ref B
Ref B
Ref B
new profile
validated
fault cleared
fault
new profile
validated
fault cleared
fault
0x0A0A
A, C
Unused
0x0A0B A, C
Unused
0x0A0C
A, C
Unused
Incremental
Reset
Decrement
Increment
phase offset
phase offset
phase offset
phase offset
0x0A0D A, C
Unused
Detect BB
Detect B
Detect AA
Detect A
Reference
profile selection state
machine
startup
0x0A0E
A, C
Unused
Force
Force
Force
Force
Force
validation
Timeout BB
Timeout B
Timeout AA Timeout A
timeout
0x0A0F
C
Unused
Reference
Ref Mon
Ref Mon
Ref Mon
Ref Mon
monitor
Override BB Override B
Override AA
Override A
override
0x0A10 C
Unused
Reference
Ref Mon
Ref Mon
Ref Mon
Ref Mon
monitor
Bypass BB
Bypass B
Bypass AA
Bypass A
bypass
Rev. 0 | Page 64 of 104
Def
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
AD9547
Addr
Opt 1
Name
D7
D6
D5
D4
Status Readback (These registers are read only and are accessible during EEPROM transactions.)
0x0D00
R
EEPROM
Unused
0x0D01
R
SYSCLK
0x0D02
R
IRQ monitor
0x0D03
R
0x0D04
R
0x0D05
R
0x0D06
R
0x0D07
R
0x0D08
0x0D09
0x0D0A
R
R
R, C
0x0D0B
R, C
0x0D0C
R, C
0x0D0
D
R, C
0x0D0E
R, C
0x0D0F
R, C
Unused
Unused
Switching
SYSCLK
unlocked
Unused
Closed
Ref A input
reference
status
Ref AA input
reference
status
Ref B input
reference
status
Ref BB input
reference
status
Unused
E
A, E
Condition
Save
0x0E03
A, E
Load
EEPROM Storage Sequence
0x0E10
E
SYSCLK
settings
0x0E11
E
0x0E12
E
0x0E13
E
I/O update
0x0E14
E
SYSCLK
calibration
0x0E15
E
General
configuration
0x0E16
E
settings
0x0E17
E
0x0E18
E
DPLL settings
Distribution
sync
Holdover
Frequency
unlocked
History
Frequency
updated
unclamped
Ref AA fault
Ref A
new profile
Ref BB
Ref B
fault
new profile
Unused
Ref AA
new profile
Ref BB
new profile
Ref AA
validated
Ref BB
validated
Ref AA
fault cleared
Ref BB
fault cleared
Offset slew
limiting
Frequency
clamped
Profile
selected
Phase
build-out
History
available
Phase lock
Frequency
Loop
lock
switching
Active reference priority[2:0]
D0
Watchdog
timer
Frequency
locked
Frequency
clamped
Ref A
validated
Ref B
validated
Load in
progress
Cal
in progress
SYSCLK cal
complete
EEPROM
fault
Phase
unlocked
Phase slew
unlimited
Ref A
fault cleared
Ref B
fault cleared
Save in
progress
Lock
detected
SYSCLK cal
started
EEPROM
complete
Phase
locked
Phase slew
limited
Ref A
fault
Ref B
fault
Holdover
Active
Unused
Def
Free
running
Active reference[1:0]
Selected profile[2:0]
Valid
Fault
Fast
Slow
Profile
selected
Selected profile[2:0]
Valid
Fault
Fast
Slow
Profile
selected
Selected profile[2:0]
Valid
Fault
Fast
Slow
Profile
selected
Selected profile[2:0]
Valid
Fault
Fast
Slow
0x0D10
R, C
0x0D11
R, C
0x0D12
R, C
0x0D13
R, C
0x0D14
R, C
Holdover
history
0x0D15
R, C
0x0D16
R, C
0x0D17
R, C
0x0D18
R, C
0x0D19
R, C
Nonvolatile Memory (EEPROM) Control
0x0E00
Write protect
0x0E01
0x0E02
D1
Unused
SYSCLK
locked
Free run
D2
Fault
detected
Unused
Stable
Unused
DPLL status
D3
Unused
Tuning word history[47:0]
Unused
Half rate
mode
Condition value[4:0]
Unused
Unused
Unused
Load from
EEPROM
Data: 9 bytes
Address: 0x0100
Action: I/O update
Action: calibrate system clock
Data: 21 bytes
Address: 0x0200
Data: 28 bytes
Rev. 0 | Page 65 of 104
Write
enable
Save to
EEPROM
Unused
0x00
0x00
0x00
0x00
0x08
0x01
0x00
0x80
0xA0
0x14
0x02
0x00
0x1B
AD9547
Addr
0x0E19
0x0E1A
0x0E1B
0x0E1C
0x0E1D
0x0E1E
0x0E1F
0x0E20
0x0E21
0x0E22
0x0E23
0x0E24
0x0E25
0x0E26
0x0E27
0x0E28
0x0E29
0x0E2A
0x0E2B
0x0E2C
0x0E2D
0x0E2E
0x0E2F
0x0E30
0x0E31
0x0E32
0x0E33
0x0E34
to
0x0E3F
1
Opt 1
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
E
Name
D7
D6
D5
D4
D3
Address: 0x0300
Data: 26 bytes
Address: 0x0400
Clock
distribution
settings
I/O update
Reference
input settings
Action: I/O update
Data: 8 bytes
Address: 0x0500
Profile 0 and
Profile 1
settings
Data: 100 bytes
Address: 0x0600
Profile2 and
Profile 3
settings
Data: 100 bytes
Address: 0x0680
Profile 4 and
Profile 5
settings
Data: 100 bytes
Address: 0x0700
Profile 6 and
Profile 7
settings
Data: 100 bytes
Address: 0x0780
I/O update
Operational
control
settings
Action: I/O update
Data: 17 bytes
Address: 0x0A00
I/O update
End of data
Action: I/O update
Action: end of data
Continuation of scratch pad area
See the I/O Programming Registers section for an explanation of the Opt column.
Rev. 0 | Page 66 of 104
D2
D1
D0
Def
0x03
0x00
0x19
0x04
0x00
0x80
0x07
0x05
0x00
0x63
0x06
0x00
0x63
0x06
0x80
0x63
0x07
0x00
0x63
0x07
0x80
0x80
0x10
0x0A
0x00
0x80
0xFF
AD9547
REGISTER BIT DESCRIPTIONS
SERIAL PORT CONFIGURATION AND PART IDENTIFICATION (REGISTER 0x0000 TO REGISTER 0x0005)
Table 37. SPI Control/I2C Control
Address
0x0000
Bit
7
Bit Name
Unidirectional
6
LSB first/IncAddr
5
Soft reset
4
Long instruction
[3:0]
Unused
Description
Select SPI port SDO pin operating mode.
0 (default) = 3-wire.
1 = 4-wire (SDO pin enabled).
Bit order for SPI port.
0 (default) = most significant bit and byte first (multibyte transfers use incrementing address).
1 = least significant bit and byte first (multibyte transfers use decrementing address).
Device reset (invokes an EEPROM download if M[7:3] ≠ 0).
0 (default) = normal operation.
1 = reset.
16-bit mode (the only mode supported by the device). This bit is read only and reads back as
Logic 1.
Unused.
Table 38. Reserved Register
Address
0x0001
Bit
[7:0]
Bit Name
Unused
Description
Unused.
Table 39. Silicon Revision Level (Read Only)
Address
0x0002
Bit
[7:0]
Bit Name
Silicon revision number
Description
Default = 0x31 = 0b00110001.
Table 40. Device ID (Read Only)
Address
0x0003
Bit
[7:0]
Bit Name
Device ID
Description
Default = 0x48 = 0b01001000.
Table 41. Register Readback Control
Address
0x0004
Bit
[7:1]
0
Bit Name
Unused
Read buffered register
Description
Unused.
For buffered registers, serial port readback reads from actual (active) registers instead of from the
buffer.
0 (default) = reads values currently applied to the device’s internal logic.
1 = reads buffered values that take effect on the next assertion of the I/O update.
Table 42. Soft I/O Update
Address
0x0005
Bit
[7:1]
0
Bit Name
Unused
I/O update
Description
Unused.
Writing a 1 to this bit transfers the data in the serial I/O buffer registers to the device’s
internal control registers. This is an autoclearing bit.
Rev. 0 | Page 67 of 104
AD9547
SYSTEM CLOCK (SYSCLK) (REGISTER 0x0100 TO REGISTER 0x0108)
Table 43. Charge Pump and Lock Detect Control
Address
0x0100
Bit
7
Bit Name
External loop filter enable
6
Charge pump mode
[5:3]
Charge pump current
2
Lock detect timer disable
[1:0]
Lock detect timer
Description
Enables use of an external SYSCLK PLL loop filter.
0 (default) = internal loop filter.
1 = external loop filter.
Charge pump current control.
0 (default) = automatic.
1 = manual.
Selects charge pump current when Bit 6 = 1.
000 = 125 μA.
001 = 250 μA.
010 = 375 μA.
011 (default) = 500 μA.
100 = 625 μA.
101 = 750 μA.
110 = 875 μA.
111 = 1000 μA.
Enable the SYSCLK PLL lock detect timer.
0 (default) = enable.
1 = disable.
Select lock detect timer depth.
00 (default) = 128.
01 = 256.
10 = 512.
11 = 1024.
Table 44. N Divider
Address
0x0101
Bit
[7:0]
Bit Name
N divider
Description
System clock PLL feedback divider value: 6 ≤ N ≤ 255 (default = 0x28 = 40).
Table 45. System Clock Input Options
Address
0x0102
Bit
7
6
Bit Name
Unused
M divider reset
[5:4]
M divider
3
2× frequency multiplier
enable
2
PLL enable
[1:0]
SYSCLK source
Description
Unused.
Reset the M divider.
0 = normal operation.
1 (default) = reset.
When not using the M divider, program this bit to Logic 1.
System clock input divider.
00 (default) = 1.
01 = 2.
10 = 4.
11 = 8.
Enable the 2× frequency multiplier.
0 (default) = disable.
1 = enable.
Enable the SYSCLK PLL.
0 = disable.
1 (default) = enable.
Input mode select for SYSCLKx pins.
00 = crystal resonator.
01 (default) = low frequency clock source.
10 = high frequency (direct) clock source.
11 = input receiver power-down.
Rev. 0 | Page 68 of 104
AD9547
Table 46. Nominal System Clock (SYSCLK) Period1
Address
0x0103
0x0104
0x0105
1
Bit
[7:0]
[7:0]
[7:5]
[4:0]
Bit Name
Nominal SYSCLK period
(expressed in fs)
Unused
Nominal SYSCLK period
Description
System clock period, Bits[7:0].
System clock period, Bits[15:8].
Unused.
System clock period, Bits[20:16].
Units are femtoseconds (fs). The default value is 0x0F424 = 1,000,000 (1 ns) and implies a system clock frequency of 1 GHz.
Table 47. System Clock Stability Period1
Address
0x0106
0x0107
0x0108
1
Bit
[7:0]
[7:0]
[7:4]
[3:0]
Bit Name
SYSCLK stability period
(expressed in ms)
Unused
SYSCLK stability period
Description
System clock stability period, Bits[7:0] (default = 0x01).
System clock stability period, Bits[15:8] (default = 0x00).
Unused.
System clock stability period, Bits[19:16] (default = 0x0)
(default period = 0x00001, or 1 ms).
Units are milliseconds (ms). The default value is 0x00001 = 1 (1 ms).
GENERAL CONFIGURATION (REGISTER 0x0200 TO REGISTER 0x0214)
Register 0x0200 to Register 0x0207—Multifunction Pin Control (M0 to M7)
Table 48. Multifunction Pin (M0 to M7) Control1
Address
0x0200
0x0201
0x0202
0x0203
0x0204
0x0205
0x0206
0x0207
1
Bit
7
Bit Name
M0 in/out
[6:0]
7
[6:0]
7
[6:0]
7
[6:0]
7
[6:0]
7
[6:0]
7
[6:0]
7
[6:0]
M0 function
M1 in/out
M1 function
M2 in/out
M2 function
M3 in/out
M3 function
M4 in/out
M4 function
M5 in/out
M5 function
M6 in/out
M6 function
M7 in/out
M7 function
Description
In/out control for the M0 pin.
0 (default) = input (control pin).
1 = output (status pin).
See Table 24 and Table 25 (default = 0xb0000000).
In/out control for the M1 pin (same as M0).
See Table 24 and Table 25 (default = 0xb0000000).
In/out control for the M2 pin (same as M0).
See Table 24 and Table 25 (default = 0xb0000000).
In/out control for the M3 pin (same as M0).
See Table 24 and Table 25 (default = 0xb0000000).
In/out control for the M4 pin (same as M0).
See Table 24 and Table 25 (default = 0xb0000000).
In/out control for the M5 pin (same as M0).
See Table 24 and Table 25 (default = 0xb0000000).
In/out control for the M6 pin (same as M0).
See Table 24 and Table 25 (default = 0xb0000000).
In/out control for the M7 pin (same as M0).
See Table 24 and Table 25 (default = 0xb0000000).
The default setting for all the multifunction pins is as an unused control input pin.
Table 49. IRQ Pin Output Mode
Address
0x0208
Bit
[7:2]
[1:0]
Bit Name
Unused
IRQ pin output mode
Description
Unused.
Select the output mode of the IRQ pin.
00 (default) = NMOS, open drain (requires an external pull-up resistor).
01 = PMOS, open drain (requires an external pull-down resistor).
10 = CMOS, active high.
11 = CMOS, active low.
Rev. 0 | Page 69 of 104
AD9547
Register 0x0209 to Register 0x0210—IRQ Mask
The IRQ mask register bits form a one-to-one correspondence with the bits of the IRQ monitor register (Address 0x0D02 to Address 0x0D09).
When set to Logic 1, the IRQ mask bits enable the corresponding IRQ monitor bits to indicate an IRQ event. The default for all IRQ mask
bits is Logic 0, which prevents the IRQ monitor from detecting any internal interrupts.
Table 50. IRQ Mask for SYSCLK
Address
0x0209
Bit
[7:6]
5
4
[3:2]
1
0
Bit Name
Unused
SYSCLK unlocked
SYSCLK locked
Unused
SYSCLK cal complete
SYSCLK cal started
Description
Unused.
Enables IRQ for indicating a SYSCLK PLL state transition from locked to unlocked.
Enables IRQ for indicating a SYSCLK PLL state transition from unlocked to locked.
Unused.
Enables IRQ for indicating that SYSCLK calibration is complete.
Enables IRQ for indicating that SYSCLK calibration has begun.
Table 51. IRQ Mask for Distribution Sync, Watchdog Timer, and EEPROM
Address
0x020A
Bit
[7:4]
3
2
1
0
Bit Name
Unused
Distribution sync
Watchdog timer
EEPROM fault
EEPROM complete
Description
Unused.
Enables IRQ for indicating a distribution sync event.
Enables IRQ for indicating expiration of the watchdog timer.
Enables IRQ for indicating a fault during an EEPROM load or save operation.
Enables IRQ for indicating successful completion of an EEPROM load or save operation.
Table 52. IRQ Mask for the Digital PLL
Address
0x020B
Bit
7
6
5
4
3
2
1
0
Bit Name
Switching
Closed
Free run
Holdover
Frequency unlocked
Frequency locked
Phase unlocked
Phase locked
Description
Enables IRQ for indicating that the DPLL is switching to a new reference.
Enables IRQ for indicating that the DPLL has entered closed-loop operation.
Enables IRQ for indicating that the DPLL has entered free-run mode.
Enables IRQ for indicating that the DPLL has entered holdover mode.
Enables IRQ for indicating that the DPLL lost frequency lock.
Enables IRQ for indicating that the DPLL has acquired frequency lock.
Enables IRQ for indicating that the DPLL lost phase lock.
Enables IRQ for indicating that the DPLL has acquired phase lock.
Table 53. IRQ Mask for History Update, Frequency Limit, and Phase Slew Limit
Address
0x020C
Bit
[7:5]
4
3
Bit Name
Unused
History updated
Frequency unclamped
2
Frequency clamped
1
Phase slew unlimited
0
Phase slew limited
Description
Unused.
Enables IRQ for indicating the occurrence of a tuning word history update.
Enables IRQ for indicating a state transition of the frequency limiter from clamped to
unclamped.
Enables IRQ for indicating a state transition of the frequency limiter from unclamped to
clamped.
Enables IRQ for indicating a state transition of the phase slew limiter from slew limiting to
not slew limiting.
Enables IRQ for indicating a state transition of the phase slew limiter from not slew
limiting to slew limiting.
Rev. 0 | Page 70 of 104
AD9547
Table 54. IRQ Mask for Reference Inputs
Address
0x020D
0x020E
0x020F
0x0210
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
[7:0]
[7:0]
Bit Name
Ref AA new profile
Ref AA validated
Ref AA fault cleared
Ref AA fault
Ref A new profile
Ref A validated
Ref A fault cleared
Ref A fault
Ref BB new profile
Ref BB validated
Ref BB fault cleared
Ref BB fault
Ref B new profile
Ref B validated
Ref B fault cleared
Ref B fault
Unused
Unused
Description
Enables IRQ for indicating that Ref AA has switched to a new profile.
Enables IRQ for indicating that Ref AA has been validated.
Enables IRQ for indicating that Ref AA has been cleared of a previous fault.
Enables IRQ for indicating that Ref AA has been faulted.
Enables IRQ for indicating that Ref A has switched to a new profile.
Enables IRQ for indicating that Ref A has been validated.
Enables IRQ for indicating that Ref A has been cleared of a previous fault.
Enables IRQ for indicating that Ref A has been faulted.
Enables IRQ for indicating that Ref BB has switched to a new profile.
Enables IRQ for indicating that Ref BB has been validated.
Enables IRQ for indicating that Ref BB has been cleared of a previous fault.
Enables IRQ for indicating that Ref BB has been faulted.
Enables IRQ for indicating that Ref B has switched to a new profile.
Enables IRQ for indicating that Ref B has been validated.
Enables IRQ for indicating that Ref B has been cleared of a previous fault.
Enables IRQ for indicating that Ref B has been faulted.
Unused.
Unused.
Table 55. Watchdog Timer1
Address
0x0211
0x0212
1
Bit
[7:0]
[7:0]
Bit Name
Watchdog timer
(expressed in ms)
Description
Watchdog timer, Bits[7:0] (default = 0x00).
Watchdog timer, Bits[15:8] (default = 0x00).
The watchdog timer is expressed in units of milliseconds (ms). The default value is 0 (disabled).
Table 56. DAC Current1
Address
0x0213
0x0214
1
Bit
[7:0]
7
Bit Name
DAC full-scale current
DAC shutdown
[6:2]
[1:0]
Unused
DAC full-scale current
Description
Full-scale current, Bits[7:0] (default = 0xFF).
Shut down the DAC current sources.
0 (default) = normal operation.
1 = shut down.
Unused.
Full-scale current, Bits[9:8] (default = 0b01).
(default current = 0x1FF, or 20.1 mA).
The default DAC full-scale current value is 0x01FF = 511, which equates to 20.1375 mA.
Rev. 0 | Page 71 of 104
AD9547
DPLL CONFIGURATION (REGISTER 0x0300 TO REGISTER 0x031B)
Table 57. Free-Running Frequency Tuning Word1
Address
0x0300
0x0301
0x0302
0x0303
0x0304
0x0305
1
Bit
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
Free-running frequency tuning word
(expressed as a 48-bit frequency
tuning word)
Description
Free-running frequency tuning word, Bits[7:0].
Free-running frequency tuning word, Bits[15:8].
Free-running frequency tuning word, Bits[23:16].
Free-running frequency tuning word, Bits[31:24].
Free-running frequency tuning word, Bits[39:32].
Free-running frequency tuning word, Bits[47:40].
The default free-running tuning word is 0x000000 = 0, which equates to 0 Hz.
Table 58. Update TW
Address
0x0306
Bit
[7:1]
0
Bit Name
Unused
Update TW
Description
Unused.
A Logic 1 written to this bit transfers the free-running frequency tuning word
(Register 0x0300 to Register 0x0305) to the register embedded in the tuning
word processing logic. Note that it is not necessary to write the update TW bit
when the device is in free-run mode. This is an autoclearing bit.
Table 59. Pull-in Range Lower and Upper Limit1
Address
0x0307
0x0308
0x0309
0x030A
0x030B
0x030C
1
Bit
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
Pull-in range lower limit (expressed
as a 24-bit frequency tuning word)
Pull-in range upper limit (expressed
as a 24-bit frequency tuning word)
Description
Lower limit pull-in range, Bits[7:0].
Lower limit pull-in range, Bits[15:8].
Lower limit pull-in range, Bits[23:16].
Upper limit pull-in range, Bits[7:0].
Upper limit pull-in range, Bits[15:8].
Upper limit pull-in range, Bits[23:16].
The default pull-in range lower limit is 0 and the upper range limit is 0xFFFFFF, which effectively spans the full output frequency range of the DDS.
Table 60. Open-Loop Phase Offset1
Address
0x030D
0x030E
1
Bit
[7:0]
[7:0]
Bit Name
Open-loop phase offset
(expressed in units of π/215 radians)
Description
DDS phase offset, Bits[7:0].
DDS phase offset, Bits[15:8].
The default DDS phase offset is 0.
Table 61. Fixed Closed-Loop Phase Lock Offset1
Address
0x030F
0x0310
0x0311
0x0312
0x0313
1
Bit
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
Fixed phase lock offset
(expressed in ps)
Description
Fixed phase lock offset, Bits[7:0].
Fixed phase lock offset, Bits[15:8].
Fixed phase lock offset, Bits[23:16].
Fixed phase lock offset, Bits[31:24].
Fixed phase lock offset, Bits[39:32].
The default fixed closed loop phase lock offset is 0.
Rev. 0 | Page 72 of 104
AD9547
Table 62. Incremental Closed-Loop Phase Lock Offset Step Size1
Address
0x0314
0x0315
1
Bit
[7:0]
[7:0]
Bit Name
Incremental phase lock offset
step size (expressed in ps/step)
Description
Incremental phase lock offset step size, Bits[7:0].
Incremental phase lock offset step size, Bits[15:8].
The default incremental closed loop phase lock offset step size value is 0x03E8 = 1000 (1 ns).
Table 63. Phase Slew Rate Limit1
Address
0x0316
0x0317
1
Bit
[7:0]
[7:0]
Bit Name
Phase slew rate limit
(expressed in ns/sec)
Description
Phase slew rate limit, Bits[7:0].
Phase slew rate limit, Bits[15:8].
The default phase slew rate limit is 0 (or disabled).
Table 64. History Accumulation Timer1
Address
0x0318
0x0319
0x031A
1
Bit
[7:0]
[7:0]
[7:0]
Bit Name
History accumulation timer
(expressed in ms)
Description
History accumulation timer, Bits[7:0].
History accumulation timer, Bits[15:8].
History accumulation timer, Bits[23:16].
Do not program a timer value of 0. The history accumulation timer default value is 0x007530 = 30,000 (30 sec).
Table 65. History Mode
Address
0x031B
Bit
[7:5]
4
Bit Name
Unused
Single sample fallback
3
Persistent history
[2:0]
Incremental average
Description
Unused.
Controls the holdover history. If tuning word history is not available for the
reference that was active just prior to holdover, then
0 (default) = use the free-running frequency tuning word register value.
1 = use the last tuning word from the DPLL.
Controls the holdover history initialization. When switching to a new reference
0 (default) = clear the tuning word history.
1 = retain the previous tuning word history.
History mode value from 0 to 7 (default = 0).
Rev. 0 | Page 73 of 104
AD9547
CLOCK DISTRIBUTION OUTPUT CONFIGURATION (REGISTER 0x0400 TO REGISTER 0x0417)
Table 66. Distribution Settings1
Address
0x0400
1
Bit
[7:6]
5
Bit Name
Unused
External distribution resistor
4
Receiver mode
[3:2]
1
Unused
OUT1 power-down
0
OUT0 power-down
Description
Unused.
Output current control for the clock distribution outputs.
0 (default) = internal current setting resistor.
1 = external current setting resistor.
Clock distribution receiver mode.
0 (default) = normal operation.
1 = high frequency mode (super-Nyquist).
Write a 1 to these bits.
Power down clock distribution output OUT1.
0 (default) = normal operation.
1 = power down.
Power down clock distribution output OUT0.
0 (default) = normal operation.
1 = power-down.
When Bits [1:0] = 11, the clock distribution output enters a deep sleep mode.
Table 67. Distribution Enable
Address
0x0401
Bit
[7:2]
1
Bit Name
Unused
OUT1 enable
0
OUT0 enable
Description
Unused.
Enable the OUT1 driver.
0 (default) = disable.
1 = enable.
Enable the OUT0 driver.
0 (default) = disable.
1 = enable.
Table 68. Distribution Synchronization
Address
0x0402
Bit
[7:6]
[5:4]
Bit Name
Unused
Sync source
[3:2]
1
Unused
OUT1 sync mask
0
OUT0 sync mask
Description
Unused.
Select the sync source for the clock distribution output channels.
00 (default) = direct.
01 = active reference.
10 = DPLL feedback edge.
11 = reserved.
Unused.
Mask the synchronous reset to the OUT1 divider.
0 (default) = unmasked.
1 = masked.
Mask the synchronous reset to the OUT0 divider.
0 (default) = unmasked.
1 = masked.
Table 69. Automatic Synchronization
Address
0x0403
Bit
[7:2]
[1:0]
Bit Name
Unused
Automatic sync mode
Description
Unused.
Autosync mode.
00 (default) = disabled.
01 = sync on DPLL frequency lock.
10 = sync on DPLL phase lock.
11 = reserved.
Rev. 0 | Page 74 of 104
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Table 70. Distribution Channel Modes
Address
0x0404
0x0405
0x0406
0x0407
Bit
[7:6]
5
Bit Name
Unused
OUT0 CMOS phase invert
4
OUT0 polarity invert
3
OUT0 drive strength
[2:0]
OUT0 mode
[7:6]
5
Unused
OUT1 CMOS phase invert
4
OUT1 polarity invert
3
OUT1 drive strength
[2:0]
OUT1 mode
[7:0]
[7:0]
Unused
Description
Unused.
When the output mode is CMOS, the bit inverts the relative phase between the two
CMOS output pins. Otherwise, this bit is nonfunctional.
0 (default) = not inverted.
1 = inverted.
Invert the polarity of OUT0.
0 (default) = not inverted.
1 = inverted.
OUT0 output drive capability control.
0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal.
1 = CMOS: normal drive strength; LVDS: 7 mA nominal.
OUT0 operating mode select.
000 = CMOS (both pins).
001 = CMOS (positive pin), tristate (negative pin).
010 = tristate (positive pin), CMOS (negative pin).
011 (default) = tristate (both pins).
100 = LVDS.
101 = LVPECL.
110 = reserved.
111 = reserved.
Unused.
When the output mode is CMOS, the bit inverts the relative phase between the two
CMOS output pins. Otherwise, this bit is nonfunctional.
0 (default) = not inverted.
1 = inverted.
Invert the polarity of OUT1.
0 (default) = not inverted.
1 = inverted.
OUT1 output drive capability control.
0 (default) = CMOS: low drive strength; LVDS: 3.5 mA nominal.
1 = CMOS: normal drive strength; LVDS: 7 mA nominal.
OUT1 operating mode select.
000 = CMOS (both pins).
001 = CMOS (positive pin), tristate (negative pin).
010 = tristate (positive pin), CMOS (negative pin).
011 (default) = tristate (both pins).
100 = LVDS.
101 = LVPECL.
110 = reserved.
111 = reserved.
Unused.
Rev. 0 | Page 75 of 104
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Register 0x0408 to Register 0x0417—Distribution Channel Dividers
Table 71. Q0 Divider1
Address
0x0408
0x0409
0x040A
0x040B
1
Bit
[7:0]
[7:0]
[7:0]
[7:6]
[5:0]
Bit Name
Q0
Unused
Q0
Description
Q0 divider, Bits[7:0].
Q0 divider, Bits[15:8].
Q0 divider, Bits[23:16].
Unused.
Q0 divider, Bits[29:24].
The default value is 0 (or divide by 1).
Table 72. Q1 Divider1
Address
0x040C
0x040D
0x040E
0x040F
1
Bit
[7:0]
[7:0]
[7:0]
[7:6]
[5:0]
Bit Name
Q1
Unused
Q1
Description
Q1 divider, Bits[7:0].
Q1 divider, Bits[15:8].
Q1 divider, Bits[23:16].
Unused.
Q1 divider, Bits[29:24].
The default value is 0 (or divide by 1).
Table 73. Reserved
Address
0x0410 to
0x0417
Bit
[7:0]
Bit Name
Unused
Description
Unused.
REFERENCE INPUT CONFIGURATION (REGISTER 0x0500 TO REGISTER 0x0507)
When all bits are set, the reference receiver section enters a deep sleep mode.
Table 74. Reference Power-Down
Address
0x0500
Bit
[7:4]
3
Bit Name
Unused
Ref BB power-down
2
Ref B power-down
1
Ref AA power-down
0
Ref A power-down
Description
Write a 1 to these bits.
REF BB input receiver power-down.
0 (default) = normal operation.
1 = power-down.
REF B input receiver power-down.
0 (default) = normal operation.
1 = power-down.
REF AA input receiver power-down.
0 (default) = normal operation.
1 = power-down.
REF A input receiver power-down.
0 (default) = normal operation.
1 = power-down.
Rev. 0 | Page 76 of 104
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Table 75. Reference Logic Family
Address
0x0501
0x0502
Bit
[7:6]
Bit Name
Ref BB logic family
[5:4]
Ref B logic family
[3:2]
[1:0]
[7:0]
Ref AA logic family
Ref A logic family
Unused
Description
Select the logic family for the REF BB input receiver (ignored if Bits[5:4] = 00).
00 (default) = disabled.
01 = 1.2 V to 1.5 V CMOS.
10 = 1.8 V to 2.5 V CMOS.
11 = 3.0 V to 3.3 V CMOS.
Select logic family for REF B input receiver.
00 (default) = differential (REFB/BB is positive/negative input).
01 = 1.2 V to 1.5 V CMOS.
10 = 1.8 V to 2.5 V CMOS.
11 = 3.0 V to 3.3 V CMOS.
The same as Register 0x0501, Bits[7:6] but for REF AA.
The same as Register 0x0501, Bits[5:4] but for REF A.
Unused.
Table 76. Manual Reference Profile Selection
Address
0x0503
0x0504
0x0505
0x0506
Bit
7
Bit Name
Enable Ref AA manual profile
[6:4]
Ref AA manual profile
3
[2:0]
7
[6:4]
3
[2:0]
[7:0]
[7:0]
Enable Ref A manual profile
Ref A manual profile
Enable Ref BB manual profile
Ref BB manual profile
Enable Ref B manual profile
Ref B manual profile
Unused
Description
Select manual or automatic reference profile assignment for REF AA.
0 (default) = automatic.
1 = manual.
Manual profile assignment.
000 (default) = Profile 0.
001 = Profile 1.
010 = Profile 2.
011 = Profile 3.
100 = Profile 4.
101 = Profile 5.
110 = Profile 6.
111 = Profile 7.
Same as Register 0x0503, Bit 7 but for REF A.
Same as Register 0x0503, Bits[6:4] but for REF A.
Same as Register 0x0503, Bit 7 but for REF BB.
Same as Register 0x0503, Bits[6:4] but for REF BB.
Same as Register 0x0503, Bit 7 but for REF B.
Same as Register 0x0503, Bits[6:4] but for REF B.
Unused.
Table 77. Phase Build-Out Switching
Address
0x0507
Bit
[7:3]
[2:0]
Bit Name
Unused
Phase master threshold
priority
Description
Unused.
Threshold priority level (a value of 0 to 7, with 0 (default) being the highest priority
level). References with a selection priority value lower than this value are treated as
phase masters (see the profile registers for selection priority value).
Rev. 0 | Page 77 of 104
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PROFILE REGISTERS (REGISTER 0x0600 TO REGISTER 0x07FF)
Note that the default value of every bit is 0 for Profile 0 to Profile 7.
Register 0x0600 to Register 0x0631—Profile 0
Table 78. Priorities—Profile 0
Address
0x0600
Bit
[7:6]
[5:3]
Bit Name
Unused
Promoted priority
[2:0]
Selection priority
Description
Unused.
User-assigned priority level (0 to 7) of the reference associated with Profile 0 while that
reference is the active reference. The numeric value of the promoted priority must be less
than or equal to the numeric value of the selection priority.
User-assigned priority level (0 to 7) of the reference associated with Profile 0, which ranks
that reference relative to the others.
Table 79. Reference Period—Profile 0
Address
0x0601
0x0602
0x0603
0x0604
0x0605
0x0606
0x0607
Bit
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
Reference period
(expressed in units of fs)
Unused.
Description
Nominal reference period, Bits[7:0].
Nominal reference period, Bits[15:8].
Nominal reference period, Bits[23:16].
Nominal reference period, Bits[31:24].
Nominal reference period, Bits[39:32].
Unused. Write 0s to these bits.
Table 80. Tolerance—Profile 0
Address
0x0608
0x0609
0x060A
0x060B
0x060C
0x060D
Bit
[7:0]
[7:0]
[7:4]
[3:0]
[7:0]
[7:0]
[7:4]
[3:0]
Bit Name
Inner tolerance
Unused
Inner tolerance
Outer tolerance
Unused
Outer tolerance
Description
Inner tolerance, Bits[7:0].
Inner tolerance, Bits[15:8].
Unused.
Inner tolerance, Bits[19:16].
Outer tolerance, Bits[7:0].
Outer tolerance, Bits[15:8].
Unused.
Outer tolerance, Bits[19:16].
Table 81. Validation Timer—Profile 0
Address
0x060E
0x060F
Bit
[7:0]
[7:0]
Bit Name
Validation timer
(expressed in units of ms)
Description
Validation timer, Bits[7:0].
Validation timer, Bits[15:8].
Table 82. Redetect Timer—Profile 0
Address
0x0610
0x0611
Bit
[7:0]
[7:0]
Bit Name
Redetect timer
(expressed in units of ms)
Description
Redetect timer, Bits[7:0].
Redetect timer, Bits[15:8].
Rev. 0 | Page 78 of 104
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Table 83. Digital Loop Filter Coefficients—Profile 01
Address
0x0612
0x0613
0x0614
0x0615
0x0616
0x0617
0x0618
0x0619
0x061A
0x061B
0x061C
0x061D
1
Bit
[7:0]
[7:0]
[7:6]
[5:0]
[7:1]
0
[7:0]
7
[6:2]
[1:0]
[7:0]
[7:0]
[7:6]
[5:1]
0
[7:0]
7
[6:0]
[7:4]
[3:0]
Bit Name
Alpha-0 linear
Alpha-2 exponent
Alpha-1 exponent
Beta-0 linear
Alpha-2 exponent
Beta-0 linear
Unused
Beta-1 exponent
Beta-0 linear
Gamma-0 linear
Unused
Gamma-1 exponent
Gamma-0 linear
Delta-0 linear
Delta-1 exponent
Delta-0 linear
Alpha-3 exponent
Delta-1 exponent
Description
Alpha-0 coefficient linear, Bits[7:0].
Alpha-0 coefficient linear, Bits[15:8].
Alpha-2 coefficient exponent, Bits[1:0].
Alpha-1 coefficient exponent, Bits[5:0].
Beta-0 coefficient linear, Bits[6:0].
Alpha-2 coefficient exponent, Bit 2.
Beta-0 coefficient linear, Bits[14:7].
Unused.
Beta-1 coefficient exponent, Bits[4:0].
Beta-0 coefficient linear, Bits[16:15].
Gamma-0 coefficient linear, Bits[7:0].
Gamma-0 coefficient linear, Bits[15:8].
Unused.
Gamma-1 coefficient exponent, Bits[4:0].
Gamma-0 coefficient linear, Bit 16.
Delta-0 coefficient linear, Bits[7:0].
Delta-1 coefficient exponent, Bit 0.
Delta-0 coefficient linear, Bits[14:8].
Alpha-3 coefficient exponent, Bits[3:0].
Delta-1 coefficient exponent, Bits[4:1].
The digital loop filter coefficients (α, β, γ, and δ) have the general form: x(2y), where x is the linear component and y is the exponential component of the coefficient.
The value of the linear component (x) constitutes a fraction, where 0 ≤ x < 1. The exponential component (y) is an integer. See the Calculating the Digital Filter
Coefficients section for details.
Register 0x061E to Register 0x0628—Profile 0 Frequency Multiplication
Table 84. R Divider—Profile 01
Address
0x061E
0x061F
0x0620
0x0621
1
Bit
[7:0]
[7:0]
[7:0]
[7:6]
[5:0]
Bit Name
R
Unused
R
Description
R, Bits[7:0].
R, Bits[15:8].
R, Bits[23:16].
Unused.
R, Bits[29:24].
The value stored in the R divider register yields an actual divide ratio of one more than the programmed value.
Table 85. S Divider—Profile 01
Address
0x0622
0x0623
0x0624
0x0625
1
Bit
[7:0]
[7:0]
[7:4]
[3:0]
[7:0]
Bit Name
S
S
Unused
S
Unused
Description
S, Bits[7:0].
S, Bits[15:8].
Unused.
S, Bits[19:16].
Unused.
The value stored in the S divider register yields an actual divide ratio of one more than the programmed value. Furthermore, the value of S must be at least 7.
Rev. 0 | Page 79 of 104
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Table 86. Fractional Feedback Divider—Profile 0
Address
0x0626
0x0627
0x0628
Bit
[7:0]
[7:4]
[3:2]
[1:0]
[7:6]
[5:0]
Bit Name
V
U
Unused
V
Unused
U
Description
V, Bits[7:0].
U, Bits[3:0].
Unused.
V, Bits[9:8].
Unused.
U, Bits[9:4].
Table 87. Lock Detectors—Profile 0
Address
0x0629
0x062A
0x062B
0x062C
0x062D
0x062E
0x062F
0x0630
0x0631
Bit
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
Phase lock threshold
(expressed in units of ps)
Phase lock fill rate
Phase lock drain rate
Frequency lock threshold
(expressed in units of ps)
Frequency lock fill rate
Frequency lock drain rate
Description
Phase lock threshold, Bits[7:0].
Phase lock threshold, Bits[15:8].
Phase lock fill rate, Bits[7:0].
Phase lock drain rate, Bits[7:0].
Frequency lock threshold, Bits[7:0].
Frequency lock threshold, Bits[15:8].
Frequency lock threshold, Bits[23:16].
Frequency lock fill rate, Bits[7:0].
Frequency lock drain rate, Bits[7:0].
Register 0x0632 to Register 0x067F—Profile 1
Table 88. Priorities—Profile 1
Address
0x0632
Bit
[7:6]
[5:3]
Bit Name
Unused
Promoted priority
[2:0]
Selection priority
Description
Unused.
User-assigned priority level (0 to 7) of the reference associated with Profile 1 while
that reference is the active reference. The numeric value of the promoted priority
must be less than or equal to the numeric value of the selection priority.
User-assigned priority level (0 to 7) of the reference associated with Profile 1, which
ranks that reference relative to the others.
Table 89. Reference Period—Profile 1
Address
0x0633
0x0634
0x0635
0x0636
0x0637
0x0638
0x0639
Bit
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
Reference period
(expressed in units of fs)
Unused
Description
Nominal reference period, Bits[7:0].
Nominal reference period, Bits[15:8].
Nominal reference period, Bits[23:16].
Nominal reference period, Bits[31:24].
Nominal reference period, Bits[39:32].
Unused. Write 0s to these bits.
Table 90. Tolerance—Profile 1
Address
0x063A
0x063B
0x063C
0x063D
0x063E
0x063F
Bit
[7:0]
[7:0]
[7:4]
[3:0]
[7:0]
[7:0]
[7:4]
[3:0]
Bit Name
Inner tolerance
Unused
Inner tolerance
Outer tolerance
Unused
Outer tolerance
Description
Inner tolerance, Bits[7:0].
Inner tolerance, Bits[15:8].
Unused.
Inner tolerance, Bits[19:16].
Outer tolerance, Bits[7:0].
Outer tolerance, Bits[15:8].
Unused.
Outer tolerance, Bits[19:16].
Rev. 0 | Page 80 of 104
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Table 91. Validation Timer—Profile 1
Address
0x0640
0x0641
Bit
[7:0]
[7:0]
Bit Name
Validation timer
(expressed in units of ms)
Description
Validation timer, Bits[7:0].
Validation timer, Bits[15:8].
Table 92. Redetect Timer—Profile 1
Address
0x0642
0x0643
Bit
[7:0]
[7:0]
Bit Name
Redetect timer
(expressed in units of ms)
Description
Redetect timer, Bits[7:0].
Redetect timer, Bits[15:8].
Table 93. Digital Loop Filter Coefficients—Profile 11
Address
0x0644
0x0645
0x0646
0x0647
0x0648
0x0649
0x064A
0x064B
0x064C
0x064D
0x064E
0x064F
1
Bit
[7:0]
[7:0]
[7:6]
[5:0]
[7:1]
0
[7:0]
7
[6:2]
[1:0]
[7:0]
[7:0]
[7:6]
[5:1]
0
[7:0]
7
[6:0]
[7:4]
[3:0]
Bit Name
Alpha-0 linear
Alpha-2 exponent
Alpha-1 exponent
Beta-0 linear
Alpha-2 exponent
Beta-0 linear
Unused
Beta-1 exponent
Beta-0 linear
Gamma-0 linear
Unused
Gamma-1 exponent
Gamma-0 linear
Delta-0 linear
Delta-1 exponent
Delta-0 linear
Alpha-3 exponent
Delta-1 exponent
Description
Alpha-0 coefficient linear, Bits[7:0].
Alpha-0 coefficient linear, Bits[15:8].
Alpha-2 coefficient exponent, Bits[1:0].
Alpha-1 coefficient exponent, Bits[5:0].
Beta-0 coefficient linear, Bits[6:0].
Alpha-2 coefficient exponent, Bit 2.
Beta-0 coefficient linear, Bits[14:7].
Unused.
Beta-1 coefficient exponent, Bits[4:0].
Beta-0 coefficient linear, Bits[16:15].
Gamma-0 coefficient linear, Bits[7:0].
Gamma-0 coefficient linear, Bits[15:8].
Unused.
Gamma-1 coefficient exponent, Bits[4:0].
Gamma-0 coefficient linear, Bit 16.
Delta-0 coefficient linear, Bits[7:0].
Delta-1 coefficient exponent, Bit 0.
Delta-0 coefficient linear, Bits[14:8].
Alpha-3 coefficient exponent, Bits[3:0].
Delta-1 coefficient exponent, Bits[4:1].
The digital loop filter coefficients (α, β, γ, and δ) have the general form: x(2y), where x is the linear component and y is the exponential component of the coefficient.
The value of the linear component (x) constitutes a fraction, where 0 ≤ x < 1. The exponential component (y) is an integer. See the Calculating the Digital Filter
Coefficients section for details.
Register 0x0650 to Register 0x065A—Profile 1 Frequency Multiplication
Table 94. R Divider—Profile 11
Address
0x0650
0x0651
0x0652
0x0653
1
Bit
[7:0]
[7:0]
[7:0]
[7:6]
[5:0]
Bit Name
R
Unused
R
Description
R, Bits[7:0].
R, Bits[15:8].
R, Bits[23:16].
Unused.
R, Bits[29:24].
The value stored in the R divider register yields an actual divide ratio of one more than the programmed value.
Rev. 0 | Page 81 of 104
AD9547
Table 95. S Divider—Profile 1 1
Address
0x0654
0x0655
0x0656
0x0657
1
Bit
[7:0]
[7:0]
[7:4]
[3:0]
[7:0]
Bit Name
S
S
Unused
S
Unused
Description
S, Bits[7:0].
S, Bits[15:8].
Unused.
S, Bits[19:16].
Unused.
The value stored in the S divider register yields an actual divide ratio of one more than the programmed value. Furthermore, the value of S must be at least 7.
Table 96. Fractional Feedback Divider—Profile 1
Address
0x0658
0x0659
0x065A
Bit
[7:0]
[7:4]
[3:2]
[1:0]
[7:6]
[5:0]
Bit Name
V
U
Unused
V
Unused
U
Description
V, Bits[7:0].
U, Bits[3:0].
Unused.
V, Bits[9:8].
Unused.
U, Bits[9:4].
Table 97. Lock Detectors—Profile 1
Address
0x065B
0x065C
0x065D
0x065E
0x065F
0x0660
0x0661
0x0662
0x0663
0x0664
to
0x067F
Bit
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
Phase lock threshold
(expressed in units of ps)
Phase lock fill rate
Phase lock drain rate
Frequency lock threshold
(expressed in units of ps)
Frequency lock fill rate
Frequency lock drain rate
Unused
Description
Phase lock threshold, Bits[7:0].
Phase lock threshold, Bits[15:8].
Phase lock fill rate, Bits[7:0].
Phase lock drain rate, Bits[7:0].
Frequency lock threshold, Bits[7:0].
Frequency lock threshold, Bits[15:8].
Frequency lock threshold, Bits[23:16].
Frequency lock fill rate, Bits[7:0].
Frequency lock drain rate, Bits[7:0].
Unused.
Register 0x0680 to Register 0x06B1—Profile 2
Table 98. Priorities—Profile 2
Address
0x0680
Bit
[7:6]
[5:3]
Bit Name
Unused
Promoted priority
[2:0]
Selection priority
Description
Unused.
User-assigned priority level (0 to 7) of the reference associated with Profile 2 while
that reference is the active reference. The numeric value of the promoted priority
must be less than or equal to the numeric value of the selection priority.
User-assigned priority level (0 to 7) of the reference associated with Profile 2, which
ranks that reference relative to the others.
Table 99. Reference Period—Profile 2
Address
0x0681
0x0682
0x0683
0x0684
0x0685
0x0686
0x0687
Bit
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
Reference period
(expressed in units of fs)
Unused
Description
Nominal reference period, Bits[7:0].
Nominal reference period, Bits[15:8].
Nominal reference period, Bits[23:16].
Nominal reference period, Bits[31:24].
Nominal reference period, Bits[39:32].
Unused. Write 0s to these bits.
Rev. 0 | Page 82 of 104
AD9547
Table 100. Tolerance—Profile 2
Address
0x0688
0x0689
0x068A
0x068B
0x068C
0x068D
Bit
[7:0]
[7:0]
[7:4]
[3:0]
[7:0]
[7:0]
[7:4]
[3:0]
Bit Name
Inner tolerance
Unused
Inner tolerance
Outer tolerance
Unused
Outer tolerance
Description
Inner tolerance, Bits[7:0].
Inner tolerance, Bits[15:8].
Unused.
Inner tolerance, Bits[19:16].
Outer tolerance, Bits[7:0].
Outer tolerance, Bits[15:8].
Unused.
Outer tolerance, Bits[19:16].
Table 101. Validation Timer—Profile 2
Address
0x068E
0x068F
Bit
[7:0]
[7:0]
Bit Name
Validation timer
(expressed in units of ms)
Description
Validation timer, Bits[7:0].
Validation timer, Bits[15:8].
Table 102. Redetect Timer—Profile 2
Address
0x0690
0x0691
Bit
[7:0]
[7:0]
Bit Name
Redetect timer
(expressed in units of ms)
Description
Redetect timer, Bits[7:0].
Redetect timer, Bits[15:8].
Table 103. Digital Loop Filter Coefficients—Profile 21
Address
0x0692
0x0693
0x0694
0x0695
0x0696
0x0697
0x0698
0x0699
0x069A
0x069B
0x069C
0x069D
1
Bit
[7:0]
[7:0]
[7:6]
[5:0]
[7:1]
0
[7:0]
7
[6:2]
[1:0]
[7:0]
[7:0]
[7:6]
[5:1]
0
[7:0]
7
[6:0]
[7:4]
[3:0]
Bit Name
Alpha-0 linear
Alpha-2 exponent
Alpha-1 exponent
Beta-0 linear
Alpha-2 exponent
Beta-0 linear
Unused
Beta-1 exponent
Beta-0 linear
Gamma-0 linear
Unused
Gamma-1 exponent
Gamma-0 linear
Delta-0 linear
Delta-1 exponent
Delta-0 linear
Alpha-3 exponent
Delta-1 exponent
Description
Alpha-0 coefficient linear, Bits[7:0].
Alpha-0 coefficient linear, Bits[15:8].
Alpha-2 coefficient exponent, Bits[1:0].
Alpha-1 coefficient exponent, Bits[5:0].
Beta-0 coefficient linear, Bits[6:0].
Alpha-2 coefficient exponent, Bit 2.
Beta-0 coefficient linear, Bits[14:7].
Unused.
Beta-1 coefficient exponent, Bits[4:0].
Beta-0 coefficient linear, Bits[16:15].
Gamma-0 coefficient linear, Bits[7:0].
Gamma-0 coefficient linear, Bits[15:8].
Unused.
Gamma-1 coefficient exponent, Bits[4:0].
Gamma-0 coefficient linear, Bit 16.
Delta-0 coefficient linear, Bits[7:0].
Delta-1 coefficient exponent, Bit 0.
Delta-0 coefficient linear, Bits[14:8].
Alpha-3 coefficient exponent, Bits[3:0].
Delta-1 coefficient exponent, Bits[4:1].
The digital loop filter coefficients (α, β, γ, and δ) have the general form: x(2y), where x is the linear component and y is the exponential component of the coefficient.
The value of the linear component (x) constitutes a fraction, where 0 ≤ x < 1. The exponential component (y) is an integer (see the Calculating the Digital Filter
Coefficients section for details).
Rev. 0 | Page 83 of 104
AD9547
Register 0x069E to Register 0x06A8—Profile 2 Frequency Multiplication
Table 104. R Divider—Profile 2 1
Address
0x069E
0x069F
0x06A0
0x06A1
1
Bit
[7:0]
[7:0]
[7:0]
[7:6]
[5:0]
Bit Name
R
Unused
R
Description
R, Bits[7:0].
R, Bits[15:8].
R, Bits[23:16].
Unused.
R, Bits[29:24].
The value stored in the R divider register yields an actual divide ratio of one more than the programmed value.
Table 105. S Divider—Profile 2 1
Address
0x06A2
0x06A3
0x06A4
0x06A5
1
Bit
[7:0]
[7:0]
[7:4]
[3:0]
[7:0]
Bit Name
S
S
Unused
S
Unused
Description
S, Bits[7:0].
S, Bits[15:8].
Unused.
S, Bits[19:16].
Unused.
The value stored in the S divider register yields an actual divide ratio of one more than the programmed value. Furthermore, the value of S must be at least 7.
Table 106. Fractional Feedback Divider—Profile 2
Address
0x06A6
0x06A7
0x06A8
Bit
[7:0]
[7:4]
[3:2]
[1:0]
[7:6]
[5:0]
Bit Name
V
U
Unused
V
Unused
U
Description
V, Bits[7:0].
U, Bits[3:0].
Unused.
V, Bits[9:8].
Unused.
U, Bits[9:4].
Table 107. Lock Detectors—Profile 2
Address
0x06A9
0x06AA
0x06AB
0x06AC
0x06AD
0x06AE
0x06AF
0x06B0
0x06B1
Bit
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
Phase lock threshold
(expressed in units of ps)
Phase lock fill rate
Phase lock drain rate
Frequency lock threshold
(expressed in units of ps)
Frequency lock fill rate
Frequency lock drain rate
Description
Phase lock threshold, Bits[7:0].
Phase lock threshold, Bits[15:8].
Phase lock fill rate, Bits[7:0].
Phase lock drain rate, Bits[7:0].
Frequency lock threshold, Bits[7:0].
Frequency lock threshold, Bits[15:8].
Frequency lock threshold, Bits[23:16].
Frequency lock fill rate, Bits[7:0].
Frequency lock drain rate, Bits[7:0].
Rev. 0 | Page 84 of 104
AD9547
Register 0x06B2 to Register 0x06FF—Profile 3
Table 108. Priorities—Profile 3
Address
0x06B2
Bit
[7:6]
[5:3]
Bit Name
Unused
Promoted priority
[2:0]
Selection priority
Description
Unused.
User-assigned priority level (0 to 7) of the reference associated with Profile 3 while
that reference is the active reference. The numeric value of the promoted priority
must be less than or equal to the numeric value of the selection priority.
User-assigned priority level (0 to 7) of the reference associated with Profile 3, which
ranks that reference relative to the others.
Table 109. Reference Period—Profile 3
Address
0x06B3
0x06B4
0x06B5
0x06B6
0x06B7
0x06B8
0x06B9
Bit
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
Reference period
(expressed in units of fs)
Unused
Description
Nominal reference period, Bits[7:0].
Nominal reference period, Bits[15:8].
Nominal reference period, Bits[23:16].
Nominal reference period, Bits[31:24].
Nominal reference period, Bits[39:32].
Unused. Write 0s to these bits.
Table 110. Tolerance—Profile 3
Address
0x06BA
0x06BB
0x06BC
0x06BD
0x06BE
0x06BF
Bit
[7:0]
[7:0]
[7:4]
[3:0]
[7:0]
[7:0]
[7:4]
[3:0]
Bit Name
Inner tolerance
Unused
Inner tolerance
Outer tolerance
Unused
Outer tolerance
Description
Inner tolerance, Bits[7:0].
Inner tolerance, Bits[15:8].
Unused.
Inner tolerance, Bits[19:16].
Outer tolerance, Bits[7:0].
Outer tolerance, Bits[15:8].
Unused.
Outer tolerance, Bits[19:16].
Table 111. Validation Timer—Profile 3
Address
0x06C0
0x06C1
Bit
[7:0]
[7:0]
Bit Name
Validation timer
(expressed in units of ms)
Description
Validation timer, Bits[7:0].
Validation timer, Bits[15:8].
Table 112. Redetect Timer—Profile 3
Address
0x06C2
0x06C3
Bit
[7:0]
[7:0]
Bit Name
Redetect timer
(expressed in units of ms)
Description
Redetect timer, Bits[7:0].
Redetect timer, Bits[15:8].
Table 113. Digital Loop Filter Coefficients—Profile 31
Address
0x06C4
0x06C5
0x06C6
0x06C7
0x06C8
Bit
[7:0]
[7:0]
[7:6]
[5:0]
[7:1]
0
[7:0]
Bit Name
Alpha-0 linear
Alpha-2 exponent
Alpha-1 exponent
Beta-0 linear
Alpha-2 exponent
Beta-0 linear
Description
Alpha-0 coefficient linear, Bits[7:0].
Alpha-0 coefficient linear, Bits[15:8].
Alpha-2 coefficient exponent, Bits[1:0].
Alpha-1 coefficient exponent, Bits[5:0].
Beta-0 coefficient linear, Bits[6:0].
Alpha-2 coefficient exponent, Bit 2.
Beta-0 coefficient linear, Bits[14:7].
Rev. 0 | Page 85 of 104
AD9547
Address
0x06C9
0x06CA
0x06CB
0x06CC
0x06CD
0x06CE
0x06CF
1
Bit
7
[6:2]
[1:0]
[7:0]
[7:0]
[7:6]
[5:1]
0
[7:0]
7
[6:0]
[7:4]
[3:0]
Bit Name
Unused
Beta-1 exponent
Beta-0 linear
Gamma-0 linear
Unused
Gamma-1 exponent
Gamma-0 linear
Delta-0 linear
Delta-1 exponent
Delta-0 linear
Alpha-3 exponent
Delta-1 exponent
Description
Unused.
Beta-1 coefficient exponent, Bits[4:0].
Beta-0 coefficient linear, Bits[16:15].
Gamma-0 coefficient linear, Bits[7:0].
Gamma-0 coefficient linear, Bits[15:8].
Unused.
Gamma-1 coefficient exponent, Bits[4:0].
Gamma-0 coefficient linear, Bit 16.
Delta-0 coefficient linear, Bits[7:0].
Delta-1 coefficient exponent, Bit 0.
Delta-0 coefficient linear, Bits[14:8].
Alpha-3 coefficient exponent, Bits[3:0].
Delta-1 coefficient exponent, Bits[4:1].
The digital loop filter coefficients (α, β, γ, and δ) have the general form: x(2y), where x is the linear component and y is the exponential component of the coefficient.
The value of the linear component (x) constitutes a fraction, where 0 ≤ x < 1. The exponential component (y) is an integer (see the Calculating the Digital Filter
Coefficients section for details).
Register 0x06D0 to Register 0x06DA—Profile 3 Frequency Multiplication
Table 114. R Divider—Profile 3 1
Address
0x06D0
0x06D1
0x06D2
0x06D3
1
Bit
[7:0]
[7:0]
[7:0]
[7:6]
[5:0]
Bit Name
R
Unused
R
Description
R, Bits[7:0].
R, Bits[15:8].
R, Bits[23:16].
Unused.
R, Bits[29:24].
The value stored in the R divider register yields an actual divide ratio of one more than the programmed value.
Table 115. S Divider—Profile 3 1
Address
0x06D4
0x06D5
0x06D6
0x06D7
1
Bit
[7:0]
[7:0]
[7:4]
[3:0]
[7:0]
Bit Name
S
S
Unused
S
Unused
Description
S, Bits[7:0].
S, Bits[15:8].
Unused.
S, Bits[19:16].
Unused.
The value stored in the S divider register yields an actual divide ratio of one more than the programmed value. Furthermore, the value of S must be at least 7.
Table 116. Fractional Feedback Divider—Profile 3
Address
0x06D8
0x06D9
0x06DA
Bit
[7:0]
[7:4]
[3:2]
[1:0]
[7:6]
[5:0]
Bit Name
V
U
Unused
V
Unused
U
Description
V, Bits[7:0].
U, Bits[3:0].
Unused.
V, Bits[9:8].
Unused.
U, Bits[9:4].
Rev. 0 | Page 86 of 104
AD9547
Table 117. Lock Detectors—Profile 3
Address
0x06DB
0x06DC
0x06DD
0x06DE
0x06DF
0x06E0
0x06E1
0x06E2
0x06E3
0x06E4 to
0x06FF
Bit
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
Phase lock threshold
(expressed in units of ps)
Phase lock fill rate
Phase lock drain rate
Frequency lock threshold
(expressed in units of ps)
Frequency lock fill rate
Frequency lock drain rate
Unused
Description
Phase lock threshold, Bits[7:0].
Phase lock threshold, Bits[15:8].
Phase lock fill rate, Bits[7:0].
Phase lock drain rate, Bits[7:0].
Frequency lock threshold, Bits[7:0].
Frequency lock threshold, Bits[15:8].
Frequency lock threshold, Bits[23:16].
Frequency lock fill rate, Bits[7:0].
Frequency lock drain rate, Bits[7:0].
Unused.
Register 0x0700 to Register 0x07FF—Profile 4 to Profile 7
Profile 4 (Register 0x0700 to Register 0x0731) is identical to Profile 0 (Register 0x0600 to Register 0x0631).
Profile 5 (Register 0x0732 to Register 0x077F) is identical to Profile 1 (Register 0x0632 to Register 0x067F).
Profile 6 (Register 0x0780 to Register 0x07B1) is identical to Profile 2 (Register 0x0680 to Register 0x06B1).
Profile 7 (Register 0x07B2 to Register 0x07FF) is identical to Profile 3 (Register 0x06B2 to Register 0x06FF).
Rev. 0 | Page 87 of 104
AD9547
OPERATIONAL CONTROLS (REGISTER 0x0A00 TO REGISTER 0x0A10)
Table 118. General Power-Down
Address
0x0A00
Bit
7
Bit Name
Reset sans regmap
6
5
Unused
SYSCLK power-down
4
Reference power-down
3
TDC power-down
2
DAC power-down
1
Dist power-down
0
Full power-down
Description
Reset internal hardware but retain programmed register values.
0 (default) = normal operation.
1 = reset.
Unused.
Place SYSCLK input and PLL in deep sleep mode.
0 (default) = normal operation.
1 = power-down.
Place reference clock inputs in deep sleep mode.
0 (default) = normal operation.
1 = power-down.
Place the time-to-digital converter in deep sleep mode.
0 (default) = normal operation.
1 = power-down.
Place the DAC in deep sleep mode.
0 (default) = normal operation.
1 = power-down.
Place the clock distribution outputs in deep sleep mode.
0 (default) = normal operation.
1 = power-down.
Place the entire device in deep sleep mode.
0 (default) = normal operation.
1 = power-down.
Table 119. Loop Mode
Address
0x0A01
Bit
7
6
Bit Name
Unused
User holdover
5
User free run
[4:3]
User selection mode
2
[1:0]
Unused
User reference selection
Description
Unused.
Force the device into holdover mode.
0 (default) = normal operation.
1 = force device into holdover mode.
The device functions as though all input references are faulted.
Force the device into free-run mode.
0 (default) = normal operation.
1 = force device into free-run mode.
The free-running frequency tuning word register (Address 0x0300 to Address 0x0305)
specifies the DDS output frequency.
Note that, when user free run is set, it overrides user holdover.
Select the operating mode of the reference switching state machine.
00 (default) = automatic mode. The fully automatic priority-based algorithm selects the
active reference (Bits[1:0] are ignored).
01 = fallback mode. The active reference is the user reference (Bits[1:0]) as long as it is valid.
Otherwise, use the fully automatic priority-based algorithm to select the active reference.
10 = holdover mode. The active reference is the user reference (Bits[1:0]) as long as it is
valid. Otherwise, enter holdover mode.
11 = manual mode. The active reference is always the user reference (Bits[1:0]). When using
manual mode, be sure that the reference declared as the user reference (Bits[1:0]) is
programmed for manual reference-to-profile assignment in the appropriate manual
reference profile selection register (Address 0x0503 and Address 0x0506).
Unused. Write a 0 to this bit.
Input reference when user selection mode = 01, 10, or 11.
00 (default) = Input Reference A.
01 = Input Reference AA.
10 = Input Reference B.
11 = Input Reference BB.
Rev. 0 | Page 88 of 104
AD9547
Table 120. Cal/Sync
Address
0x0A02
Bit
[7:2]
1
Bit Name
Unused
Sync distribution
0
Calibrate SYSCLK
Description
Unused.
Setting this bit (default = 0) initiates synchronization of the clock distribution output. When
this bit = 1, the clock distribution output stalls. Synchronization occurs on the 1 to 0 transition of
this bit.
Setting this bit (default = 0) initiates an internal calibration of the SYSCLK PLL (assuming it is
enabled). The calibration routine automatically selects the proper VCO frequency band and
signal amplitude. The internal system clock stalls during the calibration procedure, disabling
the device until calibration is complete (a few ms).
Register 0x0A03—Reset Functions
Table 121. Reset Functions 1
Address
0x0A03
1
Bit
7
6
5
4
3
2
Bit Name
Unused
Clear LF
Clear CCI
Clear phase accumulator
Reset auto sync
Reset TW history
1
Reset all IRQs
0
Reset watchdog
Description
Unused.
Setting this bit (default = 0) clears the digital loop filter (intended as a debug tool).
Setting this bit (default = 0) clears the CCI filter (intended as a debug tool).
Setting this bit (default = 0) clears DDS phase accumulator (not a recommended action).
Setting this bit (default = 0) resets the automatic synchronization logic (see Register 0x0403).
Setting this bit (default = 0) resets the tuning word history logic (part of holdover
functionality).
Setting this bit (default = 0) clears the entire IRQ monitor register (Register 0x0D02 to
Register 0x0D09). It is the equivalent of setting all the bits of the IRQ clearing register
(Register 0x0A04 to Register 0x0A0B).
Setting this bit (default = 0) resets the watchdog timer (see Register 0x0211 to Register 0x0212).
If the timer times out, it simply starts a new timing cycle. If the timer has not yet timed out,
it restarts at Time 0 without causing a timeout event. Continuously resetting the watchdog
timer at intervals less than its timeout period prevents the watchdog timer from generating
a timeout event.
All bits in this register are autoclearing.
Register 0x0A04 to Register 0x0A0B—IRQ Clearing
The IRQ clearing registers are identical in format to the IRQ monitor registers (Address 0x0D02 to Address 0x0D09). When set to Logic 1,
an IRQ clearing bit resets the corresponding IRQ monitor bit, thereby canceling the interrupt request for the indicated event. The IRQ
clearing register is an autoclearing register.
Table 122. IRQ Clearing for SYSCLK
Address
0x0A04
Bit
[7:6]
5
4
[3:2]
1
0
Bit Name
Unused
SYSCLK unlocked
SYSCLK locked
Unused
SYSCLK cal complete
SYSCLK cal started
Description
Unused.
Clears SYSCLK unlocked IRQ.
Clears SYSCLK locked IRQ.
Unused.
Clears SYSCLK calibration complete IRQ.
Clears SYSCLK calibration started IRQ.
Table 123. IRQ Clearing for Distribution Sync, Watchdog Timer, and EEPROM
Address
0x0A05
Bit
[7:4]
3
2
1
0
Bit Name
Unused
Distribution sync
Watchdog timer
EEPROM fault
EEPROM complete
Description
Unused.
Clears distribution sync IRQ.
Clears watchdog timer IRQ.
Clears EEPROM fault IRQ.
Clears EEPROM complete IRQ.
Rev. 0 | Page 89 of 104
AD9547
Table 124. IRQ Clearing for the Digital PLL
Address
0x0A06
Bit
7
6
5
4
3
2
1
0
Bit Name
Switching
Closed
Free run
Holdover
Frequency unlocked
Frequency locked
Phase unlocked
Phase locked
Description
Clears switching IRQ.
Clears closed IRQ.
Clears free-run IRQ.
Clears holdover IRQ.
Clears frequency unlocked IRQ.
Clears frequency locked IRQ.
Clears phase unlocked IRQ.
Clears phase locked IRQ.
Table 125. IRQ Clearing for History Update, Frequency Limit, and Phase Slew Limit
Address
0x0A07
Bit
[7:5]
4
3
2
1
0
Bit Name
Unused
History updated
Frequency unclamped
Frequency clamped
Phase slew unlimited
Phase slew limited
Description
Unused.
Clears history updated IRQ.
Clears frequency unclamped IRQ.
Clears frequency clamped IRQ.
Clears phase slew unlimited IRQ.
Clears phase slew limited IRQ.
Table 126. IRQ Clearing for Reference Inputs
Address
0x0A08
0x0A09
0x0A0A
0x0A0B
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
[7:0]
[7:0]
Bit Name
Ref AA new profile
Ref AA validated
Ref AA fault cleared
Ref AA fault
Ref A new profile
Ref A validated
Ref A fault cleared
Ref A fault
Ref BB new profile
Ref BB validated
Ref BB fault cleared
Ref BB fault
Ref B new profile
Ref B validated
Ref B fault cleared
Ref B fault
Unused
Description
Clears Ref AA new profile IRQ.
Clears Ref AA validated IRQ.
Clears Ref AA fault cleared IRQ.
Clears Ref AA fault IRQ.
Clears Ref A new profile IRQ.
Clears Ref A validated IRQ.
Clears Ref A fault cleared IRQ.
Clears Ref A fault IRQ.
Clears Ref BB new profile IRQ.
Clears Ref BB validated IRQ.
Clears Ref BB fault cleared IRQ.
Clears Ref BB fault IRQ.
Clears Ref B new profile IRQ.
Clears Ref B validated IRQ.
Clears Ref B fault cleared IRQ.
Clears Ref B fault IRQ.
Unused.
Rev. 0 | Page 90 of 104
AD9547
Table 127. Incremental Phase Offset Control
Address
0x0A0C
Bit
[7:3]
2
1
Bit Name
Unused
Reset phase offset
Decrement phase offset
0
Increment phase offset
Description
Unused.
Resets the incremental phase offset to 0. This is an autoclearing bit.
Decrements the incremental phase offset by the amount specified in the incremental
phase lock offset step size register (Register 0x0314 to Register 0x0315).
This is an autoclearing bit.
Increments the incremental phase offset by the amount specified in the incremental phase
lock offset step size register (Register 0x0314 to Register 0x0315).
This is an autoclearing bit.
Table 128. Reference Profile Selection State Machine Startup 1
Address
0x0A0D
1
Bit
[7:4]
3
2
1
0
Bit Name
Unused
Detect BB
Detect B
Detect AA
Detect A
Description
Unused.
Setting this bit starts the profile selection state machine for Input Reference BB.
Setting this bit starts the profile selection state machine for Input Reference B.
Setting this bit starts the profile selection state machine for Input Reference AA.
Setting this bit starts the profile selection state machine for Input Reference A.
All bits in this register are autoclearing.
Register 0x0A0E to Register 0x0A10—Reference Validation Override Controls
Table 129. Force Validation Timeout 1
Address
0x0A0E
1
Bit
[7:4]
3
Bit Name
Unused
Force Timeout BB
2
Force Timeout B
1
Force Timeout AA
0
Force Timeout A
Description
Unused.
Setting this bit emulates timeout of the validation timer for Reference BB.
This is an autoclearing bit.
Setting this bit emulates timeout of the validation timer for Reference B.
This is an autoclearing bit.
Setting this bit emulates timeout of the validation timer for Reference AA.
This is an autoclearing bit.
Setting this bit emulates timeout of the validation timer for Reference A.
This is an autoclearing bit.
All bits in this register are autoclearing.
Table 130. Reference Monitor Override 1
Address
0x0A0F
1
Bit
[7:4]
3
2
1
0
Bit Name
Unused
Ref Mon Override BB
Ref Mon Override B
Ref Mon Override AA
Ref Mon Override A
Description
Unused.
Overrides the reference monitor REF fault signal for Reference BB (default = 0, not overridden).
Overrides the reference monitor REF fault signal for Reference B (default = 0, not overridden).
Overrides the reference monitor REF fault signal for Reference AA (default = 0, not overridden).
Overrides the reference monitor REF fault signal for Reference A (default = 0, not overridden).
All bits in this register are autoclearing.
Table 131. Reference Monitor Bypass 1
Address
0x0A10
1
Bit
[7:4]
3
2
1
0
Bit Name
Unused
Ref Mon Bypass BB
Ref Mon Bypass B
Ref Mon Bypass AA
Ref Mon Bypass A
Description
Unused.
Bypasses the reference monitor for Reference BB (default = 0, not bypassed).
Bypasses the reference monitor for Reference B (default = 0, not bypassed).
Bypasses the reference monitor for Reference AA (default = 0, not bypassed).
Bypasses the reference monitor for Reference A (default = 0, not bypassed).
All bits in this register are autoclearing.
Rev. 0 | Page 91 of 104
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STATUS READBACK (REGISTER 0x0D00 TO REGISTER 0x0D19)
All bits in Register 0x0D00 to Register 0x0D19 are read only. These registers are accessible during EEPROM transactions.
Table 132. EEPROM Status
Address
0x0D00
Bit
[7:3]
2
1
0
Bit Name
Unused
Fault detected
Load in progress
Save in progress
Description
Unused.
An error occurred while saving data to or loading data from the EEPROM.
The control logic sets this bit while data is being read from the EEPROM.
The control logic sets this bit while data is being written to the EEPROM.
Table 133. SYSCLK Status
Address
0x0D01
Bit
[7:5]
4
Bit Name
Unused
Stable
[3:2]
1
0
Unused
Cal in progress
Lock detected
Description
Unused.
The control logic sets this bit when the device considers the system clock to be
stable (see the System Clock Stability Timer section).
Unused.
The control logic holds this bit set while the system clock calibration is in progress.
Indicates the status of the system clock PLL.
0 = unlocked.
1 = locked (or the PLL is disabled).
Register 0x0D02 to Register 0x0D09—IRQ Monitor
If not masked via the IRQ mask register (Address 0x0209 to Address 0x0210), the appropriate IRQ monitor bit is set to a Logic 1 when the
indicated event occurs. These bits can only be cleared via the IRQ clearing register (Address 0x0A04 to Address 0x0A0B), the reset all
IRQs bit (Register 0x0A03, Bit 1), or a device reset.
Table 134. IRQ Monitor for SYSCLK
Address
0x0D02
Bit
[7:6]
5
4
[3:2]
1
0
Bit Name
Unused
SYSCLK unlocked
SYSCLK locked
Unused
SYSCLK cal complete
SYSCLK cal started
Description
Unused.
Indicates a SYSCLK PLL state transition from locked to unlocked.
Indicates a SYSCLK PLL state transition from unlocked to locked.
Unused.
Indicates that SYSCLK calibration is complete.
Indicates that SYSCLK calibration has begun.
Table 135. IRQ Monitor for Distribution Sync, Watchdog Timer, and EEPROM
Address
0x0D03
Bit
[7:4]
3
2
1
0
Bit Name
Unused
Distribution sync
Watchdog timer
EEPROM fault
EEPROM complete
Description
Unused.
Indicates a distribution sync event.
Indicates expiration of the watchdog timer.
Indicates a fault during an EEPROM load or save operation.
Indicates successful completion of an EEPROM load or save operation.
Table 136. IRQ Monitor for the Digital PLL
Address
0x0D04
Bit
7
6
5
4
3
2
1
0
Bit Name
Switching
Closed
Free run
Holdover
Frequency unlocked
Frequency locked
Phase unlocked
Phase locked
Description
Indicates that the DPLL is switching to a new reference.
Indicates that the DPLL has entered closed-loop operation.
Indicates that the DPLL has entered free-run mode.
Indicates that the DPLL has entered holdover mode.
Indicates that the DPLL lost frequency lock.
Indicates that the DPLL has acquired frequency lock.
Indicates that the DPLL lost phase lock.
Indicates that the DPLL has acquired phase lock.
Rev. 0 | Page 92 of 104
AD9547
Table 137. IRQ Monitor for History Update, Frequency Limit, and Phase Slew Limit
Address
0x0D05
Bit
[7:5]
4
3
2
1
0
Bit Name
Unused
History updated
Frequency unclamped
Frequency clamped
Phase slew unlimited
Phase slew limited
Description
Unused.
Indicates the occurrence of a tuning word history update.
Indicates a frequency limiter state transition from clamped to unclamped.
Indicates a frequency limiter state transition from unclamped to clamped.
Indicates a phase slew limiter state transition from slew limiting to not slew limiting.
Indicates a phase slew limiter state transition from not slew limiting to slew limiting.
Table 138. IRQ Monitor for Reference Inputs
Address
0x0D06
0x0D07
0x0D08
0x0D09
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
[7:0]
[7:0]
Bit Name
Ref AA new profile
Ref AA validated
Ref AA fault cleared
Ref AA fault
Ref A new profile
Ref A validated
Ref A fault cleared
Ref A fault
Ref BB new profile
Ref BB validated
Ref BB fault cleared
Ref BB fault
Ref B new profile
Ref B validated
Ref B fault cleared
Ref B fault
Unused
Description
Indicates that Ref AA has switched to a new profile.
Indicates that Ref AA has been validated.
Indicates that Ref AA has been cleared of a previous fault.
Indicates that Ref AA has been faulted.
Indicates that Ref A has switched to a new profile.
Indicates that Ref A has been validated.
Indicates that Ref A has been cleared of a previous fault.
Indicates that Ref A has been faulted.
Indicates that Ref BB has switched to a new profile.
Indicates that Ref BB has been validated.
Indicates that Ref BB has been cleared of a previous fault.
Indicates that Ref BB has been faulted.
Indicates that Ref B has switched to a new profile.
Indicates that Ref B has been validated.
Indicates that Ref B has been cleared of a previous fault.
Indicates that Ref B has been faulted.
Unused.
Table 139. DPLL Status
Address
0x0D0A
0x0D0B
Bit
7
6
5
4
3
2
1
0
7
6
[5:3]
Bit Name
Offset slew limiting
Phase build-out
Frequency lock
Phase lock
Loop switching
Holdover
Active
Free running
Frequency clamped
History available
Active reference priority
2
[1:0]
Unused
Active reference
Description
The current closed-loop phase offset is rate limited.
A phase build-out transition was made to the currently active reference.
The DPLL has achieved frequency lock.
The DPLL has achieved phase lock.
The DPLL is in the process of a reference switchover.
The DPLL is in holdover mode.
The DPLL is active (that is, operating in a closed-loop condition).
The DPLL is free running (that is, operating in an open-loop condition).
The upper or lower frequency tuning word clamp is in effect.
There is sufficient tuning word history available for holdover operation.
Priority value of the currently active reference.
000 = highest priority.
111 = lowest priority.
Unused.
Index of the currently active reference.
00 = Reference A.
01 = Reference AA.
10 = Reference B.
11 = Reference BB.
Rev. 0 | Page 93 of 104
AD9547
Table 140. Input Reference Status
Address
0x0D0C
0x0D0D
0x0D0E
0x0D0F
0x0D10
0x0D11
0x0D12
0x0D13
Bit
7
[6:4]
Bit Name
Profile selected
Selected profile
3
2
1
Valid
Fault
Fast
0
Slow
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Unused
Description
The control logic sets this bit when it assigns Ref A to one of the eight profiles.
The index (0 to 7) of the profile assigned to Ref A.
Note that these bits are meaningless unless Bit 7 = 1.
Ref A is valid for use (that is, it is unfaulted, and its validation timer has expired).
Ref A is not valid for use.
If Bit 7 = 1, this bit indicates that the frequency of Ref A is higher than allowed by its profile settings.
If Bit 7 = 0, this bit indicates that the frequency of Ref A is above the maximum input reference
frequency supported by the device.
If Bit 7 = 1, this bit indicates that the frequency of Ref A is lower than allowed by its profile settings.
If Bit 7 = 0, this bit indicates that the frequency of Ref A is below the minimum input reference
frequency supported by the device.
Same as 0x0D0C but for REF AA instead of REF A.
Same as 0x0D0C but for REF B instead of REF A.
Same as 0x0D0C but for REF BB instead of REF A.
Unused.
Table 141. Holdover History 1
Address
0x0D14
0x0D15
0x0D16
0x0D17
0x0D18
0x0D19
1
Bit
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
Bit Name
Tuning word
history
Description
Tuning word readback, Bits[7:0].
Tuning word readback, Bits[15:8].
Tuning word readack, Bits[23:16].
Tuning word readback, Bits[31:24].
Tuning word readback, Bits[39:32].
Tuning word readback, Bits[47:40].
These registers contain the current 48-bit DDS frequency tuning word generated by the tuning word history logic.
NONVOLATILE MEMORY (EEPROM) CONTROL (REGISTER 0x0E00 TO REGISTER 0x0E03)
Table 142. Write Protect
Address
0x0E00
Bit
[7:2]
1
Bit Name
Unused
Half rate mode
0
Write enable
Description
Unused.
EEPROM serial communication rate.
0 (default) = 400 kHz (normal).
1 = 200 kHz.
EEPROM write enable/protect.
0 (default) = EEPROM is write protected.
1 = EEPROM is write enabled.
Table 143. Condition
Address
0x0E01
Bit
[7:5]
[4:0]
Bit Name
Unused
Condition value
Description
Unused.
When set to a nonzero value (default = 0), these bits establish the condition for EEPROM downloads.
Bit Name
Unused
Save to EEPROM
Description
Unused.
Upload data to the EEPROM based on in the EEPROM storage sequence. This is an autoclearing bit.
Table 144. Save
Address
0x0E02
Bit
[7:1]
0
Rev. 0 | Page 94 of 104
AD9547
Table 145. Load
Address
0x0E03
Bit
[7:2]
1
0
Bit Name
Unused
Load from
EEPROM
Unused
Description
Unused.
Download data from the EEPROM. This is an autoclearing bit.
Unused.
EEPROM STORAGE SEQUENCE (REGISTER 0x0E10 TO REGISTER 0x0E3F)
The default settings of Register 0x0E10 to Register 0x0E33 embody a sample scratch pad instruction sequence. The following is a description
of the register defaults under the assumption that the controller has been instructed to carry out an EEPROM storage sequence.
Table 146. EEPROM Storage Sequence for System Clock Settings
Address
0x0E10
Bit
[7:0]
Bit Name
System clock
0x0E11
0x0E12
[7:0]
[7:0]
System clock
0x0E13
[7:0]
I/O update
Description
The default value of this register is 0x08, which the controller interprets as a data instruction. Its
decimal value is 8, which tells the controller to transfer nine bytes of data (8 + 1) beginning at the
address specified by the next two bytes. The controller stores 0x08 in the EEPROM and increments
the EEPROM address pointer.
The default value of these two registers is 0x0100. Note that Register 0x0E11 and Register 0x0E12 are
the most significant and least significant bytes of the target address, respectively. Because the
previous register contains a data instruction, these two registers define a starting address (in this
case, 0x0100). The controller stores 0x0100 in the EEPROM and increments the EEPROM pointer by 2.
It then transfers nine bytes from the register map (beginning at Address 0x0100) to the EEPROM and
increments the EEPROM address pointer by 10 (nine data bytes and one checksum byte). The nine
bytes transferred correspond to the system clock parameters in the register map.
The default value of this register is 0x80, which the controller interprets as an I/O update instruction.
The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer.
Table 147. EEPROM Storage Sequence for System Clock Calibration
Address
0x0E14
Bit
[7:0]
Bit Name
SYSCLK calibrate
Description
The default value of this register is 0xA0, which the controller interprets as a calibrate instruction.
The controller stores 0xA0 in the EEPROM and increments the EEPROM address pointer.
Table 148. EEPROM Storage Sequence for General Configuration Settings
Address
0x0E15
Bit
[7:0]
Bit Name
General
Description
The default value of this register is 0x14, which the controller interprets as a data instruction. Its
decimal value is 20, which tells the controller to transfer 21 bytes of data (20 + 1) beginning at the
address specified by the next two bytes. The controller stores 0x14 in the EEPROM and increments
the EEPROM address pointer.
0x0E16
0x0E17
[7:0]
[7:0]
General
The default value of these two registers is 0x0200. Note that Register 0x0E16 and Register 0x0E17 are
the most significant and least significant bytes of the target address, respectively. Because the
previous register contains a data instruction, these two registers define a starting address (in this case,
0x0200). The controller stores 0x0200 in the EEPROM and increments the EEPROM pointer by 2. It then
transfers 21 bytes from the register map (beginning at Address 0x0200) to the EEPROM and increments the EEPROM address pointer by 22 (21 data bytes and one checksum byte). The 21 bytes
transferred correspond to the general configuration parameters in the register map.
Table 149. EEPROM Storage Sequence for DPLL Settings
Address
0x0E18
Bit
[7:0]
Bit Name
DPLL
0x0E19
0x0E1A
[7:0]
[7:0]
DPLL
Description
The default value of this register is 0x1B, which the controller interprets as a data instruction. Its
decimal value is 27, which tells the controller to transfer 28 bytes of data (27 + 1) beginning at the
address specified by the next two bytes. The controller stores 0x1B in the EEPROM and increments the
EEPROM address pointer.
The default value of these two registers is 0x0300. Note that Register 0x0E19 and Register 0x0E1A are
the most significant and least significant bytes of the target address, respectively. Because the
previous register contains a data instruction, these two registers define a starting address (in this case,
0x0300). The controller stores 0x0300 in the EEPROM and increments the EEPROM pointer by 2. It then
transfers 28 bytes from the register map (beginning at Address 0x0300) to the EEPROM and increments
the EEPROM address pointer by 29 (28 data bytes and one checksum byte). The 28 bytes transferred
correspond to the DPLL parameters in the register map.
Rev. 0 | Page 95 of 104
AD9547
Table 150. EEPROM Storage Sequence for Clock Distribution Settings
Address
0x0E1B
Bit
[7:0]
Bit Name
Clock distribution
0x0E1C
0x0E1D
[7:0]
[7:0]
Clock distribution
0x0E1E
[7:0]
I/O update
Description
The default value of this register is 0x19, which the controller interprets as a data instruction. Its
decimal value is 25; this tells the controller to transfer 26 bytes of data (25 + 1) beginning at the
address specified by the next two bytes. The controller stores 0x19 in the EEPROM and
increments the EEPROM address pointer.
The default value of these two registers is 0x0400. Note that Register 0x0E1C and Register 0x0E1D
are the most significant and least significant bytes of the target address, respectively. Because
the previous register contains a data instruction, these two registers define a starting address
(in this case, 0x0400). The controller stores 0x0400 in the EEPROM and increments the EEPROM
pointer by 2. It then transfers 26 bytes from the register map (beginning at Address 0x0400) to
the EEPROM and increments the EEPROM address pointer by 27 (26 data bytes and one checksum
byte). The 26 bytes transferred correspond to the clock distribution parameters in the register map.
The default value of this register is 0x80, which the controller interprets as an I/O update
instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer.
Table 151. EEPROM Storage Sequence for Reference Input Settings
Address
0x0E1F
Bit
[7:0]
Bit Name
Reference inputs
0x0E20
0x0E21
[7:0]
[7:0]
Reference inputs
Description
The default value of this register is 0x07, which the controller interprets as a data instruction. Its
decimal value is 7, which tells the controller to transfer eight bytes of data (7 + 1), beginning at the
address specified by the next two bytes. The controller stores 0x07 in the EEPROM and increments
the EEPROM address pointer.
The default value of these two registers is 0x0500. Note that Register 0x0E20 and Register 0x0E21
are the most significant and least significant bytes of the target address, respectively. Because
the previous register contains a data instruction, these two registers define a starting address
(in this case, 0x0500). The controller stores 0x0500 in the EEPROM and increments the EEPROM
pointer by 2. It then transfers eight bytes from the register map (beginning at Address 0x0500) to the
EEPROM and increments the EEPROM address pointer by nine (eight data bytes and one checksum
byte). The eight bytes transferred correspond to the reference inputs parameters in the register map.
Table 152. EEPROM Storage Sequence for Profile 0 and Profile 1 Settings
Address
0x0E22
Bit
[7:0]
Bit Name
Profile 0 and Profile 1
0x0E23
0x0E24
[7:0]
[7:0]
Profile 0 and Profile 1
Description
The default value of this register is 0x63, which the controller interprets as a data instruction. Its
decimal value is 99, which tells the controller to transfer 100 bytes of data (99 + 1), beginning at the
address specified by the next two bytes. The controller stores 0x63 in the EEPROM and
increments the EEPROM address pointer.
The default value of these two registers is 0x0600. Note that Register 0x0E23 and Register 0x0E24
are the most significant and least significant bytes of the target address, respectively. Because
the previous register contains a data instruction, these two registers define a starting address
(in this case, 0x0600). The controller stores 0x0600 in the EEPROM and increments the EEPROM
pointer by 2. It then transfers 100 bytes from the register map (beginning at Address 0x0600) to
the EEPROM and increments the EEPROM address pointer by 101 (100 data bytes and one checksum
byte). The 99 bytes transferred correspond to the Profile 0 and Profile 1 parameters in the
register map.
Table 153. EEPROM Storage Sequence for Profile 2 and Profile 3 Settings
Address
0x0E25
Bit
[7:0]
Bit Name
Profile 2 and Profile 3
0x0E26
0x0E27
[7:0]
[7:0]
Profile 2 and Profile 3
Description
The default value of this register is 0x63, which the controller interprets as a data instruction. Its
decimal value is 99, which tells the controller to transfer 100 bytes of data (99 + 1), beginning at
the address specified by the next two bytes. The controller stores 0x63 in the EEPROM and
increments the EEPROM address pointer.
The default value of these two registers is 0x0680. Note that Register (0x0E26 and Register 0x0E27
are the most significant and least significant bytes of the target address, respectively. Because
the previous register contains a data instruction, these two registers define a starting address
(in this case, 0x0680). The controller stores 0x0680 in the EEPROM and increments the EEPROM
pointer by 2. It then transfers 100 bytes from the register map (beginning at Address 0x0680) to
the EEPROM and increments the EEPROM address pointer by 101 (100 data bytes and one checksum
byte). The 99 bytes transferred correspond to the Profile 2 and Profile 3 parameters in the
register map.
Rev. 0 | Page 96 of 104
AD9547
Table 154. EEPROM Storage Sequence for Profile 4 and Profile 5 Settings
Address
0x0E28
Bit
[7:0]
Bit Name
Profile 4 and Profile 5
Description
The default value of this register is 0x63, which the controller interprets as a data instruction.
Its decimal value is 99, which tells the controller to transfer 100 bytes of data (99 + 1)
beginning at the address specified by the next two bytes. The controller stores 0x63 in the
EEPROM and increments the EEPROM address pointer.
0x0E29
0x0E2A
[7:0]
[7:0]
Profile 4 and Profile 5
The default value of these two registers is 0x0700. Note that Register 0x0E29 and Register 0x0E2A
are the most significant and least significant bytes of the target address, respectively. Because
the previous register contains a data instruction, these two registers define a starting address
(in this case, 0x0700). The controller stores 0x0700 in the EEPROM and increments the EEPROM
pointer by 2. It then transfers 100 bytes from the register map (beginning at Address 0x0700)
to the EEPROM and increments the EEPROM address pointer by 101 (100 data bytes and one
checksum byte). The 99 bytes transferred correspond to the Profile 4 and Profile 5 parameters
in the register map.
Table 155. EEPROM Storage Sequence for Profile 6 and Profile 7 Settings
Address
0x0E2B
Bit
[7:0]
Bit Name
Profile 6 and Profile 7
0x0E2C
0x0E2D
[7:0]
[7:0]
Profile 6 and Profile 7
0x0E2E
[7:0]
I/O update
Description
The default value of this register is 0x63, which the controller interprets as a data instruction.
Its decimal value is 99, this tells the controller to transfer 100 bytes of data (99 + 1) beginning
at the address specified by the next two bytes. The controller stores 0x63 in the EEPROM and
increments the EEPROM address pointer.
The default value of these two registers is 0x0780. Note that Register 0x0E2C and Register 0x0E2D
are the most significant and least significant bytes of the target address, respectively. Because
the previous register contains a data instruction, these two registers define a starting address
(in this case, 0x0780). The controller stores 0x0780 in the EEPROM and increments the EEPROM
pointer by 2. It then transfers 100 bytes from the register map (beginning at Address 0x0780)
to the EEPROM and increments the EEPROM address pointer by 101 (100 data bytes and one
checksum byte). The 99 bytes transferred correspond to the Profile 6 and Profile 7 parameters
in the register map.
The default value of this register is 0x80, which the controller interprets as an I/O update
instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer.
Table 156. EEPROM Storage Sequence for Operational Control Settings
Address
0x0E2F
Bit
[7:0]
Bit Name
Operational controls
0x0E30
0x0E31
[7:0]
[7:0]
Operational controls
0x0E32
[7:0]
I/O update
Description
The default value of this register is 0x10, which the controller interprets as a data instruction.
Its decimal value is 16, this tells the controller to transfer 17 bytes of data (16 + 1) beginning at
the address specified by the next two bytes. The controller stores 0x10 in the EEPROM and
increments the EEPROM address pointer.
The default value of these two registers is 0x0A00. Note that Register 0x0E30 and Register 0x0E31
are the most significant and least significant bytes of the target address, respectively. Because
the previous register contains a data instruction, these two registers define a starting address
(in this case, 0x0A00). The controller stores 0x0A00 in the EEPROM and increments the EEPROM
pointer by 2. It then transfers 17 bytes from the register map (beginning at Address 0x0A00) to
the EEPROM and increments the EEPROM address pointer by 18 (17 data bytes and one checksum
byte). The 17 bytes transferred correspond to the operational controls parameters in the
register map.
The default value of this register is 0x80, which the controller interprets as an I/O update
instruction. The controller stores 0x80 in the EEPROM and increments the EEPROM address pointer.
Table 157. EEPROM Storage Sequence for End of Data
Address
0x0E33
Bit
[7:0]
Bit Name
End of data
Description
The default value of this register is 0xFF, which the controller interprets as an end instruction.
The controller stores this instruction in the EEPROM, resets the EEPROM address pointer, and
enters an idle state. Note that, if this were a pause rather than an end instruction, the controller
actions would be the same except that the controller would not reset the EEPROM address pointer.
Rev. 0 | Page 97 of 104
AD9547
APPLICATIONS INFORMATION
POWER SUPPLY PARTITIONS
THERMAL PERFORMANCE
The AD9547 features multiple power supplies, and their power
consumption varies with the AD9547 configuration. This section
provides information about which power supplies can be grouped
together and how the power consumption of each block varies
with frequency.
The AD9547 is specified for a case temperature (TCASE). To ensure
that TCASE is not exceeded, an airflow source can be used. Use the
following equation to determine the junction temperature on
the application PCB:
The numbers quoted in this section are for comparison only. Refer
to the Specifications section for exact numbers. With each group,
bypass capacitors of 1 μF in parallel with 10 μF should be used.
where:
TJ is the junction temperature in degrees Celsius (°C).
TCASE is the case temperature in degrees Celsius (°C) measured
by the customer at the top center of the package.
ΨJT is the value that is indicated in Table 159.
PD is the power dissipation (see the Power Dissipation section).
Upon applying power to the device, internal circuitry monitors
the 1.8 V digital core supply and the 3.3 V digital I/O supply.
When these supplies cross the desired threshold level, the device
generates an internal 10 μs reset pulse. This pulse does not appear
on the RESET pin.
3.3 V Supplies
The 3.3 V supply domain consists of two main partitions: digital
(DVDD3) and analog (AVDD3). These two supply domains
must be kept separate.
Furthermore, the AVDD3 consists of two subdomains: the clock
distribution output domain (Pin 25, Pin 31) and the rest of the
AVDD3 supply connections. Generally, the ADD3 supply domains
can be joined together. However, if an application requires 1.8 V
CMOS driver operation in the clock distribution output block,
provide one 1.8 V supply domain to power the clock distribution
output block. Each output driver has a dedicated supply pin, as
shown in Table 158.
TJ = TCASE + (ΨJT × PD)
Values of θJA are provided for package comparison and PCB design
considerations. θJA can be used for a first-order approximation of TJ
using the following equation:
TJ = TA + (θJA × PD)
where TA is the ambient temperature in degrees Celsius (°C).
Values of θJC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Values of θJB are provided for package comparison and PCB
design considerations.
Table 158. Output Driver Supply Pins
Output Driver
OUT0
OUT1
Supply Pin
25
31
1.8 V Supplies
The 1.8 V supply domain consists of two main partitions: digital
(DVDD) and analog (AVDD). These two supply domains must
be kept separate.
Table 159. Thermal Parameters for the AD9547 64-Lead LFCSP Package
Symbol
θJA
θJMA
θJMA
θJB
θJC
ΨJT
1
2
Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board 1
Junction-to-ambient thermal resistance, 0.0 m/sec air flow per JEDEC JESD51-2 (still air)
Junction-to-ambient thermal resistance, 1.0 m/sec air flow per JEDEC JESD51-6 (moving air)
Junction-to-ambient thermal resistance, 2.5 m/sec air flow per JEDEC JESD51-6 (moving air)
Junction-to-board thermal resistance, per JEDEC JESD51-8 (still air)
Junction-to-case thermal resistance
Junction-to-top-of-package characterization parameter, 0 m/sec airflow per JEDEC JESD51-2 (still air)
Value 2
21.7
18.9
16.9
11.3
1.2
0.1
The exposed pad on the bottom of the package must be soldered to ground to achieve the specified thermal performance.
Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the
application to determine whether they are similar to those assumed in these calculations.
Rev. 0 | Page 98 of 104
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
AD9547
CALCULATING THE DIGITAL FILTER COEFFICIENTS
The digital loop filter coefficients (α, β, γ, and δ, as shown in
Figure 38) relate to the time constants (T1, T2, and T3) that are
associated with the equivalent analog circuit for a third-order loop
filter (see Figure 64).
FROM
CHARGE
PUMP
R2
C1
C3
C2
08300-042
30,517,578,125
fS
233
D=S+
The design process begins by deciding on two design parameters
related to the second-order loop filter shown in Figure 65: the
desired open-loop bandwidth (fP) and the phase margin (θ).
U
+1
V
where S, U, and V are the integer and fractional feedback divider
values that reside in the profile registers.
Keep in mind that the desired integer feedback divide ratio is one
more than the stored value of S (hence, the +1 term in the
equation for D in this equation). This leads to the digital filter
coefficients given by
R2
TO
VCO
C1
2
K=
Figure 64. Third-Order Analog Loop Filter
FROM
CHARGE
PUMP
1
ωC (T1 + T3 )
T2 =
Calculation of the digital loop filter coefficients requires a
scaling constant, K (related to the system clock frequency, fS),
and the PLL feedback divide ratio, D.
TO
VCO
R3
It can also be shown that the adjusted open-loop bandwidth
leads to T2 (the secondary time constant of the second-order
loop filter), which is expressed as
08300-043
C2
ωC 2T2 D
T1K
β=
− 32 ⎛ 1
1 ⎞
⎜ − ⎟
f S ⎜⎝ T1 T2 ⎟⎠
γ=
−32
f ST1
δ=
32
f ST3
Figure 65. Second-Order Analog Loop Filter
An analysis of the second-order loop filter leads to its primary
time constant, T1. It can be shown that T1 is expressible in terms
of fP and θ as
1 − sin(θ)
T1 =
where ωp = 2πfP
ωP cos(θ)
An analysis of the third-order loop filter leads to the definition
of another time constant, T3. It can be shown that T3 is expressible
in terms of the desired amount of additional attenuation introduced by R3 and C3 at some specified frequency offset (fOFFSET)
from the PLL output frequency.
T3 =
ATTEN
10 10
ωOFFSET
1 + (ωCT2 )2
Calculation of the coefficient register values requires the application of some special functions, which are described as follows:
The if() function
y = if (test_statement, true_value, false_value)
−1
where ωOFFSET = 2πfOFFSET
Note that ATTEN is the desired excess attenuation in decibels (dB).
Furthermore, ATTEN and ωOFFSET should be chosen so that
1
T3 ≤
5 fP
(T1 + T3 )tan(θ) ⎡⎢
T1T3 + (T1 + T3 )2 ⎢⎣
where:
test_statement is a conditional expression (for example, x < 3).
true_value is what y equals if the conditional expression is true.
false_value is what y equals if the conditional expression is false.
The round() function
y = round(x)
With an expression for T1 and T3, it is possible to define an adjusted
open-loop bandwidth (fC) that is slightly less than fP. It can be
shown that ωC (fC expressed as a radian frequency) is expressible
in terms of T1, T3, and θ (phase margin) as follows:
ωC =
(1 + (ωCT1 )2 )(1 + (ωCT3 )2 )
α=
1+
⎤
T1T3 + (T1 + T3 )2
− 1⎥
2
[(T1 + T3 )tan(θ)] ⎥⎦
If x is an integer, then y = x. Otherwise, y is the nearest integer to x.
For example, round(2.1) = 2, round(2.5) = 3, and round(−3.1) = −3.
The ceil() function
y = ceil(x)
If x is an integer, then y = x. Otherwise, y is the next integer to
the right on the number line. For example, ceil(2.8) = 3,
whereas ceil(−2.8) = −2.
Rev. 0 | Page 99 of 104
AD9547
Calculation of the α Register Values
The min() function
The quantized α coefficient consists of four components: α0, α1,
α2, and α3, according to
y = min(x0, x1, ... xn)
where:
x0 through xn is a list of real numbers.
y is the number in the list that is the farthest to the left on the
number line.
α ≈ αquantized = α0 × 216 − α
1
The max() function
y = max(x0, x1, ... xn)
where:
x0 through xn is a list of real numbers.
y is the number in the list that is the farthest to the right on the
number line.
where:
α0, α1, α2, and α3 are the register values.
α2 provides front-end gain.
α3 provides back-end gain.
α1 shifts the binary decimal point of α0 to the left to accommodate
small values of α.
Calculation of α1 is a two-step process, as follows:
w = if(α <1, −ceil(log2(α)), 0)
α1 = if(α <1, min[63, max(0, w)], 0)
The log2() function
log2(x) =
+ α2 + α3
If gain is necessary (that is, α > 1), then it is beneficial to apply
most or all of it to the front-end gain (α2) implying that the calculation of α2 is to be done before that of α3. Calculation of α2
is a three-step process that leads directly to the calculation of α3.
ln(x )
ln(2)
where: ln() is the natural log function.
x is a positive, nonzero number.
Assume that the coefficient calculations for α, β, γ, and δ above
yield the following results:
x = if(α > 1, ceil(log2(α)), 0)
y = if(α > 1, min[22, max(0, x)], 0)
α = 0.012735446
α2 = if(y ≥ 8, 7, y)
β = −6.98672 × 10−5
α3 = if(y ≥ 8, y – 7, 0)
Calculation of α0 is a two-step process, as follows:
γ = −7.50373 × 10−5
z = round(α × 216 + α
δ = 0.002015399
1
These values are floating point numbers that must be quantized
according to the bit widths of the linear and exponential components of the coefficients as they appear in the register map.
Note that the calculations that follow indicate a positive value
for the register entries of β and γ. The reason is that β and γ,
which are supposed to be negative values, are stored in the
AD9547 registers as positive values. The AD9547 converts the
stored values to negative numbers within its signal processing
core. A detailed description of the register value computations
for α, β, γ, and δ follows.
− α2 − α3
)
α0 = min[65535, max(1, z)
Using the example value of α = 0.012735446 yields
w = 6, so α1 = 6
x = 0 and y = 0, so α2 = 0 and α3 = 0
z = 53416.332099584, so α0 = 53416
This leads to the following quantized value, which is very close
to the desired value of 0.012735446:
αquantized = 53416 × 2−22 ≈ 0.01273566821
Rev. 0 | Page 100 of 104
AD9547
Calculation of the β Register Values
Using the example value of −γ = 7.50373 × 10−5 yields
The quantized β coefficient consists of two components, β0 and
β1, according to
−β ≈ βquantized = β0 × 2−(17 + β )
x = 13, so γ1 = 13
y = 80570.6873700352, so γ0 = 80571
1
This leads to the following quantized value, which is very close
to the desired value of 7.50373 × 10−5:
where β0 and β1 are the register values.
Calculation of β1 is a two-step process that leads to the
calculation of β0, which is also a two-step process.
γquantized = 80571 × 2−30 ≈ 7.503759116 × 10−5
Calculation of the δ Register Values
x = −ceil(log2( β ))
The quantized δ coefficient consists of two components, δ0 and
δ1, according to
β1 = min[31, max(0, x)]
δ ≈ δquantized = δ0 × 2−(15 + δ )
y = round( β × 217 + β )
1
1
where δ0 and δ1 are the register values.
β0 = min[131071, max(1, y)]
Calculation of δ1 is a two-step process that leads to the
calculation of δ0, which is also a two-step process.
Using the example value of −β = 6.98672 × 10−5 yields
x = 13, so β1 = 13
x = −ceil(log2(δ))
y = 75019.3347657728, so β0 = 75019
δ1 = min[31, max(0, x)]
This leads to the following quantized value, which is very close
to the desired value of 6.98672 × 10−5:
Using the example value of δ = 0.002015399, the preceding
formulas yield
Calculation of the γ Register Values
The quantized γ coefficient consists of two components, γ0 and
γ1, according to
1
where γ0 and γ1 are the register values.
Calculation of γ1 is a two-step process that leads to the
calculation of γ0, which is also a two-step process.
1
δ0 = min[32767, max(1, y)]
βquantized = 75019 × 2−30 ≈ 6.986688823 × 10−5
−γ ≈ γquantized = γ0 × 2−(17 + γ )
y = round(δ × 215 + δ )
x = 8, so δ1 = 8
y = 16906.392174592, so δ0 = 16906
This leads to the following quantized value, which is very close
to the desired value of 0.002015399:
δquantized = 16906 × 2−23 ≈ 0.002015352249
x = −ceil(log2( γ ))
y1 = min[31, max(0, x)]
y = round( γ × 217 + γ )
1
γ0 = min[131071, max(1, y)]
Rev. 0 | Page 101 of 104
AD9547
OUTLINE DIMENSIONS
0.60 MAX
9.00
BSC SQ
0.60
MAX
64
49
48
PIN 1
INDICATOR
1
PIN 1
INDICATOR
8.75
BSC SQ
0.50
BSC
0.50
0.40
0.30
1.00
0.85
0.80
33
32
16
17
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
6.35
6.20 SQ
6.05
EXPOSED PAD
(BOTTOM VIEW)
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
091707-C
TOP VIEW
Figure 66. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9547BCPZ 1
AD9547BCPZ-REEL71
AD9547/PCBZ1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 102 of 104
Package Option
CP-64-4
CP-64-4
AD9547
NOTES
Rev. 0 | Page 103 of 104
AD9547
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08300-0-7/09(0)
Rev. 0 | Page 104 of 104