19-1433; Rev 1; 3/99 2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier Features The MAX3866 combined transimpedance preamplifier and limiting postamplifier is intended for application in SDH/SONET systems operating at 2.488Gbps. It operates from a single +3.3V or +5V supply and provides a differential output signal. The differential outputs are each 50Ω reverse terminated (100Ω differential termination) for low-noise and high-speed signal performance. The small-signal bandwidth and noise performance is specified for a source capacitance of 0.5pF. When the MAX3866 is used with the PIN photodetector, sensitivities better than -22dBm can be achieved. The MAX3866 is equipped with a programmable TTL lossof-power (LOP) output. ♦ Input Sensitivities Better than -22dBm (7.8µAp-p) ♦ Overdrive Capability Better than +1.4dBm (2.5mAp-p) ♦ Single +3.3V or +5V Supply ♦ 165mW Power Dissipation (at 3.3V) ♦ 1.8GHz Analog Input Bandwidth ♦ Programmable Loss-of-Power Indicator ♦ 100Ω Differential Output Ordering Information Applications SDH/SONET Transmission Systems PART PIN/Preamplifier Receivers TEMP. RANGE MAX3866E/D (see Note) PIN-PACKAGE Dice Note: Dice are designed to operate over a -40°C to +120°C junction temperature (Tj) range, but are tested and guaranteed at TA = +25°C. 2.488Gbps ATM Receivers Regenerators for SDH/SONET Pad Configuration appears at end of data sheet. Typical Application Circuit +3.3V VCCS VCCD FIL PHOTODIODE 200Ω OUT+ LIMITING POSTAMP PREAMP IN+ Zo = 50Ω MAX3875 CLOCK AND DATA RECOVERY OUTZo = 50Ω MAX3866 CHF+ CHF- PDC LOP INV CHF RPD ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX3866 General Description MAX3866 2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier ABSOLUTE MAXIMUM RATINGS VCCD Voltage .......................................................-0.5V to +7.0V VCCS Voltage ...............0 ≤ VCCS ≤ VCCD and if VCCD ≥ 3.13V then 3.13V ≤ VCCS ≤ VCCD CHF+, CHF-, FIL, INV, LOP Voltage .......-0.5V to (VCCD + 0.5V) IN-, IN+ Voltage.....................................................-0.5V to +1.0V CPD+, CPD- Voltage ................(VCCD - 1.6V) to (VCCD + 0.5V) OUT+, OUT- Voltage ................(VCCD - 1.1V) to (VCCD + 0.5V) IN Current.......................................................................0 to 3mA PDC Current..................................................................-1mA to 0 Operating Junction Temperature Range (Tj ).....-55°C to +125°C Storage Temperature Range .............................-60°C to +160°C Processing Temperature (Die).........................................+400°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCCD = VCCS = +3.3V ±5% or VCCD = +5.0V ±10%, VCCS = open, Tj = -40°C to +120°C, unless otherwise noted. Typical values are at +3.3V and Tj = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS mA Supply Current IVCC 50 73 Input Bias Voltage VIN 0.84 0.95 V 105 120 Ω VCCD V Differential Output Impedance ZOUT 90 LOP Output High Voltage VOH Load = 4.7kΩ to VCCD (Note 7) LOP Output Low Voltage VOL Load = 4.7kΩ to VCCD (Note 7) Differential Output Voltage Swing VOD RL = 100Ω (differential), IIN ≥ 7µAp-p Output Common-Mode Voltage VCM RL = 100Ω (differential) VCCD - 0.1 0.4 100 V 145 mVp-p VCCD - 0.12 V AC ELECTRICAL CHARACTERISTICS (VCCD = VCCS = +3.3V ±5% or VCCD = +5.0V ±10%, VCCS = open, Tj = -40°C to +120°C, unless otherwise noted. Typical values are at +3.3V and Tj = +25°C.) (Notes 1, 2) PARAMETER Small-Signal Bandwidth SYMBOL Input Sensitivity IIN Input-Referred RMS Noise NIN Low-Frequency Cutoff CONDITIONS MIN BW 2.5Gbps, 223 - 1 PRBS, BER ≤ 10-10, 7.8 CIN = 0.5pF, Tj = +120°C CIN = 0.5pF, Tj = +120°C 433 fL 25 LOP Hysteresis Electrical (Note 4), low LOP assert, RPD = 510Ω 3 LOP Assert Level RPD = 510Ω LOP Deassert Level RPD = 510Ω PSRR MAX 1.8 f ≤ 2MHz, 100mVp-p Power-Supply Rejection Ratio TYP UNITS GHz (Note 3) µAp-p 566 nA 100 kHz 30 dB dB 0.9 µA 8.0 µA Output Edge Speed tr, tf 20% to 80% (Note 5) 50 70 ps Pulse-Width Distortion PWD (Notes 5, 6) 21 80 ps Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: 2 CIN = total capacitance on IN. AC parameters are guaranteed by design and characterization. See Typical Operating Characteristics for worst-case distribution. Hysteresis = 20 log (VDEASSERT / VASSERT). IIN = 2.5mA. PWD = [(2 · Pulse Width) - Period] / 2. External load not required for normal operation. _______________________________________________________________________________________ 2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier 12 PWD (ps) DEASSERT ASSERT 40 8 6 30 4 20 10 2 0 0 -20 0 20 40 60 TEMPERATURE (¡C) DIFFERENTIAL OUTPUT VOLTAGE vs. TEMPERATURE SUPPLY CURRENT vs. TEMPERATURE 135 130 125 120 115 MAX3866 TOC05 80 70 60 3.47V 50 40 100 3.14V -40 -20 0 20 40 60 80 3.10 -50 -30 -20 0 20 40 60 140 135 125 120 115 110 -30 -10 10 30 50 70 90 1 10 100 1k PULSE-WIDTH DISTORTION vs. INPUT CURRENT ELECTRICAL EYE DIAGRAM ELECTRICAL EYE DIAGRAM MAX3866 TOC07 10k MAX3866 TOC09 INPUT CURRENT (µA) MAX3866 TOC08 TEMPERATURE (°C) 15 100 130 TEMPERATURE (°C) 20 80 100 -50 100 OUT- 3.15 105 30 -60 OUT+ 3.20 100 110 105 3.25 OUTPUT VOLTAGE vs. INPUT CURRENT 90 SUPPLY CURRENT (mA) 140 3.30 TEMPERATURE (°C) 100 MAX3866 TOC04 145 80 OUTPUT VOLTAGE (mVp-p) -40 RPD (Ω) 150 3.35 3.00 -60 100 3.40 3.05 IN+ = 100µA 10 DIFFERENTIAL OUTPUT VOLTAGE (mVp-p) 10 3.45 MAX3866 TOC06 60 MAX3866 toc03 14 3.50 COMMON-MODE VOLTAGE (V) 70 MAX3866 TOC02 80 ASSERT/DEASSERT (µA) 16 MAX3866 TOC01 90 50 OUTPUT COMMON-MODE VOLTAGE vs. TEMPERATURE PULSE-WIDTH DISTORTION vs. TEMPERATURE LOP ASSERT/DEASSERT vs. RPD PWD (ps) 10 5 20mV/ div 0 INPUT = 8µAp-p, 2.5Gbps, 223-1PRBS RL = 100Ω DIFFERENTIAL -5 20mV/ div INPUT = 2.5mAp-p, 2.5Gbps, 223-1PRBS RL = 100Ω DIFFERENTIAL -10 -15 -20 1 10 100 1k 10k 50ps 50ps INPUT CURRENT (µA) _______________________________________________________________________________________ 3 MAX3866 Typical Operating Characteristics (VCCD = VCCS = +3.3V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VCCD = VCCS = +3.3V, TA = +25°C, unless otherwise noted.) 30 MAX3866 toc10 99 98 25 PERCENT OF UNITS (%) 97 96 95 94 93 92 91 MAX3866 toc11 DISTRIBUTION OF ELECTRICAL SENSITIVITY (WORST CASE) SMALL-SIGNAL IMPEDANCE vs. FREQUENCY TRANSIMPEDANCE (20log (VOUTp-p/IN+)) MAX3866 2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier VCC = +3.14V TO +5.5V Tj = +120°C 20 15 10 5 90 0 89 0.01 0.1 1 10 100 1000 7.28 FREQUENCY (MHz) 7.71 8.14 8.57 ELECTRICAL SENSITIVITY (µAp-p) Pad Description PAD NAME FUNCTION VCCS Positive Supply Voltage of Input Stage. Apply +3.3V if VCCD = +3.3V. If VCCD > +3.47V, disconnect from supply and decouple to GND. CHF+ External Filter Capacitor. A capacitor connected between CHF+ and CHF- is used for setting the low-frequency cutoff. CHF- External Filter Capacitor. A capacitor connected between CHF+ and CHF- is used for setting the low-frequency cutoff. FIL GND Electrical Ground IN+ Signal Input IN- No Connect PDC The voltage at this node programs the gain of the power detector. Connect a resistor between PDC and INV to adjust the LOP threshold. INV Used for programming the gain of the power detector. Connect a resistor between PDC and INV to adjust the LOP threshold. CPD- Filter Node for Power Detector. A capacitor connected between CPD+ and CPD- will provide additional filtering to the rectifier output within the power detector. CPD+ Filter Node for Power Detector. A capacitor connected between CPD+ and CPD- will provide additional filtering to the rectifier output within the power detector. OUT- Inverted Data-Signal Output OUT+ Noninverted Data-Signal Output LOP VCCD 4 On-Chip Resistor for Filtering Photodiode Supply Voltage (connected to VCCD on chip) TTL Output, Loss-of-Power, active high Power-Supply Voltage _______________________________________________________________________________________ 2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier 3.3V 5.0V CHF 100nF CHF 100nF 10nF CHF- CHF+ CHF- VCCD VCCS FIL IN+ OUT+ IN- LOP IN+ 100nF MAX3866 OUT+ OUT+ IN- GND PDC VCCD FIL 100nF OUT+ MAX3866 CHF+ VCCS LOP OUTINV CPD- CPD+ OUT- GND 100nF PDC OUTINV CPD- CPD+ OUT100nF RPD* 510Ω RPD* 510Ω 5.0V OPERATION 3.3V OPERATION * NOTE: IF LOP OPERATION IS NOT DESIRED, RPD = 0Ω Circuit Description Data Path The combined preamplifier and limiting postamplifier (Figure 1) accepts an input current from a photodiode attached to the input pad IN+. The transimpedance input amplifier stage converts the input current to an output voltage with a typical transimpedance of 1.4kΩ. The second stage of the data path is an active highpass filter. This filter converts the single-ended input signal to a differential signal, eliminating the DC component and adding approximately 16dB of gain. The output of the highpass filter drives the power detector and limiting amplifier circuitry. The limiting amplifier circuit is the third stage of the data signal path. It amplifies and limits the differential input signal. The output stage is a differential pair with internal 50Ω load resistors. The limited output voltage is typically 145mVp-p. Power Detector The power detect circuit consists of an adjustable-gain amplifier and combined rectifier with a lowpass filter. The adjustable-gain amplifier is controlled by an op amp. The gain is adjusted by means of an external resistor connected between the PDC and INV pins. The output voltage of the adjustable gain amplifier drives the combined rectifier and lowpass filter circuitry. The resulting DC voltage is fed to a Schmitt trigger, which generates a high-level output signal if the DC input signal is below the LOP assert level, thus causing an LOP condition on the LOP output. Design Procedure Power Supply The complete amplifier is supplied by a single supply voltage, VCCD. For operation at 3.3V, the supply voltage is applied at both the VCCD and VCCS pins (see Typical Operating Circuit). For operation at 5.0V, the voltage is only applied at VCCD. In this case, VCCS is on-chip controlled to approximately 3.2V. In the 5.0V configuration, an external 10nF grounded capacitor is required at the VCCS pin. External Filter Capacitor CHF The value of CHF affects the maximum speed at which the compensation loop adjusts the input offset current. CHF should be chosen between 10nF and 100nF. The loop should be as slow as possible to reduce patterndependent jitter. Maxim recommends a value of CHF = 100nF. _______________________________________________________________________________________ 5 MAX3866 Typical Operating Circuits MAX3866 2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier CHF- CHF+ ICC MAX3866 RF DATA SIGNAL PATH OUT+ IN OUTTIA VCCS LIM HPF OUT FIL VOLTAGE REGULATOR VCCD GND OP AMP VREF RMS DETECTOR ADJ LOP RECTIFIER PDC INV CPD+ CPD- RPD Figure 1. Functional Diagram of the Combined Preamplifier and Limiting Postamplifier Loss-of-Power Threshold If the LOP function is desired, Maxim recommends RPD = 510Ω. If the LOP function is not desired, RPD = 0Ω (shorted). See Figure 2 for LOP definitions. If desired, the LOP threshold can be adjusted (see Assert/ Deassert vs. RPD in the Typical Operating Characteristics. MAX. DEASSERT INPUT CURRENT External Filter Capacitor CPD The LF cutoff of the power detector can be reduced by adding external capacitance across the CPD pins. This capacitor is only needed when this circuit is operated at lower data rates and lower edge speeds. In this way, the remaining ripple of power detector output voltage is reduced. DEASSERT HYSTERESIS > 3dB ASSERT MIN. ASSERT Figure 2. Loss-of-Power Definitions with RPD = 510Ω 6 _______________________________________________________________________________________ 2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier VCCS VCCD 50Ω 50Ω OUT+ OUTESD STRUCTURE IN+ IN- ESD STRUCTURE ESD STRUCTURE GND GND Figure 3. OUT Pads Figure 4. IN Pads VCCD CHF+ CHF- VCCD ESD STRUCTURE 200Ω ESD STRUCTURES FIL GND GND Figure 5. FIL Pads Figure 6. CHF Pads _______________________________________________________________________________________ 7 MAX3866 Internal Input/Output Schematics 2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier MAX3866 Internal Input/Output Schematics (continued) VCCD PDC VCCD ESD STRUCTURE INV ESD STRUCTURE GND GND Figure 8. PDC Pad Figure 7. INV Pad VCCD CPD+ CPD- VCCD ESD STRUCTURE 10k LOP ESD STRUCTURES GND GND Figure 9. LOP Pad 8 Figure 10. CPD Pad _______________________________________________________________________________________ 2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier Converting Average Optical Power to Signal Amplitude Many of the MAX3866’s specifications relate to input signal amplitude. When working with fiber optic receivers, the input is usually expressed in terms of average optical power and extinction ratio. The relations given in Table 1 are helpful for converting optical power to input signal when designing with the MAX3866. In an optical receiver, the input current to the transimpedance amplifier can be found by multiplying the power relationships in Table 1 with the photodiode responsivity. Wire Bonding Table 1. Optical-Power Relations* PARAMETER SYMBOL RELATION Average Power PAVE Extinction Ratio re re = P1 / P0 Optical Power of a “1” P1 P1 = 2PAVE re Optical Power of a “0” P0 P0 = 2PAVE / (re +1) Signal Amplitude PIN PIN = P1 - P0 = 2PAVE (re - 1) PAVE = (P0 + P1) / 2 re + 1 (re + 1) *Assuming a 50% average input mark density. Make corrections to the die with gold wire only, using ball bonding techniques. Die pad size is 4mils (100µm) square and die thickness is 12mils (~300µm). Pad Configuration Layout Techniques The MAX3866’s performance can be greatly affected by circuit board layout and design. Use good high-frequency design techniques, including minimizing ground inductances and using fixed-impedance transmission lines on all data signals. MAX3866 Applications Information LOP GND OUT+ GND OUT- VCCD CPD+ VCCD CPD- VCCS VCCS GND 0.066" GND (1.68mm) CHF+ INV CHF- PDC FIL GND IN+ IN- GND N.C. 0.057" (1.45mm) TRANSISTOR COUNT: 851 _______________________________________________________________________________________ 9 MAX3866 2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier NOTES 10 ______________________________________________________________________________________ 2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier ______________________________________________________________________________________ MAX3866 NOTES 11 MAX3866 2.5Gbps, +3.3V Combined Transimpedance/Limiting Amplifier NOTES Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.