19-4767; Rev 2; 1/99 L MANUA ION KIT HEET T A U L EVA TA S WS DA FOLLO +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs Features The MAX3885 deserializer is ideal for converting 2.488Gbps serial data to 16-bit wide, 155Mbps parallel data in SDH/SONET applications. Operating from a single +3.3V supply, this device accepts PECL serial clock and data inputs, and delivers low-voltage differential-signal (LVDS) clock and data outputs for interfacing with high-speed digital circuitry. It also provides an LVDS synchronization input that enables data realignment and reframing. The MAX3885 is available in the extended temperature range (-40°C to +85°C) in a 64pin TQFP package. ♦ Single +3.3V Supply ♦ 2.488Gbps Serial to 155Mbps Parallel Conversion ♦ 660mW Operating Power ♦ LVDS Data Outputs and Synchronization Inputs ♦ Self-Biasing PECL Inputs Ease AC Coupling ♦ Synchronization Inputs for Data Realignment and Reframing Applications Ordering Information 2.488Gbps SDH/SONET Transmission Systems PART MAX3885ECB Add/Drop Multiplexers Digital Cross Connects TEMP. RANGE PIN-PACKAGE -40°C to +85°C 64 TQFP Pin Configuration appears at end of data sheet. Typical Operating Circuit VCC = +3.3V VCC = +3.3V VCC VCC = +3.3V 133Ω PD15+ 133Ω 100Ω* SD+ PD15- MAX3875 SD86.6Ω SERIAL DATA INPUTS DATA AND CLOCK RECOVERY 86.6Ω • • • MAX3885 OVERHEAD TERMINATION PD0+ 100Ω* VCC = +3.3V PD0133Ω 133Ω PCLK+ 100Ω* SCLK+ PCLK- SCLK86.6Ω SYNC+ 86.6Ω SYNCGND *REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω. ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. MAX3885 General Description MAX3885 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs ABSOLUTE MAXIMUM RATINGS Positive Supply Voltage (VCC)...............................-0.5V to +7.0V Input Voltage Level (all inputs)...................-0.5V to (VCC + 0.5V) Output Current LVDS outputs .............................................10mA Continuous Power Dissipation (TA = +85°C) TQFP (derate 24mW/°C above +85°C) .......................1000mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-60°C to +160°C Lead Temperature (soldering, 10sec) .............................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, differential loads = 100Ω ±1%, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) PARAMETER SYMBOL CONDITIONS UNITS MIN TYP MAX Supply Current ICC 200 280 mA PECL INPUTS (SD+/-, SCLK+/-) Input High Voltage VIH VCC - 1.16 VCC - 0.88 V Input Low Voltage VIL VCC - 1.81 VCC - 1.48 V Input High Current IIH VIN = VIH(MAX) -900 900 µA Input Low Current IIL VIN = VIL(MIN) -900 900 µA LVDS INPUTS AND OUTPUTS (SYNC+/-, PCLK+/-, PD_+/-) Input Voltage Range VI Differential Input Threshold VIDTH Threshold Hysteresis VHYST Differential Input Resistance RIN Output High Voltage VOH Output Low Voltage VOL V OD Differential Output Voltage Change in Magnitude of Differential Output Voltage for Complementary States Output Offset Voltage Differential input voltage = 100mV Common-mode voltage = 50mV 0 2.4 V -100 100 mV 78 85 100 Figure 1 Single-Ended Output Resistance RO Change in Magnitude of SingleEnded Output Resistance for Complementary Outputs ∆RO V V 250 VOS ∆VOS Ω 1.475 0.925 400 mV ±25 mV 1.275 V ±25 mV 95 140 Ω ±2.5 ±10 % ∆ V OD Change in Magnitude of Output Offset Voltage for Complementary States mV 115 1.125 40 AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, differential loads = 100Ω ±1%, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C.) (Note 1, Figure 4) PARAMETER Maximum Serial Clock Frequency Serial Data Setup Time Serial Data Hold Time Parallel Clock-to-Data Output Delay SYMBOL CONDITIONS MIN TYP UNITS 2.488 GHz tSU 100 ps tH 100 tCLK-Q 200 ps 450 Note 1: AC Characteristics guaranteed by design and characterization. 2 MAX fSCLK _______________________________________________________________________________________ 900 ps +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs 4.2 4.1 4.0 SERIAL DATA-HOLD TIME (ps) SERIAL DATA-SETUP TIME (ps) VCC = 3V 0 MAX3885-02 100 MAX3885-01 VCC = 3.6V 4.3 80 60 40 20 0 25 50 75 100 -50 TEMPERATURE (°C) -25 0 25 50 75 -25 VCC = 3V 150 100 25 50 TEMPERATURE (°C) 75 100 PCLK TO DATA OUTPUT PROPAGATION DELAY (ps) MAX3885-04 VCC = 3.6V 200 0 25 50 75 100 TEMPERATURE (°C) PARALLEL CLOCK TO DATA OUTPUT PROPAGATION DELAY vs. TEMPERATURE 250 0 -80 TEMPERATURE (°C) 300 -25 -60 -50 100 SUPPLY CURRENT vs. TEMPERATURE -50 -40 700 MAX3885-05 -25 -20 -100 0 -50 SUPPLY CURRENT (mA) MAX SERIAL CLOCK FREQUENCY (GHz) 4.4 SERIAL DATA-HOLD TIME vs. TEMPERATURE SERIAL DATA-SETUP TIME vs. TEMPERATURE MAX3885-03 MAXIMUM SERIAL CLOCK FREQUENCY vs. TEMPERATURE 600 500 400 300 200 -50 -25 0 25 50 75 100 TEMPERATURE (°C) _______________________________________________________________________________________ 3 MAX3885 Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.) +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs MAX3885 Pin Description PIN NAME FUNCTION 1, 2, 8, 16, 17, 24, 32, 33, 41, 48, 49, 57, 64 GND Ground 3, 5, 7, 9, 11, 13, 25, 34, 42, 47, 56 VCC +3.3V Supply Voltage 4 SD+ Serial Data Noninverting PECL Input. Data is clocked on the SCLK signal’s positive transition. 6 SD- Serial Data Inverting PECL Input. Data is clocked on the SCLK signal’s positive transition. 10 SCLK+ Serial Clock Noninverting PECL Input 12 SCLK- Serial Clock Inverting PECL Input 14 SYNC- Synchronizing Pulse Inverting LVDS Input. Pulse the SYNC signal high for at least four SCLK periods to shift the data alignment by dropping one bit. 15 SYNC+ Synchronizing Pulse Noninverting LVDS Input. Pulse the SYNC signal high for at least four SCLK periods to shift the data alignment by dropping one bit. 18 PCLK- Parallel Clock Inverting LVDS Output 19 PCLK+ Parallel Clock Noninverting LVDS Output 20, 22, 26, 28, 30, 35, 37, 39, 43, 45, 50, 52, 54, 58, 60, 62 PD0- to PD15- Parallel Data Inverting LVDS Outputs. Data is updated on the negative transition of the PCLK signal. 21, 23, 27, 29, 31, 36, 38, 40, 44, 46, 51, 53, 55, 59, 61, 63 PD0+ to PD15+ Parallel Data Noninverting LVDS Outputs. Data is updated on the negative transition of the PCLK signal. PD+ RL = 100Ω D V VOD PDVPD- VOH |VOD| SINGLE-ENDED OUTPUT VPD+ VOS VOL +VOD VPD+ - VPDDIFFERENTIAL OUTPUT 0V (DIFF.) 0V VOD, P - P = VPD+ - VPD-VOD Figure 1. Driver Output Levels 4 _______________________________________________________________________________________ +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs The MAX3885 deserializer uses a 16-bit shift register, 16-bit parallel output register, 4-bit counter, PECL input buffers, and low-voltage differential-signal (LVDS) input/output buffers to convert 2.488Gbps serial data to 16-bit wide, 155Mbps parallel data (Figure 2). The input PD15+ SD+ PECL SD- 16-BIT SHIFT REGISTER SCLK+ 16-BIT PARALLEL OUTPUT REGISTER LVDS PD15- PECL SCLK- PD1+ LVDS MAX3885 PD1PD0+ LVDS SYNC+ 100Ω LVDS SYNC- PD0PCLK+ 4-BIT COUNTER LVDS PCLK- Figure 2. Functional Diagram D15 D14 shift register continuously clocks incoming data on the positive transition of the serial clock (SCLK) input signal. The 4-bit counter generates a parallel-output clock (PCLK) by dividing the serial-clock frequency by 16. The PCLK signal clocks the parallel-output register. During normal operation, the counter divides the SCLK frequency by 16, causing the output register to latch every 16 bits of incoming serial data. The synchronization inputs (SYNC+, SYNC-) realign and reframe data. When the SYNC signal is pulsed high for at least four SCLK cycles, the parallel output data is delayed by one SCLK cycle. This realignment is guaranteed to occur within two complete PCLK cycles of the SYNC signal’s positive transition. As a result, the first incoming bit of data during that PCLK cycle is dropped, shifting the alignment between PCLK and data by one bit. See Figure 3 for the timing diagram and Figure 4 for the timing parameters diagram. Low-Voltage Differential-Signal (LVDS) Inputs and Outputs The MAX3885 features LVDS inputs and outputs for interfacing with high-speed digital circuitry. The LVDS standard is based on the IEEE 1596.3 LVDS specification. This technology uses 500mVp-p to 800mVp-p differential low-voltage swings to achieve fast transition times, minimize power dissipation, and improve noise immunity. The parallel clock and data LVDS outputs (PCLK+, PCLK-, PD_+, PD_-) require 100Ω differential D13 SCLK SD SYNC PCLK (LSB) PD0 D0 D16 D32 D48 D65 PD1 D1 D17 D33 D49 D66 • • • (MSB) PD15 TRANSMITTED FIRST ONE BIT HAS SLIPPED IN THIS TIME SLICE D15 D31 D47 D64 D80 Figure 3. Timing Diagram _______________________________________________________________________________________ 5 MAX3885 Detailed Description MAX3885 +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs tSCLK = 1 / fSCLK SCLK tSU tH SD PCLK tCLK-Q PD0–PD15 NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-). Figure 4. Timing Parameters DC termination between the inverting and noninverting outputs for proper operation. Do not terminate these outputs to ground. The synchronization LVDS inputs (SYNC+, SYNC-) are internally terminated with 100Ω differential input resistance and, therefore, do not require external termination. THEVENIN-EQUIVALENT TERMINATION +3.3V 133Ω 133Ω MAX3885 ZO = 50Ω PECL Inputs Because of the self-biasing resistor networks, the serial data and clock PECL inputs (SD+, SD-, SCLK+, SCLK-) require 53Ω termination to VCC - 2V when interfacing with a PECL source (see Alternative PECL Input Termination). This results in an equivalent input resistance of 50Ω. PECL INPUTS ZO = 50Ω 86.6Ω 86.6Ω Applications Information Alternative PECL Input Termination Figure 5 shows alternative PECL input-termination methods. Use Thevenin-equivalent termination when a VCC - 2V termination voltage is not available. When interfacing with an ECL-output device, the MAX3885’s internal self-biasing allows easy ECL AC-coupling termination. ECL AC-COUPLING TERMINATION ZO = 50Ω 53Ω Layout Techniques For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Also, use controlled impedance transmission lines to interface with the MAX3885 high-speed inputs and outputs. MAX3885 ZO = 50Ω PECL INPUTS -2V 53Ω -2V Figure 5. Alternative PECL Input Termination 6 _______________________________________________________________________________________ +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VCC GND PD5- PD6- PD5+ PD6+ PD7- PD7+ 48 VCC GND PD8- PD8+ PD9- VCC PD9+ GND TOP VIEW GND 49 32 GND PD10- 50 31 PD4+ PD10+ 51 30 PD4- PD11- 52 29 PD3+ PD11+ 53 28 PD3- PD12- 54 27 PD2+ PD12+ 55 26 PD225 VCC VCC 56 MAX3885 GND 57 24 GND PD13- 58 23 PD1+ PD13+ 59 22 PD1- PD14- 60 21 PD0+ PD14+ 61 20 PD0- PD15- 62 19 PCLK+ PD15+ 63 18 PCLK- GND 64 8 9 GND VCC SD+ VCC SD- VCC GND VCC 10 11 12 13 14 15 16 GND 7 SYNC- 6 SYNC+ 5 VCC 4 SCLK- 3 VCC 2 SCLK+ 1 GND 17 GND TQFP ___________________Chip Information TRANSISTOR COUNT: 2820 _______________________________________________________________________________________ 7 MAX3885 Pin Configuration +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs TQFPPO.EPS MAX3885 Package Information 8 _______________________________________________________________________________________