MAXIM MAX5742EUB

19-2122; Rev 2; 7/03
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
Features
♦ Ultra-Low Power Consumption
229µA at VDD = +3.6V
271µA at VDD = +5.5V
The 20MHz, 3-wire SPI™, QSPI™, MICROWIRE™ and
DSP-compatible serial interface saves board space
and reduces the complexity of opto- and transformerisolated applications. The MAX5742 on-chip power-on
reset (POR) circuit resets the DAC outputs to zero and
loads the output with a 100kΩ resistor to ground. This
provides additional safety for applications that drive
valves or other transducers that need to be off on
power-up. The MAX5742’s software-controlled powerdown reduces supply current to less than 0.3µA and
provides software-selectable output loads (1kΩ, 100kΩ,
or high impedance) while in power-down. The MAX5742
is specified over the -40°C to +125°C automotive temperature range.
♦ Three Software-Selectable Power-Down
Impedances (100kΩ, 1kΩ, Hi-Z)
♦ Wide +2.7V to +5.5V Single-Supply Range
♦ 10-Pin µMAX Package
♦ 0.3µA Power-Down Current
♦ Guaranteed 12-Bit Monotonicity (±1LSB DNL)
♦ Safe Power-Up Reset to Zero Volts at DAC Output
♦ Fast 20MHz 3-Wire SPI, QSPI, and MICROWIRECompatible Serial Interface
♦ Rail-to-Rail Output Buffer Amplifiers
♦ Schmitt-Triggered Logic Inputs for Direct
Interfacing to Optocouplers
♦ Wide -40°C to +125°C Operating Temperature
Range
Ordering Information
Applications
Automatic Tuning
PART
TEMP RANGE
PIN-PACKAGE
Gain and Offset Adjustment
MAX5742EUB
-40°C to +85°C
10 µMAX
Power Amplifier Control
MAX5742AUB
-40°C to +125°C
10 µMAX
Process Control I/O Boards
Battery-Powered Instruments
VCO Control
Pin Configuration
TOP VIEW
Functional Diagram appears at end of data sheet.
Rail-to-Rail is a registered trademark of Nippon Motorola, Inc.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor, Corp.
CS 1
SCLK
2
VDD
3
GND
DIN
10 OUTD
9
OUTC
8
OUTB
4
7
OUTA
5
6
REF
MAX5742
µMAX
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX5742
General Description
The MAX5742 quad, 12-bit, low-power, buffered voltage-output, digital-to-analog converter (DAC) is packaged in a space-saving 10-pin µMAX package (5mm ✕
3mm). The wide supply voltage range of +2.7V to
+5.5V and 229µA supply current accommodates lowpower and low-voltage applications. DAC outputs
employ on-chip precision output amplifiers that swing
Rail-to-Rail®. The MAX5742’s reference input accepts a
voltage range from 0 to VDD. In power-down the reference input is high impedance, further reducing the system’s total power consumption.
MAX5742
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V
OUT_, SCLK, DIN, CS, REF to GND...............-0.3 to (VDD+0.3V)
Maximum Continuous Current Into Any Pin......................±50mA
Continuous Power Dissipation (TA = +70°C)
10-Pin µMAX (derate 6.9 mW/°C above +70°C) ..........555mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature.......................................-65°C to +150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are
VDD = +5V, TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
±2
±16
LSB
±1
LSB
0.4
1.5
% of FS
STATIC ACCURACY (Note 1)
Resolution
N
12
Integral Nonlinearity Error
INL
(Note 2)
Differential Nonlinearity Error
DNL
Guaranteed monotonic (Note 2)
Zero-Code Error
OE
Code = 000
GE
Code = FFF hex
Zero-Code Error Tempco
Gain Error
2.3
PSRR
ppm/°C
±3
Gain-Error Tempco
Power-Supply Rejection Ratio
Bits
Code = FFF hex, ∆VDD = ±10%
% of FS
0.26
ppm/°C
58.8
dB
REFERENCE INPUT
Reference Input Voltage Range
VREF
Reference Input Impedance
RREF
Power-Down Reference Current
0
In operation
32
VDD
45
In power-down mode
2
In power-down mode (Note 3)
1
63
V
kΩ
MΩ
10
µA
DAC OUTPUT
Output Voltage Range
No load (Note 4)
DC Output Impedance
Code = 800 hex
0.8
Short-Circuit Current
Wake-Up Time
Output Leakage Current
2
0
VDD
VDD = +3V
15
VDD = +5V
48
VDD = +3V
8
VDD = +5V
8
Power-down mode = output high
impedance
±18
_______________________________________________________________________________________
V
Ω
mA
µs
nA
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
(VDD = +2.7V to +5.5V, GND = 0, VREF = VDD, RL = 5kΩ, CL = 200pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are
VDD = +5V, TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SCLK, DIN, CS)
Input High Voltage
VIH
VDD = +3V, +5V
Input Low Voltage
VIL
VDD = +3V, +5V
Input Leakage Current
IIN
Digital inputs = 0 or VDD
Input Capacitance
CIN
0.7 x
VDD
V
0.3 x
VDD
±0.1
±1
5
V
µA
pF
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
SR
Voltage Output Settling Time
0.5
400 hex to C00 hex (Note 5)
4
V/µs
10
µs
Digital Feedthrough
Any digital inputs from 0 to VDD
0.1
nV-s
Digital-Analog Glitch Impulse
Major carry transition (code 7FF hex to code
800 hex)
12
nV-s
2.4
nV-s
DAC-to-DAC Crosstalk
POWER REQUIREMENTS
Supply-Voltage Range
VDD
Supply Current with No Load
IDD
Power-Down Supply Current
IDDPD
2.7
5.5
V
All digital inputs at 0 or VDD = 3.6V
229
395
All digital inputs at 0 or VDD = 5.5V
271
420
All digital inputs at 0 or VDD = 5.5V
0.29
1
µA
TYP
MAX
UNITS
20
MHz
µA
TIMING CHARACTERISTICS
(VDD = 2.7V to 5.5V, GND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
SCLK Clock Frequency
f SCLK
0
SCLK Pulse Width High
tCH
25
ns
SCLK Pulse Width Low
tCL
25
ns
CS Fall to SCLK Rise Setup Time
tCSS
10
ns
SCLK Fall to CS Rise Setup Time
tCSH
10
ns
tDS
15
ns
tDH
0
ns
tCSW
80
ns
DIN to SCLK Fall Setup Time
DIN to SCLK Fall Hold Time
CS Pulse Width High
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
DC specifications are tested without output loads.
Linearity guaranteed from code 115 to code 3981.
Limited with test conditions.
Offset and gain error limit the FSR.
Guaranteed by design.
_______________________________________________________________________________________
3
MAX5742
ELECTRICAL CHARACTERISTICS (continued)
__________________________________________Typical Operating Characteristics
(VREF = VDD, TA = +25°C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY vs.
CODE, TA = +25°C
0.6
0.4
VDD = +5V
0
-4
0.2
0
-0.2
-0.4
-8
-0.6
VDD = +3V
-12
-1.0
INTEGRAL NONLINEARITY vs.
CODE, TA = -40°C
0.8
0.6
LSB
INL (LSB)
0.2
0
0
-0.2
-4
-0.4
VDD = +3V
-0.6
-12
-16
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
-4
VDD = +3V
-12
-0.2
VDD = +5V
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
512 1024 1536 2048 2560 3072 3584 4096
CODE
TOTAL UNADJUSTED ERROR vs.
CODE, TA = +125°C
0.4
0.2
0
-0.2
-0.4
-0.6
1.0
0.8
0.6
0.4
VDD = +3V
0.2
0
-0.2
VDD = +5V
-0.4
-0.8
-16
4
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
MAX5742 toc08
0.6
DNL (LSB)
0
0
VDD = +3V
0.2
-0.6
0.8
VDD = +5V
-8
0.4
-0.4
1.0
8
4
0.6
DIFFERENTIAL NONLINEARITY vs.
CODE, TA = +125°C
MAX5742 toc07
12
0.8
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
1.0
-0.8
INTEGRAL NONLINEARITY vs.
CODE, TA = +125°C
16
VDD = +5V
TOTAL UNADJUSTED ERROR vs.
CODE, TA = -40°C
0.4
VDD = +5V
-8
-0.2
0
TOTAL UNADJUSTED ERROR (%)
1.0
8
4
0.0
512 1024 1536 2048 2560 3072 3584 4096
CODE
MAX5742 toc05
12
VDD = +3V
0.2
DIFFERENTIAL NONLINEARITY vs.
CODE, TA = -40°C
MAX5742 toc04
16
0.4
-0.6
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
TOTAL UNADJUSTED ERROR (%)
0
0.6
-0.4
-0.8
-16
0.8
MAX5742 toc06
4
DNL (LSB)
INL (LSB)
8
1.0
MAX5742 toc03
0.8
MAX5742 toc09
12
MAX5742 toc02
1.0
MAX5742 toc01
16
TOTAL UNADJUSTED ERROR vs.
CODE, TA = +25°C
TOTAL UNADJUSTED ERROR (%)
INTEGRAL NONLINEARITY vs.
CODE, TA = +25°C
INL (LSB)
MAX5742
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
-0.6
-1.0
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
_______________________________________________________________________________________
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
SOURCE-AND-SINK CURRENT CAPABILITY
(VDD = +3V)
2.5
MAXIMUM INL
2.0
0
-4
CODE = C00
HEX, SOURCING
CURRENT
FROM OUT_
1.5
MINIMUM INL
1.5
0
20
40
60
80
TEMPERATURE (°C)
0
100 120
2
4
6
8
10
12
14
0
16
0
CODE = 0 x 000
240
160
80
0
250
200
150
100
4.2
4.7
5.2
8
10
12
14
16
800
700
600
VDD = +5V
500
400
300
VDD = +3V
200
50
100
0
3.7
6
900
SUPPLY CURRENT (µA)
320
4
SUPPLY CURRENT vs. CS INPUT VOLTAGE
300
MAX5742 toc14
400
0
2.0
2.5
SUPPLY VOLTAGE (V)
3.0
3.5
4.0
4.5
5.0
5.5
0
SUPPLY VOLTAGE (V)
1
2
3
4
5
CS INPUT VOLTAGE (V)
SUPPLY CURRENT vs. TEMPERATURE
MAX5742 toc16
290
280
SUPPLY CURRENT (µA)
3.2
2
ISOURCE/SINK (mA)
POWER-DOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
POWER-DOWN SUPPLY CURRENT (nA)
CODE = 0 x FFF
MAX5742 toc13
480
2.7
CODE = 000 HEX,
SINKING CURRENT INTO OUT_
ISOURCE/SINK (mA)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
CODE = 0 x 800
CODE = 400 HEX,
SINKING CURRENT
INTO OUT_
0.5
0
-40 -20
CODE = C00 HEX,
SOURCING CURRENT
FROM OUT_
2.5
2.0
CODE = 000 HEX,
SINKING CURRENT INTO OUT_
-12
-16
3.0
1.0
0.5
SUPPLY CURRENT (µA)
4.0
3.5
CODE = 400 HEX,
SINKING CURRENT
INTO OUT_
1.0
MINIMUM DNL
-8
CODE = FFF HEX, SOURCING
CURRENT FROM OUT_
4.5
MAX5742 toc15
MAXIMUM DNL
4
VOUT (V)
INL AND DNL (LSB)
8
5.0
VOUT (V)
12
CODE = FFF
HEX, SOURCING
CURRENT
FROM OUT_
MAX5742 toc12
3.0
MAX5742 toc10
16
SOURCE-AND-SINK CURRENT CAPABILITY
(VDD = +5V)
MAX5742 toc11
WORST-CASE INL AND DNL
vs. TEMPERATURE
270
VDD = 5.5V
260
250
240
230
VDD = 3.6V
220
210
200
-40 -20
0
20
40
60
80
100 120
TEMPERATURE (°C)
_______________________________________________________________________________________
5
MAX5742
Typical Operating Characteristics (continued)
(VREF = VDD, TA = +25°C, unless otherwise noted.)
MAX5742
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
Typical Operating Characteristics (continued)
(VREF = VDD, TA = +25°C, unless otherwise noted.)
FULL-SCALE SETTLING TIME
(VDD = +5V)
FULL-SCALE SETTLING TIME
(VDD = +5V)
MAX5742 toc17
MAX5742 toc18
VSCLK,
5V/div
VSCLK,
5V/div
VOUT_
1V/div
VOUT_
1V/div
CODE 000 TO FFF HEX
RL = 5kΩ
CL = 200pF
CODE FFF TO 000 HEX
RL = 5kΩ
CL = 200pF
1µs/div
1µs/div
HALF-SCALE SETTLING TIME
(VDD = +3V)
HALF-SCALE SETTLING TIME
(VDD = +3V)
MAX5742 toc20
MAX5742 toc19
VSCLK,
5V/div
VSCLK,
5V/div
VOUT_
1V/div
VOUT_
1V/div
CODE C00 TO 400 HEX
RL = 5kΩ
CL = 200pF
CODE 400 TO C00 HEX
RL = 5kΩ
CL = 200pF
1µs/div
1µs/div
DIGITAL-TO-ANALOG GLITCH IMPULSE
(VDD = +5V)
EXITING POWER-DOWN
(VDD = +5V)
MAX5742 toc22
MAX5742 toc21
CODE 800 HEX
VSCLK,
5V/div
SCLK,
fSCLK = 500kHz
2V/div
VOUT_
1V/div
VOUT_
AC-COUPLED,
20mV/div
CODE 7FF HEX
to 800 HEX
5µs/div
6
1µs/div
_______________________________________________________________________________________
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
DIGITAL-TO-ANALOG GLITCH IMPULSE
(VDD = +5V)
DIGITAL-TO-ANALOG GLITCH IMPULSE
(VDD = +3V)
MAX5742 toc24
MAX5742 toc23
CODE 7FF HEX
to 800 HEX
SCLK,
fSCLK = 500kHz,
2V/div
SCLK,
fSCLK = 500kHz
2V/div
VOUT_
AC-COUPLED,
20mV/div
VOUT_
AC-COUPLED,
20mV/div
CODE 800 HEX
to 7FF HEX
1µs/div
1µs/div
DIGITAL-TO-ANALOG GLITCH IMPULSE
(VDD = +3V)
POWER-ON RESET, FAST RISE TIME
(VDD = +5V)
MAX5742 toc26
MAX5742 toc25
SCLK,
fSCLK = 500kHz,
2V/div
VDD
2V/div
VOUT_
AC-COUPLED,
20mV/div
VOUT_
AC-COUPLED,
10mV/div
VDD RISE
TIME = 20µs
CODE 800F HEX
to 7FF HEX
20µs/div
1µs/div
POWER-ON RESET, FAST RISE TIME
(VDD = +3V)
POWER-ON RESET, SLOW RISE TIME
(VDD = +5V)
MAX5742 toc28
MAX5742 toc27
VDD
2V/div
VDD
2V/div
VDD RISE
TIME = 76µs
VDD RISE
TIME = 20µs
VOUT_
AC-COUPLED,
10mV/div
VOUT_
AC-COUPLED,
2mV/div
40µs/div
20µs/div
_______________________________________________________________________________________
7
MAX5742
____________________________Typical Operating Characteristics (continued)
(VREF = VDD, TA = +25°C, unless otherwise noted.)
MAX5742
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
Typical Operating Characteristics (continued)
(VREF = VDD, TA = +25°C, unless otherwise noted.)
CLOCK FEEDTHROUGH
(VDD = +5V)
POWER-ON RESET, SLOW RISE-TIME
(VDD = +3V)
MAX5742 toc30
MAX5742 toc29
VDD
2V/div
SCLK,
2V/div
VOUT_
AC-COUPLED,
2mV/div
VOUT_
AC-COUPLED,
1mV/div
VDD RISE
TIME = 72µs
CODE = 800 HEX,
2µs/div
fSCLK = 50kHz
40µs/div
2µs/div
CLOCK FEEDTHROUGH
(VDD = +3V)
LINE TRANSIENT RESPONSE
(VDD = +5V)
MAX5742 toc32
MAX5742 toc31
CODE = 800 HEX,
2µs/div
fSCLK = 50kHz
SCLK,
2V/div
VDD,
AC-COUPLED,
100mV/div
VOUT_
AC-COUPLED,
1mV/div
VOUT_
AC-COUPLED,
10mV/div
20µs/div
2µs/div
LINE TRANSIENT RESPONSE
(VDD = +3V)
CROSSTALK (VDD = +5V)
MAX5742 toc33
MAX5742 toc34
VDD,
AC-COUPLED,
100mV/div
CODE FFF HEX
to 00B HEX
VOUT_
AC-COUPLED,
10mV/div
20µs/div
8
VOUTA,
2V/div
VOUTB,
AC-COUPLED,
2mV/div
4µs/div
_______________________________________________________________________________________
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
PIN
NAME
FUNCTION
1
CS
Chip-Select Input
2
SCLK
Serial-Clock Input
3
VDD
Power-Supply Input
4
GND
Ground
5
DIN
Serial Data Input
6
REF
External Reference Voltage Input
7–10
OUTA –OUTD
DAC Voltage Outputs. Power-on reset sets DAC registers to zero, and internally connects
OUT to GND with 100kΩ resistor.
Detailed Description
The MAX5742 contains four 12-bit, voltage-output, lowpower digital-to-analog converters (DACs). Each DAC
employs a resistor string architecture that converts a
12-bit digital input word to an equivalent analog output
voltage proportional to the applied reference voltage.
The MAX5742 shares one reference input (REF)
between all four DACs. The MAX5742 includes rail-torail output buffer amplifiers for each DAC, and input
logic for simple microprocessor (µP), and CMOS interfaces. The power-supply range is from +2.7V to +5.5V
(Functional Diagram). The MAX5742’s reference input
accepts a voltage range from 0 to VDD. In power-down
mode the reference input is high impedance. The
MAX5742 is compatible with the 3-wire SPI, QSPI,
MICROWIRE and DSP serial interface with Schmitt-triggered logic inputs.
Reference Input and DAC Output Range
The reference input accepts positive DC and AC signals. The voltage at REF sets the full-scale output voltage of the four DACs. The reference input voltage
range is 0 to VDD. The impedance at REF is 45kΩ. The
voltage at REF can vary from GND to VDD. The output
voltages (VOUT_) are represented by a digitally programmable voltage source as:
VOUT_ = (VREF ✕ D) / 212
where D is the decimal equivalent of binary DAC input
code ranging from 0 to 4095. VREF is the voltage at
REF.
Output Buffer Amplifiers
All DACs are internally buffered at the output. The
buffer amplifiers have both rail-to-rail common mode
and (GND to VREF) output voltage range. The buffers
are unity-gain stable with CL = 200pF and RL = 5kΩ.
Buffer amplifiers are disabled during power-up and
individual DAC outputs are shorted to GND through a
100kΩ resistor. Buffer amplifiers can individually or altogether be powered-down by programming the input
register control bits. During power down, contents of
the input and DAC registers remain the same. On
wake-up, all DAC outputs are restored to their prepower-down voltage values.
Power-Down Mode
In power-down mode, the DAC outputs are programmed to one of three output states, 1kΩ, 100kΩ, or
floating (Table 1). The REF input is high impedance
(2MΩ typ) to conserve current drain from the system
reference; therefore, the system reference does not
have to be powered-down. The DAC outputs return to
the values contained in the registers when brought out
of power-down. The recovery time, from total powerdown to power-up, is 8µs. This extra time is needed to
allow the internal bias to wake-up. Power-down mode
reduces current consumption to 0.3µA.
3-Wire Serial Interface
The MAX5742 digital interface is a standard 3-wire connection compatible with SPI/QSPI/MICROWIRE/DSP
interfaces. The chip-select input (CS) frames the serial
data loading at DIN. Immediately following CS high-tolow transition, the data is shifted synchronously and
latched into the input register on the falling edge of the
serial clock input (SCLK). After 16 bits have been
loaded into the serial input register, it transfers its contents to the DAC latch. CS may then either be held low
or brought high. CS must be brought high for a minimum of 80ns before the next write sequence, since a
_______________________________________________________________________________________
9
MAX5742
Pin Description
MAX5742
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
Table 1. Power-Down Mode Control
EXTENDED
CONTROL
DATA BITS
DESCRIPTION
FUNCTION
C3
C2
C1
C0
D11–D5
D4
D3
D2
D1
D0
1
1
1
1
X
0
0
0
0
0
DAC A
DAC O/P, wakeup
1
1
1
1
X
0
0
0
0
1
DAC A
Floating output
1
1
1
1
X
0
0
0
1
0
DAC A
Output is terminated with 1kΩ
1
1
1
1
X
0
0
0
1
1
DAC A
Output is terminated with 100kΩ
1
1
1
1
X
0
0
1
0
0
DAC B
DAC O/P, wakeup
1
1
1
1
X
0
0
1
0
1
DAC B
Floating output
1
1
1
1
X
0
0
1
1
0
DAC B
Output is terminated with 1kΩ
1
1
1
1
X
0
0
1
1
1
DAC B
Output is terminated with 100kΩ
1
1
1
1
X
0
1
0
0
0
DAC C
DAC O/P, wakeup
1
1
1
1
X
0
1
0
0
1
DAC C
Floating output
1
1
1
1
X
0
1
0
1
0
DAC C
Output is terminated with 1kΩ
1
1
1
1
X
0
1
0
1
1
DAC C
Output is terminated with 100kΩ
1
1
1
1
X
0
1
1
0
0
DAC D
DAC O/P, wakeup
1
1
1
1
X
0
1
1
0
1
DAC D
Floating output
1
1
1
1
X
0
1
1
1
0
DAC D
Output is terminated with 1kΩ
1
1
1
1
X
0
1
1
1
1
DAC D
Output is terminated with 100kΩ
1
1
1
1
X
1
0
0
0
0
DAC A-D
DAC O/P, wakeup
1
1
1
1
X
1
0
0
0
1
DAC A-D
Floating output
1
1
1
1
X
1
0
0
1
0
DAC A-D
Output is terminated with 1kΩ
1
1
1
1
X
1
0
0
1
1
DAC A-D
Output is terminated with 100kΩ
X = Don’t care
write sequence is initiated on a falling edge of CS. Not
keeping CS low during the first 15 SCLK cycles discards input data. The serial clock (SCLK) can idle
either high or low between transitions.
The MAX5742 has two internal registers per DAC, the
input register and the DAC register. The input register
holds the data that is waiting to be shifted to the DAC
register. All input registers can be loaded without
updating the output. This function is useful when all outputs need to be updated at the same time. The input
register can be made transparent. When the input register is transparent, the data written into DIN loads
directly to the DAC register and the output is updated.
The DAC output is not updated until data is written to
the DAC register. See Table 2 for a list of serial-interface programming commands.
10
Power-On Reset (POR)
The MAX5742 has an internal POR circuit. At power-up all
DACs are powered-down and OUT_ is terminated to
GND through 100kΩ resistors. Contents of input and DAC
registers are cleared to all zero. An 8µs recovery time
after issuing a wake-up command is needed before writing to the DAC registers. Power-down mode control commands can be applied immediately with no recovery time.
C3-C0 are control bits. The data bits D11 to D0 are in
straight binary format. All zeros correspond to zero
scale and all ones correspond to full scale.
Digital Inputs
The digital inputs are compatible with CMOS logic. In
order to save power and reduce input to output coupling,
SCLK and DIN input buffers are powered down immediately after completion of shifting 16 bits into the input shift
register. A high to low transition at CS powers up SCLK
and DIN input buffers.
______________________________________________________________________________________
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
C3
D0 (LSB)
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 1. 16-Bit Input Word
tCL
SCLK
X
1
2
tOS
DIN
X
C3
tCSPWH
tCH
3
4
5
6
16
X
tOH
C2
C1
C0
D11
D10
D1
D0
X
tCSH
tCSS
CS
Figure 2. Timing Diagram
Applications Information
Unipolar Output
The typical application circuit (Figure 3) shows the
MAX5742 configured for a unipolar output, where the
output voltages and the reference inputs have the
same polarity. Table 3 lists the unipolar output codes.
Bipolar Output
The MAX5742 can be configured for bipolar operation
using a dual supply op amp (Figure 4). The transfer
function for bipolar operation is:
where NB is the decimal value of the DACs binary input
code. Table 4 shows digital codes (offset binary) and
corresponding output voltages for the circuit in Figure 4.
Power Supply and Layout Considerations
Careful PC board layout is important for optimal system
performance. To reduce noise injection and digital feedthrough, keep analog and digital signals separate.
Ensure that that the return path from GND to the supply
ground is short and low impedance. Use a ground
plane. Bypass VDD to GND with a 0.1µF capacitor as
close as possible to VDD.
 2NB  
VOUT = VREF 
 − 1
 4096  
______________________________________________________________________________________
11
MAX5742
CONTENTS OF SHIFT REGISTER
D15 (MSB)
MAX5742
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
Table 2. Serial-Interface Programming Commands
CONTROL
DATA BITS
DAC
FUNCTION
C3
C2
C1
C0
D11–D0
0
0
0
0
X
A
Input register transparent, data shifted directly to DAC register, OUTA updated
0
0
0
1
X
B
Input register transparent, data shifted directly to DAC register, OUTB updated
0
0
1
0
X
C
Input register transparent, data shifted directly to DAC register, OUTC updated
0
0
1
1
X
D
Input register transparent, data shifted directly to DAC register, OUTD updated
0
1
0
0
X
A
Data shifted to input register, OUTA unchanged
0
1
0
1
X
B
Data shifted to input register, OUTB unchanged
0
1
1
0
X
C
Data shifted to input register, OUTC unchanged
0
1
1
1
X
D
Data shifted to input register, OUTD unchanged
1
0
0
0
X
A
Shift data from input register to DAC register, OUTA updated
1
0
0
1
X
B
Shift data from input register to DAC register, OUTB updated
1
0
1
0
X
C
Shift data from input register to DAC register, OUTC updated
1
0
1
1
X
D
Shift data from input register to DAC register, OUTD updated
1
1
0
0
X
A–D
Input registers transparent, data shifted directly to DAC registers, OUTA–OUTD
updated
1
1
0
1
X
A–D
Data shifted to input registers, OUTA–OUTD unchanged
1
1
1
0
X
A–D
Shift data from input registers to DAC registers, OUTA–OUTD updated
X = Don’t care
R1
+2.7V TO +5.5V
R2
V+
+2.7V TO +5.5V
REF
REF
VDD
VDD
OUT_
DAC_
DAC_
OUT_
MAX6050
V-
GND
GND
MAX5742
Figure 3. Typical Operating Circuit, Unipolar Output
12
VOUT
OUT
IN
MAX5742
R1 = R2
Figure 4. Bipolar Output Circuit
______________________________________________________________________________________
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
Table 4. Bipolar Code Table
DAC CONTENTS
ANALOG OUTPUT
DAC CONTENTS
1111 1111 1111
 4095 
VREF 

 4096 
1111 1111 1111
 2047 
+ VREF 

 2048 
1000 0000 0001
 2049 
VREF 

 4096 
1000 0000 0001
 1 
+ VREF 

 2048 
VREF
2
1000 0000 0000
 2047 
VREF 

 4096 
0111 1111 1111
MAX5742
Table 3. Unipolar Code Table
0000 0000 0001
 1 
VREF 

 4096 
0000 0000 0000
0
1000 0000 0000
ANALOG OUTPUT
0
 1 

 2048 
0111 1111 1111
− VREF 
0000 0000 0001
− VREF 
0000 0000 0000
 2047 

 2048 
− VREF
Chip Information
TRANSISTOR COUNT: 14,458
PROCESS: BiCMOS
______________________________________________________________________________________
13
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
MAX5742
Functional Diagram
VDD
INPUT
REGISTER A
REF
DAC
REGISTER A
12-BIT DAC A
OUTPUT
BUFFER
OUTA
RESISTOR
NETWORK
INPUT
REGISTER B
DAC
REGISTER B
12-BIT DAC B
OUTPUT
BUFFER
OUTB
RESISTOR
NETWORK
INPUT
REGISTER C
DAC
REGISTER C
12-BIT DAC C
OUTPUT
BUFFER
OUTC
RESISTOR
NETWORK
INPUT
REGISTER D
DAC
REGISTER D
12-BIT DAC D
OUTPUT
BUFFER
OUTD
RESISTOR
NETWORK
INPUT CONTROL
LOGIC AND SHIFT
REGISTER
POWER-DOWN
CONTROL LOGIC
MAX5742
CS
14
SCLK
DIN
GND
______________________________________________________________________________________
12-Bit, Low-Power, Quad, Voltage-Output
DAC with Serial Interface
10LUMAX.EPS
e
4X S
10
10
INCHES
H
ÿ 0.50±0.1
0.6±0.1
1
1
0.6±0.1
BOTTOM VIEW
TOP VIEW
D2
MILLIMETERS
MAX
DIM MIN
A
0.043
A1
0.002
0.006
A2
0.030
0.037
D1
0.116
0.120
D2
0.114
0.118
E1
0.116
0.120
0.118
E2
0.114
0.199
H
0.187
L
0.0157 0.0275
L1
0.037 REF
b
0.007
0.0106
e
0.0197 BSC
c
0.0035 0.0078
0.0196 REF
S
α
0∞
6∞
MAX
MIN
1.10
0.15
0.05
0.75
0.95
3.05
2.95
3.00
2.89
3.05
2.95
2.89
3.00
4.75
5.05
0.40
0.70
0.940 REF
0.177
0.270
0.500 BSC
0.090
0.200
0.498 REF
0∞
6∞
E2
GAGE PLANE
A2
c
A
b
A1
α
E1
L
D1
L1
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL
DOCUMENT CONTROL NO.
21-0061
REV.
I
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX5742
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)