SN74ALVC7813 64 × 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS594A – OCTOBER 1997 – REVISED APRIL 1998 D D D D D D D D D D D D D Member of the Texas Instruments Widebus Family Low-Power Advanced CMOS Technology Operates From 3-V to 3.6-V VCC Free-Running Read and Write Clocks Can Be Asynchronous or Coincident Read and Write Operations Synchronized to Independent System Clocks Half-Full Flag and Programmable Almost-Full/Almost-Empty Flag Bidirectional Configuration and Width Expansion Without Additional Logic Input-Ready Flag Synchronized to Write Clock Output-Ready Flag Synchronized to Read Clock Fast Access Times of 13 ns With a 50-pF Load and All Data Outputs Switching Simultaneously Data Rates up to 50 MHz Pin-to-Pin Compatible With SN74ACT7803, SN74ACT7805, and SN74ACT7813 Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Lead Spacing description The SN74ALVC7813 is suited for buffering asynchronous data paths up to 50-MHz clock rates and 13-ns access times. This device is designed for 3-V to 3.6-V VCC operation. Two devices can be configured for bidirectional data buffering without additional logic. DL PACKAGE (TOP VIEW) RESET D17 D16 D15 D14 D13 D12 D11 D10 VCC D9 D8 GND D7 D6 D5 D4 D3 D2 D1 D0 HF PEN AF/AE WRTCLK WRTEN2 WRTEN1 IR 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 OE1 Q17 Q16 Q15 GND Q14 VCC Q13 Q12 Q11 Q10 Q9 GND Q8 Q7 Q6 Q5 VCC Q4 Q3 Q2 GND Q1 Q0 RDCLK RDEN OE2 OR The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident. Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low and output ready (OR) is high. The first word written to memory is clocked through to the output buffer, regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer. The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET) must be asserted while at least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be reset upon power up. The SN74ALVC7813 is characterized for operation from 0°C to 70°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALVC7813 64 × 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS594A – OCTOBER 1997 – REVISED APRIL 1998 logic symbol† 1 RESET WRTCLK WRTEN1 Φ FIFO 64 × 18 RESET 25 WRTCLK 27 & WRTEN 26 In Ready WRTEN2 RDCLK 32 Almost-Full/Empty 56 OE1 Half-Full RDCLK & 30 Out Ready EN1 28 22 24 29 IR HF AF/AE OR OE2 & RDEN 31 RDEN PEN D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 23 21 Program Enable 0 0 34 19 36 18 37 17 38 16 40 15 41 14 42 12 43 11 45 Data Data 1 9 46 8 47 7 48 6 49 5 51 4 53 3 54 2 55 17 17 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 33 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 SN74ALVC7813 64 × 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS594A – OCTOBER 1997 – REVISED APRIL 1998 functional block diagram OE1 OE2 Output Control D0–D17 RDCLK RDEN Synchronous Read Control RAM Read Pointer 64 × 18 WRTCLK WRTEN1 WRTEN2 Synchronous Write Control Write Pointer Register RESET StatusFlag Logic Reset Logic Q0–Q17 OR IR HF PEN AF/AE POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALVC7813 64 × 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS594A – OCTOBER 1997 – REVISED APRIL 1998 Terminal Functions TERMINAL I/O DESCRIPTION 24 O Almost-full/almost-empty flag. Depth-offset values can be programmed for this flag, or the default value of 8 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is high when memory contains X or fewer words or (64 – Y) or more words. AF/AE is high after reset. 2–9, 11–12, 14–21 I 18-bit data input port HF 22 O Half-full flag. HF is high when the FIFO memory contains 32 or more words. HF is low after reset. IR 28 O Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low, the FIFO is full and writes are disabled. IR is low during reset and goes high on the second low-to-high transition of WRTCLK after reset. OE1 OE2 56 30 I Output enables. When OE1, OE2, and RDEN are low and OR is high, data is read from the FIFO on a low-to-high transition of RDCLK. When either OE1 or OE2 is high, reads are disabled and the data outputs are in the high-impedance state. NAME AF/AE D0–D17 4 NO. OR 29 O Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the FIFO is empty and reads are disabled. Ready data is present on Q0–Q17 when OR is high. OR is low during reset and goes high on the third low-to-high transition of RDCLK after the first word is loaded to empty memory. PEN 23 I Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D7 is latched as an AF/AE offset value when PEN is low and WRTCLK is high. Q0–Q17 33–34, 36–38, 40–43, 45–49, 51, 53–55 O 18-bit data output port. After the first valid write to empty memory, the first word is output on Q0–Q17 on the third rising edge of RDCLK. OR also is asserted high at this time to indicate ready data. When OR is low, the last word read from the FIFO is present on Q0–Q17. RDCLK 32 I Read clock. RDCLK is a continuous clock and can be asynchronous or coincident to WRTCLK. A low-to-high transition of RDCLK reads data from memory when OE1, OE2, and RDEN are low and OR is high. OR is synchronous to the low-to-high transition or RDCLK. RDEN 31 I Read enable. When RDEN, OE1, and OE2 are low and OR is high, data is read from the FIFO on the low-to-high transition of RDCLK. RESET 1 I Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of WRTCLK must occur while RESET is low. This sets HF, IR, and OR low and AF/AE high. WRTCLK 25 I Write clock. WRTCLK is a continuous clock and can be asynchronous or coincident to RDCLK. A low-to-high transition of WRTCLK writes data to memory when WRTEN2 is low, WRTEN1 is high, and IR is high. IR is synchronous to the low-to-high transition of WRTCLK. WRTEN1 WRTEN2 27 26 I Write enables. When WRTEN1 is high, WRTEN2 is low, and IR is high, data is written to the FIFO on a low-to-high transition of WRTCLK. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC7813 64 × 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS594A – OCTOBER 1997 – REVISED APRIL 1998 RESET PEN 1 WRTCLK 2 3 4 1 2 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ WRTEN1 Don’t Care WRTEN2 Don’t Care Don’t Care D0–D17 1 RDCLK 2 3 4 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ OE1 Don’t Care RDEN Don’t Care OE2 Don’t Care Q0–Q17 Invalid OR Don’t Care AF/AE Don’t Care HF Don’t Care IR Don’t Care Define the AF/AE Flag Using the Default Value of X = Y = 8 Figure 1. Reset Cycle POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALVC7813 64 × 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS594A – OCTOBER 1997 – REVISED APRIL 1998 RESET 1 0 PEN 1 0 WRTCLK 1 0 WRTEN1 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ WRTEN2 D0–D17 RDCLK W1 W2 W3 W4 1 2 3 W(X+2) A B C 1 0 OE1 1 0 1 0 RDEN OE2 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ Q0–Q17 Invalid W1 OR AF/AE HF IR DATA-WORD NUMBER FOR FLAG TRANSITIONS DEVICE SN74ALVC7813 TRANSITION WORD A B C W33 W(65 – Y) W65 Figure 2. FIFO Write 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC7813 64 × 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS594A – OCTOBER 1997 – REVISED APRIL 1998 RESET 1 0 PEN 1 0 2 1 WRTCLK WRTEN1 WRTEN2 D0–D17 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 1 0 W513 RDCLK 1 0 OE1 RDEN OE2 Q0–Q17 ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ W1 W2 W3 W(Y+1) W(Y+2) A B C D E F OR AF/AE HF IR DATA-WORD NUMBERS FOR FLAG TRANSITIONS DEVICE SN74ALVC7813 TRANSITION WORD A B C D E F W33 W34 W(64 – X) W(65 – X) 64 65 Figure 3. FIFO Read POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74ALVC7813 64 × 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS594A – OCTOBER 1997 – REVISED APRIL 1998 offset values for AF/AE The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset value (Y). They can be programmed after the FIFO is reset and before the first word is written to memory. If the offsets are not programmed, the default values of X = Y = 8 are used. The AF/AE flag is high when the FIFO contains X or fewer words or (64 – Y) or more words. Program enable (PEN) should be held high throughout the reset cycle. PEN can be brought low only when IR is high. On the following low-to-high transition of WRTCLK, the binary value on D0–D7 is stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PEN low for another low-to-high transition of WRTCLK reprograms Y to the binary value on D0–D7 at the time of the second WRTCLK low-to-high transition. When the offsets are being programmed, writes to the FIFO memory are disabled, regardless of the state of the write enables (WRTEN1, WRTEN2). A maximum value of 63 can be programmed for either X or Y (see Figure 4). To use the default values of X = Y = 8, PEN must be held high. RESET WRTCLK PEN D0–D7 IR WRTEN1 WRTEN2 3 4 ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ É ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉ É ÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ X and Y Y Figure 4. Programming X and Y Separately 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC7813 64 × 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS594A – OCTOBER 1997 – REVISED APRIL 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Voltage range applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Input clamp current, IIK ( VI < 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK ( VO < 0 or VO > VCC ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO ( VO = 0 to VCC ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings can be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions ’ALVC7813-20 MAX MIN MAX MIN MAX 3.6 3 3.6 3 3.6 Supply voltage 3 High-level input voltage 2 VIL IOH Low-level input voltage IOL TA Low-level output current, Q outputs, flags VCC = 3 V VCC = 3 V Operating free-air temperature ’ALVC7813-40 MIN VCC VIH High-level output current, Q outputs, flags ’ALVC7813-25 2 V V 0.8 0.8 0.8 V –8 –8 –8 mA 16 mA 70 °C 16 0 2 UNIT 70 16 0 70 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK TEST CONDITIONS MIN TYP‡ MAX UNIT –1.2 V VCC = 3 V, VCC = 3 V to 3.6 V, IIK = –18 mA IOH = –100 µA VCC = 3 V, VCC = 3 V to 3.6 V, IOH = –8 mA IOL = 100 µA VCC = 3 V, VCC = 3 V, IOL = 8 mA IOL = 16 mA 0.55 II IOZ VCC = 3.6 V, VCC = 3.6 V, VI = VCC or GND VO = VCC or GND ±5 µA ±10 µA ICC ∆ICC§ VI = VCC or 0 VCC = 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND 40 µA 500 µA Ci VCC = 3.3 V, VCC = 3.3 V, VOH Flags Q outputs Flags, Flags, Q outputs VOL Flags Q outputs VI = VCC or GND VO = VCC or GND VCC–0.2 2.4 Co ‡ All typical values are at VCC = 3.3 V, TA = 25°C. § This is the supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 0.2 0.4 V 2.5 pF 5.5 pF 9 SN74ALVC7813 64 × 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS594A – OCTOBER 1997 – REVISED APRIL 1998 timing requirements over recommended operating conditions (see Figures 1 through 5) ’ALVC7813-20 MIN fclock tw Clock frequency Pulse duration tsu Setup time th MAX Hold time ’ALVC7813-25 MIN 50 MAX ’ALVC7813-40 MIN 40 25 D0–D17 high or low 9 10 14 WRTCLK high or low 7 8 12 RDCLK high or low 7 8 12 PEN low 9 9 12 WRTEN1 high, WRTEN2 low 8 8 12 OE1, OE2 low 9 9 12 RDEN low 8 8 12 D0–D17 before WRTCLK↑ 5 5 5 WRTEN1, WRTEN2 before WRTCLK↑ 5 5 5 OE1, OE2 before RDCLK↑ 5 6 6 RDEN before RDCLK↑ 5 5 7 Reset: RESET low before first WRTCLK↑ and RDCLK↑† 6 6 6 PEN before WRTCLK↑ 6 6 6 D0–D17 after WRTCLK↑ 0 0 0 WRTEN1, WRTEN2 after WRTCLK↑ 0 0 0 OE1, OE2, RDEN after RDCLK↑ 0 0 0 Reset: RESET low after fourth WRTCLK↑ and RDCLK↑† 2 2 2 2 2 2 PEN low after WRTCLK↑ † To permit the clock pulse to be utilized for reset purposes MAX UNIT MHz ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 5) PARAMETER FROM (OUTPUT) fmax WRTCLK or RDCLK RDCLK↑ tpd ’ALVC7813-20 TO (INPUT) MIN MAX 50 ’ALVC7813-25 MIN MAX ’ALVC7813-40 MIN 40 MAX 25 UNIT MHz Any Q 4 13 4 15 4 20 WRTCLK↑ IR 3 11 3 13 3 15 RDCLK↑ OR 3 11 3 13 3 15 7 19 7 21 7 23 7 19 7 21 7 23 HF 7 17 7 19 7 21 ns WRTCLK↑ AF/AE RDCLK↑ ns tPLH tPHL WRTCLK↑ RDCLK↑ HF 7 18 7 20 7 22 ns tPLH RESET low AF/AE 2 11 2 13 2 15 ns tPHL RESET low HF 2 12 2 14 2 16 ns ten OE1, OE2 Any Q 2 11 2 11 2 14 ns tdis OE1, OE2 Any Q 2 11 2 14 2 14 ns operating characteristics, VCC = 3.3 V, TA = 25°C PARAMETER Cpd 10 Power dissipation capacitance TEST CONDITIONS Outputs enabled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CL = 50 pF, f = 5 MHz TYP 53 UNIT pF SN74ALVC7813 64 × 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS594A – OCTOBER 1997 – REVISED APRIL 1998 PARAMETER MEASUREMENT INFORMATION PARAMETER 6V S1 500 Ω From Output Under Test Open ten GND tdis CL = 50 pF (see Note A) 500 Ω tpd LOAD CIRCUIT FOR OUTPUTS S1 tPZH tPZL tPHZ tPLZ GND 6V GND 6V tPHL/tPLH Open tw 3V 3V Timing Input Input 1.5 V 0V 1.5 V 0V tsu 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 0V tPLH 1.5 V 1.5 V Output Waveform 1 S1 at 6 V (see Note B) 1.5 V VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V 0V tPLZ 3V 1.5 V tPZH tPHL VOH Output 3V Output Control (low-level enabling) tPZL 3V 1.5 V VOLTAGE WAVEFORMS PULSE DURATION th 3V Data Input Input (see Note C) 1.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. Figure 5. Standard CMOS Outputs (FULL, EMPTY, HF, AF/AE) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN74ALVC7813 64 × 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS594A – OCTOBER 1997 – REVISED APRIL 1998 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs CLOCK FREQUENCY 140 fdata = 1/2 fclock TA = 75°C CL = 0 pF I CC(f) – Supply Current – mA 120 VCC = 3.6 V 100 VCC = 3.3 V 80 60 VCC = 3 V 40 20 0 0 10 20 30 40 50 60 70 fclock – Clock Frequency – MHz Figure 6 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 80 90 SN74ALVC7813 64 × 18 LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS594A – OCTOBER 1997 – REVISED APRIL 1998 APPLICATION INFORMATION SN74ALVC7813 WRTCLK RDCLK CLOCK A W/RA WRTEN1 OE1 CSA WRTEN2 RDEN CLOCK B W/RB CSB OE2 18 D0–D17 Q0–Q17 B0–B17 SN74ALVC7813 RDCLK WRTCLK OE1 WRTEN1 RDEN WRTEN2 OE2 18 A0–A17 Q0–Q17 D0–D17 Figure 7. Bidirectional Configuration SN74ALVC7813 WRTCLK RDCLK WRTCLK WRTEN1 WRTEN1 RDEN WRTEN2 WRTEN2 OE1 IR RDCLK OE1 OR OE2 OE2 36 D0–D35 D0–D17 Q0–Q17 OR IR SN74ALVC7813 WRTCLK RDCLK WRTEN1 RDEN WRTEN2 OE1 IR OR OE2 36 D0–D17 Q0–Q17 Figure 8. Word-Width Expansion: 64 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q0–Q35 36 Bits 13 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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