SN74ALVC7814 64 × 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY SCAS592A – OCTOBER 1997 – REVISED APRIL 1998 D D D D D D D D D D D Member of the Texas Instruments Widebus Family Low-Power Advanced CMOS Technology Operates From 3-V to 3.6-V VCC Load Clock and Unload Clock Can Be Asynchronous or Coincident Full, Empty, and Half-Full Flags Programmable Almost-Full/Almost-Empty Flag Fast Access Times of 18 ns With a 50-pF Load and All Data Outputs Switching Simultaneously Data Rates up to 40 MHz 3-State Outputs Pin-to-Pin Compatible With SN74ACT7804, SN74ACT7806, and SN74ACT7814 Packaged in Shrink Small-Outline 300-mil Package Using 25-mil Center-to-Center Spacing description A FIFO memory is a storage device that allows data to be written into and read from its array at independent data rates. The SN74ALVC7814 is an 18-bit FIFO with high speed and fast access times. Data is processed at rates up to 40 MHz with access times of 18 ns in a bit-parallel format. These memories are designed for 3-V to 3.6-V VCC operation. DL PACKAGE (TOP VIEW) RESET D17 D16 D15 D14 D13 D12 D11 D10 VCC D9 D8 GND D7 D6 D5 D4 D3 D2 D1 D0 HF PEN AF/AE LDCK NC NC FULL Data is written into memory on a low-to-high transition of the load clock (LDCK) and is read out on a low-to-high transition of the unload clock (UNCK). The memory is full when the number of words clocked in exceeds the number of words clocked out by 64. When the memory is full, LDCK has no effect on the data residing in memory. When the memory is empty, UNCK has no effect. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 OE Q17 Q16 Q15 GND Q14 VCC Q13 Q12 Q11 Q10 Q9 GND Q8 Q7 Q6 Q5 VCC Q4 Q3 Q2 GND Q1 Q0 UNCK NC NC EMPTY NC – No internal connection Status of the FIFO memory is monitored by the full (FULL), empty (EMPTY), half-full (HF), and almostfull/almost-empty (AF/AE) flags. The FULL output is low when the memory is full and high when the memory is not full. The EMPTY output is low when the memory is empty and high when it is not empty. The HF output is high whenever the FIFO contains 32 or more words and low when it contains 31 or fewer words. The AF/AE status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN) is low. The AF/AE flag is high when the FIFO contains X or fewer words or (64 – Y) or more words. The AF/AE flag is low when the FIFO contains between (X + 1) and (63 – Y) words. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALVC7814 64 × 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY SCAS592A – OCTOBER 1997 – REVISED APRIL 1998 description (continued) A low level on the reset (RESET) resets the internal stack pointers and sets FULL high, AF/AE high, HF low, and EMPTY low. The Q outputs are not reset to any specific logic level. The FIFO must be reset on power up. The first word loaded into empty memory causes EMPTY to go high and the data to appear on the Q outputs. The data outputs are in the high-impedance state when the output-enable (OE) is high. The SN74ALVC7814 is characterized for operation from 0°C to 70°C. logic symbol† Φ FIFO 64 × 18 RESET LDCK UNCK OE PEN D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 1 RESET 25 32 56 23 21 Full LDCK Half-Full UNCK Almost Full/Empty EN1 Empty 22 24 FULL HF AF/AE 29 EMPTY Program Enable 0 0 33 20 34 19 36 18 37 17 38 16 40 15 41 14 42 12 43 11 45 Data Data 1 9 46 8 47 7 48 6 49 5 51 4 53 3 54 2 55 17 17 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 Q16 Q17 SN74ALVC7814 64 × 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY SCAS592A – OCTOBER 1997 – REVISED APRIL 1998 functional block diagram OE D0–D17 RAM Read Pointer UNCK 64 × 18 Write Pointer LDCK Q0–Q17 EMPTY Reset Logic RESET StatusFlag Logic PEN FULL HF AF/AE Terminal Functions TERMINAL I/O DESCRIPTION 24 O Almost full/almost empty flag. Depth-offset values can be programmed for this flag or the default value of 64 can be used for both the almost empty offset (X) and the almost full offset (Y). AF/AE is high when memory contains X or fewer words or (64 – Y) or more words. AF/AE is high after reset. D0–D17 2–9, 11–12, 14–21 I 18-bit data input port EMPTY 29 O Empty flag. EMPTY is low when the FIFO is empty. A FIFO reset also causes EMPTY to go low. FULL 28 O Full flag. FULL is low when the FIFO is full. A FIFO reset causes FULL to go high. HF 22 O Half-full flag. HF is high when the FIFO memory contains 32 or more words. HF is low after reset. LDCK 25 I Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high. OE 56 I Output enable. When OE is high, the data outputs are in the high-impedance state. PEN 23 I Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D7 is latched as an AF/AE offset value when PEN is low and WRTCLK is high. Q0–Q17 33–34, 36–38, 40–43, 45–49, 51, 53–55 O 18-bit data output port RESET 1 I Reset. A low level on RESET resets the FIFO and drives AF/AE and FULL high and HF and EMPTY low. UNCK 32 I Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high. NAME NO. AF/AE POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 0 ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ ÎÎ LDCK D0–D17 W1 W2 W (X+1) A B Don’t Care C 1 OE W1 W2 W (Y+1) W (Y+2) D E EMPTY AF/AE HF FULL Define the AF/AE Flag Using the Default Value of X and Y Figure 1. Write, Read, and Flag Timing Reference F G H ÎÎ ÎÎ ÎÎ ÎÎ • DALLAS, TEXAS 75265 Q0–Q17 0 ÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎ POST OFFICE BOX 655303 UNCK I SN74ALVC7814 64 × 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY 1 PEN SCAS592A – OCTOBER 1997 – REVISED APRIL 1998 4 RESET SN74ALVC7814 64 × 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY SCAS592A – OCTOBER 1997 – REVISED APRIL 1998 DATA-WORD NUMBERS FOR FLAG TRANSITIONS TRANSITION WORD DEVICE SN74ALVC7814 A B C D E F G H I W32 W(64 – Y) W64 W33 W34 W(64 – X) W(65 – X) W64 W64 Figure 1. Write, Read, and Flag Timing Reference (Continued) offset values for AF/AE The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset value (Y). They can be programmed after the FIFO is reset and before the first word is written to memory. The AF/AE flag is high when the FIFO contains X or fewer words or (512 – Y) or more words. To program the offset values, PEN can be brought low after reset. On the following low-to-high transition of LDCK, the binary value on D0–D7 is stored as the almost-empty offset value (X) and the almost-full offset value (Y). Holding PEN low for another low-to-high transition of LDCK reprograms Y to the binary value on D0–D7 at the time of the second LDCK low-to-high transition. Writes to the FIFO memory are disabled while the offsets are programmed. A maximum value of 32 can be programmed for either X or Y (see Figure 2). To use the default values of X = Y = 8, PEN must be held high.Figure 1 RESET LDCK ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌ PEN Don’t Care ÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎ Î ÏÏÏÏÏÏ ÏÏÏÏÏÏ D0–D17 Don’t Care X and Y Y EMPTY Figure 2. Programming X and Y Separately POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALVC7814 64 × 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY SCAS592A – OCTOBER 1997 – REVISED APRIL 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V 50 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C * † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings can be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions ’ALVC7814-25 ’ALVC7814-40 MIN MAX MIN MAX 3.6 3 3.6 VCC VIH Supply voltage 3 High-level input voltage 2 VIL VI Low-level input voltage VO IOH Output voltage IOL TA Low-level output current, Q outputs, flags 2 0.8 Input voltage 0 0 High-level output current, Q outputs, flags VCC = 3 V VCC = 3 V Operating free-air temperature VCC VCC 0 0 –8 16 0 70 0 UNIT V V 0.8 V VCC VCC V V –8 mA 16 mA 70 °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH Flags Q outputs Flags, Flags, Q outputs VOL Flags Q outputs II IOZ ICC ∆ICC§ Ci TEST CONDITIONS MIN MAX UNIT VCC = 3 V to 3.6 V, VCC = 3 V, IOH = –100 µA IOH = –8 mA VCC = 3 V to 3.6 V, VCC = 3 V, IOL = 100 µA IOL = 8 mA VCC = 3 V, VCC = 3.6 V, IOL = 16 mA VI =VCC or GND 0.55 ±5 µA VCC = 3.6 V, VCC = 3.6 V, VO =VCC or GND VI = VCC or GND, ±10 µA 40 µA 500 µA VCC–0.2 2.4 0.4 IO = 0 VCC = 3.6 V, One input at VCC–0.6 V, Other inputs at VCC or GND VCC = 3.3 V, VI = VCC or GND VCC = 3.3 V, VO = VCC or GND ‡ All typical values are at VCC = 3.3 V, TA = 25°C. § This is the supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. POST OFFICE BOX 655303 V 0.2 Co 6 TYP‡ • DALLAS, TEXAS 75265 V 3 pF 6 pF SN74ALVC7814 64 × 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY SCAS592A – OCTOBER 1997 – REVISED APRIL 1998 timing requirements over recommended operating conditions (see Figures 1 through 3) ’ALVC7814-25 MIN fclock tw Clock frequency th ’ALVC7814-40 MIN 40 Pulse duration Setup time Hold time MAX 25 D0–D17 high or low 8 12 LDCK high or low 8 12 UNCK high or low 8 12 PEN low 8 12 RESET low tsu MAX 10 12 D0–D17 before LDCK↑ 5 5 LDCK inactive before RESET high 6 6 PEN before LDCK↑ 8 8 D0–D17 after LDCK↑ 0 0 PEN high after LDCK low 0 0 PEN low after LDCK↑ 3 3 LDCK inactive after RESET high 6 6 UNIT MHz ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 3) ’ALVC7814-40 FROM (INPUT) fmax LDCK or UNCK 40 LDCK↑ 9 22 9 24 6 18 6 20 6 17 6 19 6 17 6 19 4 18 4 20 6 17 6 19 4 20 4 22 6 17 6 19 7 20 7 22 7 20 7 22 tpd d tPLH tPHL tPLH tPHL tpd d tPLH tPHL ten tdis UNCK↑ LDCK↑ TO (OUTPUT) ’ALVC7814-25 PARAMETER Any Q EMPTY UNCK↑ RESET low EMPTY UNCK↑ RESET low LDCK↑ LDCK↑ UNCK↑ FULL FULL AF/AE MIN MAX MIN MAX 25 MHz RESET low AF/AE 2 12 2 14 LDCK↑ HF 5 20 5 22 7 20 7 22 3 14 3 16 UNCK↑ RESET low HF UNIT ns ns ns ns ns ns ns ns OE Any Q 2 10 2 11 ns OE Any Q 2 11 2 12 ns operating characteristics, VCC = 3.3 V, TA = 25°C PARAMETER Cpd Power dissipation capacitance per FIFO channel POST OFFICE BOX 655303 TEST CONDITIONS Outputs enabled • DALLAS, TEXAS 75265 CL = 50 pF, f = 5 MHz TYP 53 UNIT pF 7 SN74ALVC7814 64 × 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY SCAS592A – OCTOBER 1997 – REVISED APRIL 1998 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test CL = 50 pF (see Note A) PARAMETER Open ten GND 500 Ω tdis tpd S1 tPZH GND tPZL 6V tPHZ GND tPLZ 6V tPLH/tPHL Open LOAD CIRCUIT FOR OUTPUTS tw 3V 3V Timing Input 1.5 V 0V 0V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 0V tPLH Output Control (low-level enabling) 1.5 V VOH 1.5 V VOL tPLZ 3V 1.5 V tPZH Output Waveform 2 S1 at GND (see Note B) 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPHL 1.5 V 3V tPZL 3V 1.5 V VOLTAGE WAVEFORMS PULSE DURATION th 3V Data Input Output 1.5 V 1.5 V tsu Input (see Note C) Input VOL + 0.3 V VOL tPHZ 1.5 V VOH VOH – 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. Figure 3. Standard CMOS Outputs (FULL, EMPTY, HF, AF/AE) 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC7814 64 × 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY SCAS592A – OCTOBER 1997 – REVISED APRIL 1998 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs CLOCK FREQUENCY 140 fdata = 1/2 fclock TA = 75°C CL = 0 pF I CC(f) – Supply Current – mA 120 VCC = 3.6 V 100 VCC = 3.3 V 80 60 VCC = 3 V 40 20 0 0 10 20 30 40 50 60 70 80 90 fclock – Clock Frequency – MHz Figure 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN74ALVC7814 64 × 18 LOW-POWER FIRST-IN, FIRST-OUT MEMORY SCAS592A – OCTOBER 1997 – REVISED APRIL 1998 APPLICATION INFORMATION LDCK SN74ALVC7814 LDCK UNCK FULL UNCK EMPTY EMPTY FULL OE D18–D35 D0–D17 OE Q18–Q35 Q0–Q17 SN74ALVC7814 LDCK UNCK FULL EMPTY OE D0–D17 D0–D17 Q0–Q17 Figure 5. Word-Width Expansion: 64 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Q0–Q17 36 Bits PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74ALVC7814-25DL ACTIVE SSOP DL 56 SN74ALVC7814-25DLR ACTIVE SSOP DL 56 SN74ALVC7814-40DL ACTIVE SSOP DL 56 SN74ALVC7814-40DLR ACTIVE SSOP DL 56 20 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 20 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). 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