SN74ACT2226, SN74ACT2228 DUAL 64 × 1, DUAL 256 × 1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219C – JUNE 1992 – REVISED OCTOBER 1997 D D D D D D D D D Dual Independent FIFOs Organized as: 64 Words by 1 Bit Each – SN74ACT2226 256 Words by 1 Bit Each – SN74ACT2228 Free-Running Read and Write Clocks Can Be Asynchronous or Coincident on Each FIFO Input-Ready Flags Synchronized to Write Clocks Output-Ready Flags Synchronized to Read Clocks Half-Full and Almost-Full/Almost-Empty Flags Support Clock Frequencies up to 22 MHz Access Times of 20 ns Low-Power Advanced CMOS Technology Packaged in 24-Pin Small-Outline Integrated-Circuit Package DW PACKAGE (TOP VIEW) 1HF 1AF/AE 1WRTCLK 1WRTEN 1IR 1D GND 1RESET 2Q 2OR 2RDEN 2RDCLK 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 1RDCLK 1RDEN 1OR 1Q 2RESET VCC 2D 2IR 2WRTEN 2WRTCLK 2AF/AE 2HF description The SN74ACT2226 and SN74ACT2228 are dual FIFOs suited for a wide range of serial-data buffering applications, including elastic stores for frequencies up to T2 telecommunication rates. Each FIFO on the chip is arranged as 64 × 1 (SN74ACT2226) or 256 × 1 (SN74ACT2228) and has control signals and status flags for independent operation. Output flags for each FIFO include input ready (1IR or 2IR), output ready (1OR or 2OR), half full (1HF or 2HF), and almost full/almost empty (1AF/AE or 2AF/AE). Serial data is written into a FIFO on the low-to-high transition of the write-clock (1WRTCLK or 2WRTCLK) input when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR) output are both high. Serial data is read from a FIFO on the low-to-high transition of the read-clock (1RDCLK or 2RDCLK) input when the read-enable (1RDEN or 2RDEN) input and output-ready flag (1OR or 2OR) output are both high. The read and write clocks of a FIFO can be asynchronous to one another. Each input-ready flag (1IR or 2IR) is synchronized by two flip-flop stages to its write clock (1WRTCLK or 2WRTCLK), and each output-ready flag (1OR or 2OR) is synchronized by three flip-flop stages to its read clock (1RDCLK or 2RDCLK). This multistage synchronization ensures reliable flag-output states when data is written and read asynchronously. A half-full flag (1HF or 2HF) is high when the number of bits stored in its FIFO is greater than or equal to half the depth of the FIFO. An almost-full/almost-empty flag (1AF/AE or 2AF/AE) is high when eight or fewer bits are stored in its FIFO and when eight or fewer empty locations are left in the FIFO. A bit present on the data output is not stored in the FIFO. The SN74ACT2226 and SN74ACT2228 are characterized for operation from –40°C to 85°C. For more information on this device family, see the application report FIFOs With a Word Width of One Bit (literature number SCAA006). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ACT2226, SN74ACT2228 DUAL 64 × 1, DUAL 256 × 1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219C – JUNE 1992 – REVISED OCTOBER 1997 logic symbols† 8 1RESET 1WRTCLK 1WRTEN 1RDCLK 1RDEN 1D 3 4 24 23 20 2WRTEN 2RDCLK 2RDEN 2D 1WRTCLK 1WRTEN 1RDCLK 1RDEN 1D 12 11 2RDCLK 2RDEN 2D WRTEN HALF FULL ALMOST FULL/EMPTY RDCLK OUT RDY 3 4 24 23 RESET IN RDY HALF FULL WRTEN ALMOST FULL/EMPTY RDCLK OUT RDY 1HF 1AF/AE 1OR 17 13 14 10 1Q 2IR 2HF 2AF/AE 2OR 2Q Φ FIFO 256 × 1 SN74ACT2228 RESET IN RDY WRTCLK WRTEN HALF FULL ALMOST FULL/EMPTY RDCLK OUT RDY 5 1 2 22 1IR 1HF 1AF/AE 1OR RDEN 21 RESET IN RDY HALF FULL WRTEN RDCLK ALMOST FULL/EMPTY OUT RDY 17 13 14 10 1Q 2IR 2HF 2AF/AE 2OR RDEN 18 9 † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 22 9 WRTCLK 11 2 1IR RDEN 15 12 1 21 6 16 5 RDEN 18 20 2WRTEN WRTCLK WRTCLK 16 2RESET 2WRTCLK IN RDY 15 8 1RESET RESET 6 2RESET 2WRTCLK Φ FIFO 64 × 1 SN74ACT2226 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2Q SN74ACT2226, SN74ACT2228 DUAL 64 × 1, DUAL 256 × 1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219C – JUNE 1992 – REVISED OCTOBER 1997 SN74ACT2226 functional block diagram (each FIFO) D Location 1 RDCLK RDEN WRTCLK WRTEN Synchronous Read Control Synchronous Write Control Read Pointer Write Pointer Location 2 Dual-Port SRAM 64 × 1 Location 63 Location 64 Register Q AF/AE Status HF Reset Logic IR RESET OR SN74ACT2228 functional block diagram (each FIFO) D Location 1 RDCLK RDEN WRTCLK WRTEN Synchronous Read Control Synchronous Write Control Read Pointer Write Pointer Location 2 Dual-Port SRAM 256 × 1 Location 255 Location 256 Register Q AF/AE Status Reset Logic HF IR RESET OR POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ACT2226, SN74ACT2228 DUAL 64 × 1, DUAL 256 × 1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219C – JUNE 1992 – REVISED OCTOBER 1997 Terminal Functions TERMINAL NAME 4 NO. I/O DESCRIPTION 1AF/AE 2AF/AE 2 14 O Almost-full/almost-empty flag. AF/AE is high when the memory is eight locations or less from a full or empty state. AF/AE is set high after reset. 1D 2D 6 18 I Data input GND 7 1HF 2HF 1 13 O Half-full flag. HF is high when the number of bits stored in memory is greater than or equal to half the FIFO depth. HF is set low after reset. 1IR 2IR 5 17 O Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low, the FIFO is full and writes are disabled. IR is set low during reset and is set high on the second low-to-high transition of WRTCLK after reset. 1OR 2OR 22 10 O Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the FIFO is empty and reads are disabled. Ready data is present on the data output when OR is high. OR is set low during reset and set high on the third low-to-high transition of RDCLK after the first word is loaded to empty memory. 1Q 2Q 21 9 O Data outputs. After the first valid write to empty memory, the first bit is output on the third rising edge of RDCLK. OR for the FIFO is asserted high to indicate ready data. 1RDCLK 2RDCLK 24 12 I Read clock. RDCLK is a continuous clock and can be independent of any other clock on the device. A low-to-high transition of RDCLK reads data from memory when the FIFO RDEN and OR are high. OR is synchronous with the low-to-high transition of RDCLK. 1RDEN 2RDEN 23 11 I Read enable. When the RDEN and OR of a FIFO are high, data is read from the FIFO on the low-to-high transition of RDCLK. 1RESET 2RESET 8 20 I Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of WRTCLK must occur while RESET is low. This sets HF, IR, and OR low and AF/AE high. Before it is used, a FIFO must be reset after power up. VCC 19 1WRTCLK 2WRTCLK 3 15 I Write clock. WRTCLK is a continuous clock and can be independent of any other clock on the device. A low-to-high transition of WRTCLK writes data to memory when WRTEN and IR are high. IR is synchronous with the low-to-high transition of WRTCLK. 1WRTEN 2WRTEN 4 16 I Write enable. When WRTEN and IR are high, data is written to the FIFO on a low-to-high transition of WRTCLK. Ground Supply voltage POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT2226, SN74ACT2228 DUAL 64 × 1, DUAL 256 × 1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219C – JUNE 1992 – REVISED OCTOBER 1997 RESET WRTCLK WRTEN D RDCLK RDEN Q OR AF/AE HF IR 1 2 3 4 1 2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ Don’t Care Don’t Care 1 2 3 4 Don’t Care Don’t Care Don’t Care Don’t Care Don’t Care Figure 1. FIFO Reset POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ACT2226, SN74ACT2228 DUAL 64 × 1, DUAL 256 × 1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219C – JUNE 1992 – REVISED OCTOBER 1997 1 0 RESET WRTCLK 1 0 WRTEN ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ D RDCLK B1 B2 B3 B4 1 2 3 B10 A B 1 0 RDEN ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ B1 Q OR AF/AE HF IR DATA BIT NUMBER BASED ON FIFO DEPTH DATA BIT DEVICE A B C SN74ACT2226 B33 B57 B65 SN74ACT2228 B129 B249 B257 Figure 2. FIFO Write 6 C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT2226, SN74ACT2228 DUAL 64 × 1, DUAL 256 × 1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219C – JUNE 1992 – REVISED OCTOBER 1997 1 0 RESET WRTCLK 1 2 WRTEN ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ D F RDCLK RDEN Q B1 B2 B3 B9 B10 A B C D E F OR AF/AE HF IR DATA BIT NUMBER BASED ON FIFO DEPTH DEVICE DATA BIT A B C D E F SN74ACT2226 B33 B34 B56 B57 B64 B65 SN74ACT2228 B129 B130 B248 B249 B256 B257 Figure 3. FIFO Read POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74ACT2226, SN74ACT2228 DUAL 64 × 1, DUAL 256 × 1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219C – JUNE 1992 – REVISED OCTOBER 1997 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded provided that the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions VCC VIH Supply voltage VIL IOH Low-level input voltage High-level input voltage Low level output current Low-level TA Operating free-air temperature MAX 4.5 5.5 2 High-level output current IOL MIN UNIT V V 0.8 V Q outputs, flags –8 mA Q outputs 16 Flags 8 –40 85 mA °C electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL II IOZ ICC ∆ICC§ Ci Flags Q outputs TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, IOH = –8 mA IOL = 8 mA VCC = 4.5 V, VCC = 5.5 V, IOL = 16 mA VI = VCC or 0 MIN TYP‡ One input at 3.4 V, UNIT V 0.5 0.5 VCC = 5.5 V, VO = VCC or 0 VI = VCC – 0.2 V or 0 VCC = 5.5 V, VI = 0, MAX 2.4 Other inputs at VCC or GND V ±5 µA ±5 µA 400 µA 1 mA f = 1 MHz 4 pF VO = 0, f = 1 MHz ‡ All typical values are at VCC = 5 V, TA = 25°C. § This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or VCC. 8 pF Co 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ACT2226, SN74ACT2228 DUAL 64 × 1, DUAL 256 × 1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219C – JUNE 1992 – REVISED OCTOBER 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figures 1 through 3) MIN fclock Clock frequency tw Pulse duration tsu th Setup time Hold time 1WRTCLK, 2WRTCLK high or low 15 1RDCLK, 2RDCLK high or low 15 1D before 1WRTCLK↑ and 2D before 2WRTCLK↑ 6 1WRTEN before 1WRTCLK↑ and 2WRTEN before 2WRTCLK↑ 6 1RDEN before 1RDCLK↑ and 2RDEN before 2RDCLK↑ 6 1RESET low before 1WRTCLK↑ and 2RESET low before 2WRTCLK↑† 1RESET low before 1RDCLK↑ and 2RESET low before 2RDCLK↑† 6 1D after 1WRTCLK↑ and 2D after 2WRTCLK↑ 0 1WRTEN after 1WRTCLK↑ and 2WRTEN after 2WRTCLK↑ 0 1RDEN after 1RDCLK↑ and 2RDEN after 2RDCLK↑ 0 1RESET low after 1WRTCLK↑ and 2RESET low after 2WRTCLK↑† 1RESET low after 1RDCLK↑ and 2RESET low after 2RDCLK↑† 6 MAX UNIT 22 MHz ns ns 6 ns 6 † Requirement to count the clock edge as one of at least four needed to reset a FIFO switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 4) PARAMETER FROM (INPUT) fmax 1WRTCLK, 2WRTCLK, or 1RDCLK, 2RDCLK tpd MAX 22 1Q, 2Q 2 20 1IR, 2IR 1 20 1RDCLK↑, 2RDCLK↑ 1OR, 2OR 1 20 3 20 3 20 2 20 3 20 1AF/AE, 2AF/AE 1 20 1HF, 2HF 1 20 1WRTCLK↑, 2WRTCLK↑ 1RDCLK↑, 2RDCLK↑ 1RESET 2RESET low 1RESET, POST OFFICE BOX 655303 1AF/AE 2AF/AE 1AF/AE, 1HF 2HF 1HF, • DALLAS, TEXAS 75265 UNIT MHz 1RDCLK↑, 2RDCLK↑ 1RDCLK↑, 2RDCLK↑ tPLH tPHL MIN 1WRTCLK↑, 2WRTCLK↑ 1WRTCLK↑, 2WRTCLK↑ tPLH tPHL TO (OUTPUT) ns ns ns 9 SN74ACT2226, SN74ACT2228 DUAL 64 × 1, DUAL 256 × 1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219C – JUNE 1992 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION 7V PARAMETER S1 ten 500 Ω From Output Under Test Test Point CL = 50 pF (see Note A) tdis tpd 500 Ω S1 tPZH tPZL tPHZ tPLZ tPLH tPHL Open Closed Open Closed Open Open tw LOAD CIRCUIT 3V 3V Timing Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 3V Data Input 1.5 V 3V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 0V 1.5 V VOL Output Waveform 2 S1 at Open VOL + 0.3 V 1.5 V VOH VOH – 0.3 V ≈0V NOTE A: CL includes probe and jig capacitance. Figure 4. Load Circuit and Voltage Waveforms • DALLAS, TEXAS 75265 VOL tPHZ VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES POST OFFICE BOX 655303 tPLZ 1.5 V tPZH VOH 10 1.5 V ≈ 3.5 V Output Waveform 1 S1 at 7 V tPHL 1.5 V 1.5 V 0V 1.5 V tPLH Output Control tPZL 3V Output 1.5 V 1.5 V tsu Input Input SN74ACT2226, SN74ACT2228 DUAL 64 × 1, DUAL 256 × 1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219C – JUNE 1992 – REVISED OCTOBER 1997 TYPICAL CHARACTERISTICS SINGLE FIFO SUPPLY CURRENT vs CLOCK FREQUENCY I CC(f) – Supply Current – mA 18 fI = 1/2 fclock TA = 75°C CL = 0 pF 16 VCC = 5.5 V VCC = 5 V 14 12 10 VCC = 4.5 V 8 6 4 2 0 0 5 10 15 20 25 fclock – Clock Frequency – MHz Figure 5 calculating power dissipation Data for Figure 5 is taken with one FIFO active and one FIFO idle on the device. The active FIFO has both writes and reads enabled with its read clock (RDCLK) and write clock (WRTCLK) operating at the rate specified by fclock. The data input rate and data output rate are half the fclock rate, and the data output is disconnected. A close approximation of the total device power can be found by using Figure 5, determining the capacitive load on the data output and determining the number of SN74ACT2226/2228 inputs driven by TTL high levels. With ICC(f) taken from Figure 5, the maximum power dissipation (PT) of one FIFO on the SN74ACT2226 or SN74ACT2228 can be calculated by: PT = VCC × [ICC(f) + (N × ∆ICC × dc)] + (CL × VCC2 × fo) where: N ∆ICC dc CL fo = number of inputs driven by TTL levels = increase in power-supply current for each input at a TTL high level = duty cycle of inputs at a TTL high level of 3.4 V = output capacitive load = switching frequency of an output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN74ACT2226, SN74ACT2228 DUAL 64 × 1, DUAL 256 × 1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS219C – JUNE 1992 – REVISED OCTOBER 1997 APPLICATION INFORMATION An example of concentrating two independent serial-data signals into a single composite data signal with the use of an SN74ACT2226 or SN74ACT2228 device is shown in Figure 6. The input data to the FIFOs share the same average (mean) frequency and the mean frequency of the SYS_CLOCK is greater than or equal to the sum of the individual mean input rates. A single-bit FIFO is needed for each additional input data signal that is time-division multiplexed into the composite signal. The FIFO memories provide a buffer to absorb clock jitter generated by the transmission systems of incoming signals and synchronize the phase-independent inputs to one another. FIFO half-full (HF) flags are used to signal the multiplexer to start fetching data from the buffers. The state of the flags also can be used to indicate when a FIFO read should be suppressed to regulate the output flow (pulse-stuffing control). The FIFO almost-full/almost-empty (AF/AE) flags can be used in place of the half-full flags to reduce transmission delay. SN74ACT2226 or SN74ACT2228 SYS_CLOCK +5 V 1HF Serial Data Stream 1WRTCLK 1RDCLK 1RDEN 1WRTEN 1Q 1D Serial Data Stream 2WRTCLK 2RDCLK 2WRTEN 2RDEN 2D 2Q 2HF READY_1 SELECT_1 DATA_1 Time-Division Multiplexer Composite Data Stream SELECT_2 DATA_2 READY_2 Figure 6. Time-Division Multiplexing Using the SN74ACT2226 or SN74ACT2228 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 22-Sep-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74ACT2226DW ACTIVE SOIC DW 24 SN74ACT2226DWR ACTIVE SOIC DW 24 SN74ACT2228DW ACTIVE SOIC DW 24 SN74ACT2228DWR ACTIVE SOIC DW 24 25 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 25 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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