MAXIM MAX13103EETL+

19-3802; Rev 3; 6/08
16-Channel Buffered CMOS
Logic-Level Translators
♦ Wide Supply Voltage Range
VCC Range of 1.65V to 5.5V
VL Range of 1.2V to VCC
♦ ESD Protection on I/O VCC Lines
±15kV Human Body Model
♦ Up to 20Mbps Throughput
♦ Low 0.03µA Typical Quiescent Current
♦ WLP and TQFN Packages
Pin Configurations
I/O VCC8
I/O VCC9
I/O VCC10
I/O VCC11
I/O VCC12
GND
29
I/O VCC6
I/O VCC5
30
I/O VCC7
GND
TOP VIEW OF BOTTOM LEADS
28
27
26
25
24
23
22
21
20 I/O VCC13
I/O VCC4
31
I/O VCC3
32
19 I/O VCC14
I/O VCC2
33
18 I/O VCC15
I/O VCC1
34
VCC
35
VL
36
17 I/O VCC16
MAX13101E
MAX13102E
MAX13103E
16 VCC
15 VL
I/O VL1
37
14 I/O VL16
I/O VL2
38
13 I/O VL15
I/O VL3
39
I/O VL4
40
*EP
12 I/O VL14
+
5
6
7
8
9
10
I/O VL9
I/O VL10
I/O VL11
I/O VL12
EN
4
I/O VL8
3
I/O VL7
Applications
11 I/O VL13
2
I/O VL6
GND
1
I/O VL5
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-bit bidirectional CMOS logic-level translators provide the level shifting necessary to allow data transfer in
multivoltage systems. These devices are inherently
bidirectional due to their design and do not require the
use of a direction input. Externally applied voltages,
VCC and VL, set the logic levels on either side of the
devices. Logic signals present on the VL side of the
device appear as a higher voltage logic signal on the
VCC side of the device, and vice-versa.
The MAX13101E/MAX13102E/MAX13103E feature an
enable input (EN) that, when low, reduces the VCC and
VL supply currents to less than 2µA. The MAX13108E
features a multiplexing input (MULT) that selects one
byte between the two, thus allowing multiplexing of the
signals. The MAX13101E/MAX13102E/MAX13103E/
MAX13108E have ±15kV ESD protection on the I/O VCC
side for greater protection in applications that route signals externally. Three different output configurations are
available during shutdown, allowing the I/O on the VCC
side or the VL side to be put in a high-impedance state
or pulled to ground through an internal 6kΩ resistor.
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
accept V CC voltages from +1.65V to +5.5V and V L
voltages from +1.2V to VCC, making them ideal for data
transfer between low-voltage ASICs/PLDs and higher
voltage systems. The MAX13101E/MAX13102E/
MAX13103E/MAX13108E are available in 36-bump
WLP and 40-pin TQFN packages, and operate over the
extended -40°C to +85°C temperature range.
Features
*EXPOSED PAD CONNECTED TO GROUND
CMOS Logic-Level
Translation
PDAs
Digital Still Cameras
Pin Configurations continued at end of data sheet.
Portable Equipment
Smart Phones
Typical Operating Circuit appears at end of data sheet.
TQFN
Cell Phones
Ordering Information/Selector Guide
PART
PIN-PACKAGE
MAX13101EEWX+*
36 WLP**
3.06mm x 3.06mm
DATA
RATE (Mbps)
I/O VL STATE
DURING SHUTDOWN
I/O VCC STATE
DURING SHUTDOWN
MULTIPLEXER
FEATURE
20
High impedance
6kΩ to GND
No
6kΩ to GND
No
40 TQFN-EP***
20
High impedance
5mm x 5mm x 0.8mm
Note: All devices are specified over the -40°C to +85°C operating temperature range.
+Denotes a lead-free/RoHS-compliant package.
*Future product—contact factory for availability.
**WLP bumps are in a 6 x 6 array.
***EP = Exposed pad.
MAX13101EETL+
Ordering Information/Selector Guide continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX13101E/MAX13102E/MAX13103E/MAX13108E
General Description
MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.)
VCC ...........................................................................-0.3V to +6V
VL...........................................................................................-0.3V to +6V
I/O VCC_......................................................-0.3V to (VCC + 0.3V)
I/O VL_ .....................................................................-0.3V to (VL + 0.3V)
EN, MULT .................................................................-0.3V to +6V
Short-Circuit Duration I/O VL_, I/O VCC_ to GND .......Continuous
Continuous Power Dissipation (TA = +70°C)
36-Bump WLP (derate 17.0mW/°C above +70°C).....1361mW
40-Pin TQFN (derate 35.7mW/°C above +70°C) .......2857mW
Operating Temperature Range ...........................-40°C to +85°C
Maximum Junction Temperature .....................................+150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +1.65V to +5.5V, VL = +1.2V to VCC, EN = VL (MAX13101E/MAX13102E/MAX13103E), MULT = VL or GND (MAX13108E),
TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +1.65V, VL = +1.2V, TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLIES
VL Supply Range
VCC Supply Range
Supply Current from VCC
Supply Current from VL
VL
1.2
VCC
V
VCC
1.65
5.50
V
IQVCC
I/O VCC_ = GND, I/O VL _ = GND
or I/O VCC_ = VCC, I/O VL _ = VL,
EN = VL, MULT = GND or VL
0.03
10
µA
IQVL
I/O VCC_ = GND, I/O VL _ = GND
or I/O VCC_ = VCC, I/O VL _ = VL,
EN = VL, MULT = GND or VL
0.03
20
µA
VCC Shutdown Supply Current
ISHDN-VCC
TA = +25°C, EN = GND, I/O VCC_ = GND,
I/O VL _ = GND,
MAX13101E/MAX13102E/MAX13103E
0.03
1
µA
VL Shutdown Supply Current
ISHDN-VL
TA = +25°C, EN = GND, I/O VCC_ = GND,
I/O VL _ = GND,
MAX13101E/MAX13102E/MAX13103E
0.03
2
µA
TA = +25°C, EN = GND,
MAX13102E/MAX13103E
0.02
1
TA = +25°C, MULT = GND (I/O VCC1 - I/O VCC 8)
or MULT = VL (I/O VCC 9 - I/O VCC 16)
MAX13108E
0.02
1
TA = +25°C, EN = GND, MAX13101E/
MAX13103E
0.02
1
TA = +25°C, MULT = GND (I/O VL1 - I/O
VL8) or MULT = VL (I/OVL9 - I/O VL16)
MAX13108E
0.02
1
I/O VCC_ Tri-State Output
Leakage Current
I/O VL _ Tri-State Output Leakage
Current
I/O VL _ Pulldown Resistance
During Shutdown
2
EN = GND, MAX13102E
µA
µA
4
_______________________________________________________________________________________
10
kΩ
16-Channel Buffered CMOS
Logic-Level Translators
(VCC = +1.65V to +5.5V, VL = +1.2V to VCC, EN = VL (MAX13101E/MAX13102E/MAX13103E), MULT = VL or GND (MAX13108E),
TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +1.65V, VL = +1.2V, TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
I/O VCC_ Pulldown Resistance
During Shutdown
EN = GND, MAX13101E
EN or MULT Input Leakage
Current
TA = +25°C
MIN
TYP
4
MAX
UNITS
10
kΩ
1
µA
2/3 x
VL
V
LOGIC-LEVEL THRESHOLDS
I/O VL _ Input-Voltage High
Threshold
VIHL
I/O VL _ Input-Voltage Low
Threshold
VILL
I/O VCC_ Input-Voltage High
Threshold
VIHC
I/O VCC_ Input-Voltage Low
Threshold
VILC
1/3 x
VL
V
2/3 x
VCC
1/3 x
VCC
EN, MULT Input-Voltage High
Threshold
VIH-SHDN
EN, MULT Input-Voltage Low
Threshold
VIL-SHDN
I/O VL _ Output-Voltage High
VOHL
I/O VL _ source current = 20µA, I/O VCC_ ≥ VIHC VL - 0.4
I/O VL _ Output-Voltage Low
VOLL
I/O VL _ sink current = 20µA, I/O VCC_ ≤ VILC
I/O VCC_ Output-Voltage High
VOHC
I/O VCC_ Output-Voltage Low
VOLC
I/O VCC_ source current = 20µA, I/O VL _ ≥ VIHL VCC - 0.4
I/O VCC_ sink current = 20µA, I/O VL _ ≤ VILL
V
V
VL - 0.4
0.4
V
V
V
0.4
V
V
0.4
V
RISE/FALL-TIME ACCELERATOR STAGE
Transition-Detect Threshold
I/O VCC side
I/O VL side
VCC / 2
VL / 2
Accelerator Pulse Duration
VL = 1.2V, VCC = 1.65V
20
I/O VL _ Output-Accelerator Sink
Impedance
VL = 1.2V, VCC = 1.65V
60
VL = 5V, VCC = 5V
5
I/O VCC_ Output-Accelerator Sink
Impedance
VL = 1.2V, VCC = 1.65V
15
VL = 5V, VCC = 5V
5
I/O VL _ Output-Accelerator
Source Impedance
VL = 1.2V, VCC = 1.65V
30
VL = 5V, VCC = 5V
5
VL = 1.2V, VCC = 1.65V
20
VL = 5V, VCC = 5V
7
I/O VCC_ Output-Accelerator
Source Impedance
V
ns
Ω
Ω
Ω
Ω
ESD PROTECTION
I/O VCC_
Human Body Model
±15
kV
_______________________________________________________________________________________
3
MAX13101E/MAX13102E/MAX13103E/MAX13108E
ELECTRICAL CHARACTERISTICS (continued)
MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
TIMING CHARACTERISTICS
(VCC = +1.65V to +5.5V, VL = +1.2V to VCC, EN = VL (MAX13101E/MAX13102E/MAX13103E), MULT = VL or GND (MAX13108E),
TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +1.65V, VL = +1.2V, TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
15
ns
I/O VL _ Rise Time
tRVL
RS = 50Ω, CI/OVL_ = 15pF, tRISE ≤ 3ns,
(Figures 2a, 2b)
I/O VL _ Fall Time
tFVL
RS = 50Ω, CI/OVL_ = 15pF, tFALL ≤ 3ns,
(Figures 2a, 2b)
15
ns
I/O VCC_ Rise Time
tRVCC
RS = 50Ω, CI/OVCC_ = 50pF, tRISE ≤ 3ns,
(Figures 1a, 1b)
15
ns
I/O VCC_ Fall Time
tFVCC
RS = 50Ω, CI/OVCC_ = 50pF, tFALL ≤ 3ns,
(Figures 1a, 1b)
15
ns
Propagation Delay
(Driving I/O VL _)
tPVL-VCC
RS = 50Ω, CI/OVCC_ = 50pF, tRISE ≤ 3ns,
(Figures 1a, 1b)
20
ns
Propagation Delay
(Driving I/O VCC_)
tPVCC-VL
RS = 50Ω, CI/OVL_ = 15pF, tRISE ≤ 3ns,
(Figures 2a, 2b)
20
ns
tSKEW
RS = 50Ω, CI/OVCC_ = 50pF, CI/OVL_ =
15pF, tRISE ≤ 3ns
5
ns
Channel-to-Channel Skew
Part-to-Part Skew
tPPSKEW
RS = 50Ω, CI/OVCC_ = 50pF, CI/OVL_ =
15pF, tRISE ≤ 3ns, ΔTA = +20°C (Notes 3, 4)
10
ns
Propagation Delay from
I/O VL _ to I/O VCC_ After EN
tEN-VCC
CI/OVCC_ = 50pF (Figure 3)
1
µs
Propagation Delay from
I/O VCC_ to I/O VL _ After EN
tEN-VL
CI/OVL_ = 15pF (Figure 4)
1
µs
Maximum Data Rate
RSOURCE = 50Ω, CI/OVCC_ = 50pF,
CI/OVL_ = 15pF, tRISE ≤ 3ns
20
Mbps
Note 1: All units are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design
and not production tested.
Note 2: For normal operation, ensure that VL < (VCC + 0.3V). During power-up, VL > (VCC + 0.3V) does not damage the device.
Note 3: VCC from device 1 must equal VCC of device 2. VL from device 1 must equal VL of device 2.
Note 4: Guaranteed by design, not production tested.
4
_______________________________________________________________________________________
16-Channel Buffered CMOS
Logic-Level Translators
tRISE/FALL ≤ 3ns
MAX13101E
MAX13102E
MAX13103E
MAX13108E
VL
I/O VL_
VCC
90%
50%
50%
10%
EN/(MULT)
tPLH
6kΩ
tPHL
I/O VL_
I/O VCC_
I/O VCC_
SOURCE
6kΩ
RS
CI/OVCC_
90%
90%
50%
10%
10%
ALL UNUSED I/O VCC_ AND I/O VL_ CONNECTED TO GND
tFVCC
( ) ARE FOR THE MAX13108E
tRVCC
tPVL-VCC = tPHL or tPLH
Figure 1a. Driving I/O VL_
Figure 1b. Timing for Driving I/O VL_
tRISE/FALL ≤ 3ns
MAX13101E
MAX13102E
MAX13103E
MAX13108E
VL
I/O VCC_
VCC
90%
50%
50%
10%
EN/(MULT)
tPLH
6kΩ
tPHL
RS
I/O VL_
CI/OVL_
6kΩ
I/O VCC_
SOURCE
I/O VL_
90%
90%
50%
10%
10%
ALL UNUSED I/O VCC_ AND I/O VL_ CONNECTED TO GND
( ) ARE FOR THE MAX13108E
tPVCC-VL = tPHL or tPLH
Figure 2a. Driving I/O VCC_
tFVL
tRVL
Figure 2b. Timing for Driving I/O VCC_
_______________________________________________________________________________________
5
MAX13101E/MAX13102E/MAX13103E/MAX13108E
Test Circuits/Timing Diagrams
MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
Test Circuits/Timing Diagrams (continued)
MAX13101E
MAX13102E
MAX13103E
MAX13108E
VL
EN/(MULT)
tEN-VCC
EN/(MULT)
SOURCE
0
6kΩ
VL
I/O VCC_
I/O VL_
I/O VL_
0
6kΩ
VL
CI/OVCC
VCC
VCC
100kΩ
2
I/O VCC_
( ) ARE FOR THE MAX13108E
Figure 3. Propagation Delay from I/O VL_ to I/O VCC_ After EN
MAX13101E
MAX13102E
MAX13103E
MAX13108E
VL
EN/(MULT)
tEN-VL
EN/(MULT)
SOURCE
VCC
6kΩ
I/O VCC_
I/O VCC_
I/O VL_
6kΩ
100kΩ
CI/OVL
VCC
0
I/O VL_
VL
VL
2
( ) ARE FOR THE MAX13108E
Figure 4. Propagation Delay from I/O VCC_ to I/O VL_ After EN
6
0
_______________________________________________________________________________________
0
16-Channel Buffered CMOS
Logic-Level Translators
VL SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE
(DRIVING I/0 VL_, VL = 1.8V)
FIGURE 1a
CI/OVCC_ = 15pF
80
60
40
DRIVING ONE I/O VCC
1500
1000
0
0
2.0
2.5 3.0 3.5 4.0 4.5
VCC SUPPLY VOLTAGE (V)
5.0
1.5
5.5
7000
FIGURE 1a
6000
CI/OVCC_ = 15pF
5000
4000
3000
2000
5.0
8000
DRIVING ONE I/O VCC
7000
FIGURE 2a
VCC SUPPLY CURRENT (μA)
MAX13101-3/8 toc03
DRIVING ONE I/O VL
2.5 3.0 3.5 4.0 4.5
VL SUPPLY VOLTAGE (V)
5.5
VCC SUPPLY CURRENT vs. VL SUPPLY VOLTAGE
(DRIVING I/0 VCC_, VCC = 5.5V)
VCC SUPPLY CURRENT vs. VCC SUPPLY VOLTAGE
(DRIVING I/0 VL_, VL = 1.8V)
8000
2.0
MAX13101-3/8 toc04
1.5
VCC SUPPLY CURRENT (μA)
CI/OVL_ = 15pF
500
20
6000
CI/OVL_ = 15pF
5000
4000
3000
2000
1000
1000
0
0
1.5
2.0
2.5 3.0 3.5 4.0 4.5
VCC SUPPLY VOLTAGE (V)
5.0
1.5
5.5
VL SUPPLY CURRENT vs. TEMPERATURE
(DRIVING I/O VCC_)
DRIVING ONE I/O VCC
700
FIGURE 2a
CI/OVL_ = 15pF
600
500
400
300
200
2.0
2.5 3.0 3.5 4.0 4.5
VL SUPPLY VOLTAGE (V)
5.0
5.5
VCC SUPPLY CURRENT vs. TEMPERATURE
(DRIVING I/O VCC_)
3000
DRIVING ONE I/O VCC
FIGURE 2a
2500
VCC SUPPLY CURRENT (μA)
MAX13101-3/8E toc05
800
VL SUPPLY CURRENT (μA)
FIGURE 2a
2000
MAX13101-3/8 toc06
VL SUPPLY CURRENT (μA)
100
2500
MAX13101-3/8E toc02.
DRIVING ONE I/O VL
VL SUPPLY CURRENT (μA)
MAX13101-3/8E toc01
120
VL SUPPLY CURRENT vs. VL SUPPLY VOLTAGE
(DRIVING I/0 VCC_, VCC = 5.5V)
CI/OVL_ = 15pF
2000
1500
1000
500
100
0
0
-40
-15
10
35
TEMPERATURE (°C)
60
85
-40
-15
10
35
TEMPERATURE (°C)
60
85
_______________________________________________________________________________________
7
MAX13101E/MAX13102E/MAX13103E/MAX13108E
Typical Operating Characteristics
(VCC = 3.3V, VL = 1.8V, data rate = 20Mbps, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VCC = 3.3V, VL = 1.8V, data rate = 20Mbps, TA = +25°C, unless otherwise noted.)
600
400
200
3000
2000
20
30
40
CAPACITIVE LOAD (pF)
50
20
30
40
CAPACITIVE LOAD (pF)
RISE/FALL TIME (ns)
5
tFVL
10
tRVL
3
2
10
FIGURES 1a, 1b
8
PROPAGATION DELAY (ns)
FIGURES 2a, 2b
50
20
30
40
CAPACITIVE LOAD (pF)
PROPAGATION DELAY vs. CAPACITIVE LOAD
ON I/O VCC_ (DRIVING I/O VL_)
MAX13101-3/8E toc10
7
4
tFVCC
0
10
RISE/FALL TIME vs. CAPACITIVE LOAD
ON I/O VL_ (DRIVING I/O VCC_)
6
2
1
0
10
tRVCC
3
1000
0
tPLH
6
4
tPHL
2
1
0
0
10
8
MAX13101-3/8E toc09
FIGURES 1a, 1b
RISE/FALL TIME (ns)
800
FIGURE 1a
4000
4
MAX13101-3/8E toc08
FIGURE 2a
DRIVING ONE I/O VL
VCC SUPPLY CURRENT (μA)
DRIVING ONE I/O VCC
1000
5000
MAX13101-3/8E toc07
1200
RISE/FALL TIME vs. CAPACITIVE LOAD ON
I/O VCC_ (DRIVING I/O VL_)
VCC SUPPLY CURRENT vs. CAPACITIVE LOAD
ON I/O VCC_ (DRIVING I/O VL_)
MAX13101-3/8E toc11
VL SUPPLY CURRENT vs. CAPACITIVE LOAD
ON I/O VL_ (DRIVING I/O VCC_)
VL SUPPLY CURRENT (μA)
MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
20
30
40
CAPACITIVE LOAD (pF)
50
10
20
30
40
CAPACITIVE LOAD (pF)
50
_______________________________________________________________________________________
50
16-Channel Buffered CMOS
Logic-Level Translators
5
FIGURES 2a, 2b
tPHL
PROPAGATION DELAY (ns)
4
MAX13101-3/8E toc12
PROPAGATION DELAY vs. CAPACITIVE LOAD
ON I/O VL_ (DRIVING I/O VCC_)
RAIL-TO-RAIL DRIVING (DRIVING I/O VL)
MAX13101E-3/8E toc13
CI/OVCC_= 50pF
I/0 VL_
1V/div
tPLH
3
GND
2
I/0 VCC_
2V/div
1
GND
0
10
20
30
40
CAPACITIVE LOAD (pF)
10ns/div
50
Pin Description—MAX13101E/MAX13102E/MAX13103E
PIN
NAME
FUNCTION
TQFN
WLP
1, 21, 30
D6
GND
2
C2
I/O VL5
Input/Output 5. Referenced to VL.
3
A3
I/O VL6
Input/Output 6. Referenced to VL.
4
B3
I/O VL7
Input/Output 7. Referenced to VL.
5
C3
I/O VL8
Input/Output 8. Referenced to VL.
6
A4
I/O VL9
Input/Output 9. Referenced to VL.
7
B4
I/O VL10
Input/Output 10. Referenced to VL.
8
C4
I/O VL11
Input/Output 11. Referenced to VL.
9
A5
I/O VL12
Input/Output 12. Referenced to VL.
10
C6
EN
11
B5
I/O VL13
Input/Output 13. Referenced to VL.
12
C5
I/O VL14
Input/Output 14. Referenced to VL.
13
A6
I/O VL15
Input/Output 15. Referenced to VL.
14
B6
I/O VL16
Input/Output 16. Referenced to VL.
15, 36
A1
VL
16, 35
F1
VCC
17
E6
I/O VCC16 Input/Output 16. Referenced to VCC.
18
F6
I/O VCC15 Input/Output 15. Referenced to VCC.
Ground
Global Enable Input. Pull EN low for shutdown. Drive EN to VCC or VL for normal operation.
Logic Supply Voltage, +1.2V ≤ VL ≤ VCC. Bypass VL to GND with a 0.1µF capacitor.
VCC Supply Voltage, +1.65V ≤ VCC ≤ +5.5V. Bypass VCC to GND with a 0.1µF capacitor.
For full ESD protection, connect a 1.0µF capacitor from VCC to GND, located as close to the
VCC input as possible.
_______________________________________________________________________________________
9
MAX13101E/MAX13102E/MAX13103E/MAX13108E
Typical Operating Characteristics (continued)
(VCC = 3.3V, VL = 1.8V, data rate = 20Mbps, TA = +25°C, unless otherwise noted.)
MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
Pin Description—MAX13101E/MAX13102E/MAX13103E (continued)
PIN
NAME
FUNCTION
TQFN
WLP
19
D5
I/O VCC14 Input/Output 14. Referenced to VCC.
20
E5
I/O VCC13 Input/Output 13. Referenced to VCC.
22
F5
I/O VCC12 Input/Output 12. Referenced to VCC.
23
D4
I/O VCC11 Input/Output 11. Referenced to VCC.
24
E4
I/O VCC10 Input/Output 10. Referenced to VCC.
25
F4
I/O VCC9
Input/Output 9. Referenced to VCC.
26
D3
I/O VCC8
Input/Output 8. Referenced to VCC.
27
E3
I/O VCC7
Input/Output 7. Referenced to VCC.
28
F3
I/O VCC6
Input/Output 6. Referenced to VCC.
29
D2
I/O VCC5
Input/Output 5. Referenced to VCC.
31
E2
I/O VCC4
Input/Output 4. Referenced to VCC.
32
F2
I/O VCC3
Input/Output 3. Referenced to VCC.
33
D1
I/O VCC2
Input/Output 2. Referenced to VCC.
34
E1
I/O VCC1
Input/Output 1. Referenced to VCC.
37
B1
I/O VL1
Input/Output 1. Referenced to VL.
38
C1
I/O VL2
Input/Output 2. Referenced to VL.
39
A2
I/O VL3
Input/Output 3. Referenced to VL.
40
B2
I/O VL4
Input/Output 4. Referenced to VL.
—
—
EP
Exposed Pad. Connect EP to GND.
Pin Description—MAX13108E
PIN
NAME
FUNCTION
TQFN
WLP
1, 21, 30
D6
GND
2
C2
I/O VL5
Input/Output 5. Referenced to VL.
3
A3
I/O VL6
Input/Output 6. Referenced to VL.
4
B3
I/O VL7
Input/Output 7. Referenced to VL.
5
C3
I/O VL8
Input/Output 8. Referenced to VL.
6
A4
I/O VL9
Input/Output 9. Referenced to VL.
7
B4
I/O VL10
Input/Output 10. Referenced to VL.
8
C4
I/O VL11
Input/Output 11. Referenced to VL.
9
A5
I/O VL12
Input/Output 12. Referenced to VL.
10
Ground
______________________________________________________________________________________
16-Channel Buffered CMOS
Logic-Level Translators
PIN
NAME
FUNCTION
TQFN
WLP
10
C6
MULT
11
B5
I/O VL13
Input/Output 13. Referenced to VL.
12
C5
I/O VL14
Input/Output 14. Referenced to VL.
13
A6
I/O VL15
Input/Output 15. Referenced to VL.
Input/Output 16. Referenced to VL.
Multiplexing Input. Drive MULT low to enable channels 9 to 16. Driving MULT low puts
channels 1 to 8 into tri-state. Drive MULT to VCC or VL to enable channels 1 to 8. Driving
MULT to VCC or VL puts channels 9 to 16 into tri-state.
14
B6
I/O VL16
15, 36
A1
VL
16, 35
F1
VCC
17
E6
I/O VCC16 Input/Output 16. Referenced to VCC.
18
F6
I/O VCC15 Input/Output 15. Referenced to VCC.
19
D5
I/O VCC14 Input/Output 14. Referenced to VCC.
20
E5
I/O VCC13 Input/Output 13. Referenced to VCC.
22
F5
I/O VCC12 Input/Output 12. Referenced to VCC.
23
D4
I/O VCC11 Input/Output 11. Referenced to VCC.
24
E4
I/O VCC10 Input/Output 10. Referenced to VCC.
25
F4
I/O VCC9
Input/Output 9. Referenced to VCC.
26
D3
I/O VCC8
Input/Output 8. Referenced to VCC.
27
E3
I/O VCC7
Input/Output 7. Referenced to VCC.
28
F3
I/O VCC6
Input/Output 6. Referenced to VCC.
29
D2
I/O VCC5
Input/Output 5. Referenced to VCC.
31
E2
I/O VCC4
Input/Output 4. Referenced to VCC.
32
F2
I/O VCC3
Input/Output 3. Referenced to VCC.
33
D1
I/O VCC2
Input/Output 2. Referenced to VCC.
34
E1
I/O VCC1
Input/Output 1. Referenced to VCC.
37
B1
I/O VL1
Input/Output 1. Referenced to VL.
38
C1
I/O VL2
Input/Output 2. Referenced to VL.
39
A2
I/O VL3
Input/Output 3. Referenced to VL.
40
B2
I/O VL4
Input/Output 4. Referenced to VL.
—
—
EP
Logic Supply Voltage, +1.2V ≤ VL ≤ VCC. Bypass VL to GND with a 0.1µF capacitor.
VCC Supply Voltage, +1.65V ≤ VCC ≤ +5.5V. Bypass VCC to GND with a 0.1µF capacitor.
For full ESD protection, connect a 1.0µF capacitor from VCC to GND, located as close to the
VCC input as possible.
Exposed Pad. Connect EP to GND.
______________________________________________________________________________________
11
MAX13101E/MAX13102E/MAX13103E/MAX13108E
Pin Description—MAX13108E (continued)
MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
Functional Diagrams
VCC
VL
VL
VCC
MULT
EN
MAX13101E
MAX13102E
MAX13103E
MAX13108E
I/O VL1
I/O VCC1
I/O VL2
I/O VCC2
I/O VL3
I/O VL1
I/O VCC1
I/O VL2
I/O VCC2
I/O VL3
I/O VCC3
I/O VL4
I/O VCC4
I/O VL5
I/O VCC5
I/O VL6
I/O VCC6
I/O VL7
I/O VCC7
I/O VL8
I/O VCC8
I/O VL9
I/O VCC9
I/O VL10
I/O VCC10
I/O VL11
I/O VCC11
I/O VL12
I/O VCC12
I/O VL13
I/O VCC13
I/O VL14
I/O VCC14
I/O VCC15
I/O VCC3
I/O VL4
I/O VCC4
I/O VL5
I/O VCC5
I/O VL6
I/O VCC6
I/O VL7
I/O VCC7
I/O VL8
I/O VCC8
I/O VL9
I/O VCC9
I/O VL10
I/O VCC10
I/O VL11
I/O VCC11
I/O VL12
I/O VCC12
I/O VL13
I/O VCC13
I/O VL14
I/O VCC14
I/O VL15
I/O VCC15
I/O VL15
I/O VL16
I/O VCC16
I/O VL16
GND
12
I/O VCC16
GND
______________________________________________________________________________________
16-Channel Buffered CMOS
Logic-Level Translators
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
logic-level translators provide the level shifting necessary to allow data transfer in a multivoltage system.
Externally applied voltages, VCC and VL, set the logic
levels on either side of the device. Logic signals present on the VL side of the device appear as a higher
voltage logic signal on the VCC side of the device, and
vice-versa. The MAX13101E/MAX13102E/MAX13103E/
MAX13108E are bidirectional level translators allowing
data translation in either direction (V L ↔ V CC ) on
any single data line. The MAX13101E/MAX13102E/
MAX13103E/MAX13108E accept VL from +1.2V to VCC.
All devices have a VCC range from +1.65V to +5.5V,
making them ideal for data transfer between low-voltage ASICs/PLDs and higher voltage systems.
The MAX13101E/MAX13102E/MAX13103E feature an
output enable mode that reduces VCC supply current to
less than 1µA, and VL supply current to less than 2µA
when in shutdown. The MAX13108E features a multiplexing input that selects one byte between the two,
thus allowing multiplexing of the signals. The
MAX13101E/MAX13102E/MAX13103E/MAX13108E
have ±15kV ESD protection on the I/O VCC side for
greater protection in applications that route signals
externally. The MAX13101E/MAX13102E/MAX13103E/
MAX13108E operate at a guaranteed data rate of
20Mbps. The maximum data rate depends heavily
on the load capacitance (see the Typical Operating
Characteristics ) and the output impedance of the
external driver.
Power-Supply Sequencing
For proper operation, ensure that +1.65V ≤ VCC ≤ +5.5V,
+1.2V ≤ VL ≤ +5.5V, and VL ≤ VCC. During power-up
sequencing, VL ≥ VCC does not damage the device.
When VCC is disconnected and VL is powering up, up to
10mA of current can be sourced to each load on the VL
side, yet the device does not latch up. To guarantee that
no excess leakage current flows and that the device
does not interfere with the I/O on the VL side, VCC should
be connected to GND with a max 50Ω resistor when the
VCC supply is not present (Figure 5).
Input Driver Requirements
The MAX13101E/MAX13102E/MAX13103E/MAX13108E
architecture is based on a one-shot accelerator output
stage (Figure 6). Accelerator output stages are always
in tri-state except when there is a transition on any of
the translators on the input side, either I/O V L _ or
I/O V CC _. Then a short pulse is generated, during
which the accelerator output stages become active and
charge/discharge the capacitances at the I/Os. Due to
VBATT
VCC SUPPLY
DISABLE
+1.2V TO +5.5V
VCC
RDSON < 50Ω
VL
MAX13101E
MAX13102E
MAX13103E
MAX13108E
I/O VCC1
I/O VL1
I/O VCC16
I/O VL16
GND
Figure 5. Recommended Circuit for Powering Down VCC
the bidirectional nature, both input stages become
active during the one-shot pulse. This can lead to some
current feeding into the external source that is driving
the translator. However, this behavior helps to speed
up the transition on the driven side.
For proper full-speed operation, the output current of a
device that drives the inputs of the MAX13101E/
MAX13102E/MAX13103E/MAX13108E should meet the
following requirement:
i > 108 x V x (C + 10pF)
where, i is the driver output current, V is the logic-supply
voltage (i.e., VL or VCC) and C is the parasitic capacitance of the signal line.
Enable Output Mode (EN)
The MAX13101E/MAX13102E/MAX13103E feature an
enable input (EN) that, when driven low, places the
device into shutdown mode. During shutdown, the
MAX13101E I/O VCC_ ports are pulled down to ground
with internal 6kΩ resistors and the I/O VL _ ports enter
tri-state. MAX13102E I/O VCC_ lines enter tri-state and
the I/OVL _ lines are pulled down to ground with internal
6kΩ resistors. All I/O VCC_ and I/O VL _ lines on the
MAX13103E enter tri-state while the device is in shutdown mode. During shutdown, the VCC supply current
reduces to less than 1µA, and the VL supply current
reduces to less than 2µA. To guarantee minimum shutdown supply current, all I/O VL _ need to be driven to
GND or V L , or pulled to GND or V L through 100kΩ
resistors. All I/O VCC_ need to be driven to GND or
VCC, or pulled to GND or VCC through 100kΩ resistors.
Drive EN to logic-high (VL or VCC) for normal operation.
______________________________________________________________________________________
13
MAX13101E/MAX13102E/MAX13103E/MAX13108E
Detailed Description
MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
Multiplexing Input (MULT)
The MAX13108E features a multiplexing input (MULT)
that enables 8 of the 16 channels and places the
remaining 8 into tri-state. Figure 7 depicts a typical multiplexing configuration using the MAX13108E. Drive
MULT high to enable I/O VCC1 through I/O VCC8 and
I/O V L 1 through I/O V L 8. Driving MULT high sets
I/O VCC9 through I/O VCC16 and I/O VL9 through I/O
VL16 into tri-state. Drive MULT low to enable I/O VCC9
through I/O V CC 16 and I/O V L 9 through I/O V L 16.
Driving MULT low sets I/O VCC1 through I/O VCC8 and
I/O VL1 through I/O VL8 into tri-state.
VCC
VL
RISE-TIME
ACCELERATOR
I/O VL_
I/O VCC_
FALL-TIME
ACCELERATOR
±15kV ESD Protection
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
The I/O VCC_ lines have extra protection against static
discharge. Maxim’s engineers have developed state-ofthe-art structures to protect these pins against ESD of
±15kV without damage. The ESD structures withstand
high ESD in all states: normal operation, tri-state output
mode, and powered down. After an ESD event, Maxim’s
E versions keep working without latchup, whereas competing products can latch and must be powered down
to remove the latchup condition.
RISE-TIME
ACCELERATOR
FALL-TIME
ACCELERATOR
MAX13101E
MAX13102E
MAX13103E
MAX13108E
ESD protection can be tested in various ways. The
I/O V CC _ lines of the MAX13101E/ MAX13102E/
MAX13103E/MAX13108E are characterized for protection to ±15kV using the Human Body Model.
Figure 6. Simplified Diagram (1 I/O Line)
MULT
I/O VL1
I/O VL2
PORT A
I/O VCC1
I/O VCC2
I/O VL3
I/O VCC3
I/O VL4
I/O VL5
I/O VL6
I/O VCC4
I/O VCC5
I/O VCC6
I/O VL7
I/O VCC7
I/O VL8
I/O VCC8
MAX13108E
PORT B
I/O VL9
I/O VCC9
I/O VL10
I/O VL11
I/O VCC10
I/O VCC11
I/O VL12
I/O VL13
I/O VL14
I/O VCC12
I/O VCC13
I/O VCC14
I/O VL15
I/O VL16
I/O VCC15
I/O VCC16
Figure 7. MAX13108E Multiplexing Configuration
14
______________________________________________________________________________________
16-Channel Buffered CMOS
Logic-Level Translators
CHARGE-CURRENTLIMIT RESISTOR
HIGHVOLTAGE
DC
SOURCE
CS
100pF
RD 1500Ω
IP 100%
90%
DISCHARGE
RESISTANCE
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
AMPERES
STORAGE
CAPACITOR
DEVICE
UNDER
TEST
36.8%
10%
0
0
tRL
TIME
tDL
CURRENT WAVEFORM
Figure 8a. Human Body ESD Test Model
Figure 8b. Human Body Model Current Waveform
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report that documents
test setup, test methodology, and test results.
Human Body Model
Figure 8a shows the Human Body Model and Figure 8b
shows the current waveform it generates when discharged into a low impedance. This model consists of
a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device
through a 1.5kΩ resistor.
Machine Model
The Machine Model for ESD tests all pins using a
200pF storage capacitor and zero discharge resistance. Its objective is to emulate the stress caused by
contact that occurs with handling and assembly during
manufacturing. All pins require this protection during
manufacturing, not just inputs and outputs. Therefore,
after PC board assembly, the Machine Model is less
relevant to I/O ports.
Applications Information
Power-Supply Decoupling
To reduce ripple and the chance of transmitting incorrect data, bypass VL and VCC to ground with 0.1µF
capacitors. To ensure full ±15kV ESD protection,
bypass VCC to ground with a 1µF ceramic capacitor.
Place all capacitors as close to the power-supply inputs
as possible.
Capacitive Loading
Capacitive loading on the I/O lines impacts the rise time
(and fall time) of the MAX13101E/MAX13102E/
MAX13103E/MAX13108E when driving the signal lines.
The actual rise time is a function of the parasitic capacitance, the supply voltage, and the drive impedance of
the MAX13101E/MAX13102E/MAX13103E/MAX13108E.
For proper operation, the signal must reach the VOH as
required before the rise-time accelerators turn off.
______________________________________________________________________________________
15
MAX13101E/MAX13102E/MAX13103E/MAX13108E
RC 1MΩ
Ordering Information/Selector Guide (continued)
PART
PIN-PACKAGE
DATA
RATE (Mbps)
I/O VL STATE
DURING SHUTDOWN
I/O VCC STATE
DURING SHUTDOWN
MULTIPLEXER
FEATURE
MAX13102EEWX+
36 WLP**
3.06mm x 3.06mm
20
6kΩ to GND
High impedance
No
MAX13102EETL+
40 TQFN-EP***
5mm x 5mm x 0.8mm
20
6kΩ to GND
High impedance
No
MAX13103EEWX+
36 WLP**
3.06mm x 3.06mm
20
High impedance
High impedance
No
MAX13103EETL+
40 TQFN-EP***
5mm x 5mm x 0.8mm
20
High impedance
High impedance
No
MAX13108EEWX+
36 WLP**
3.06mm x 3.06mm
20
High impedance
High impedance
Yes
MAX13108EETL+
40 TQFN-EP***
5mm x 5mm x 0.8mm
20
High impedance
High impedance
Yes
Note: All devices are specified over the -40°C to +85°C operating temperature range.
+Denotes a lead-free/RoHS-compliant package.
**WLP bumps are in a 6 x 6 array.
***EP = Exposed pad.
Pin Configurations (continued)
GND
I/O VCC5
I/O VCC6
I/O VCC7
I/O VCC8
I/O VCC9
I/O VCC10
I/O VCC11
I/O VCC12
GND
TOP VIEW OF BOTTOM LEADS
30
29
28
27
26
25
24
23
22
21
I/O VCC4
31
20 I/O VCC13
I/O VCC3
32
19 I/O VCC14
I/O VCC2
33
18 I/O VCC15
I/O VCC1
34
17 I/O VCC16
VCC
35
16 VCC
MA131018E
VL
36
15 VL
I/O VL1
37
14 I/O VL16
I/O VL2
38
I/O VL3
39
6
7
8
9
10
I/O VL12
MULT
5
I/O VL11
4
I/O VL9
3
I/O VL10
2
I/O VL8
GND
1
11 I/O VL13
I/O VL7
40
12 I/O VL14
+
I/O VL6
I/O VL4
13 I/O VL15
*EP
I/O VL5
MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
* EXPOSED PAD CONNECTED TO GROUND
TQFN
16
______________________________________________________________________________________
16-Channel Buffered CMOS
Logic-Level Translators
MAX13108E
MAX13101E/MAX13102E/MAX13103E
1
2
3
4
5
6
VCC
I/O VCC3
I/O VCC6
I/O VCC9
I/O VCC12 I/O VCC15
I/O VCC1
I/O VCC4
I/O VCC7
I/O VCC10
I/O VCC13 I/O VCC16
I/O VCC2
I/O VCC5
I/O VCC8
I/O VCC11
I/O VCC14
GND
I/O VL2
I/O VL5
I/O VL8
I/O VL11
I/O VL14
EN
I/O VL1
I/O VL4
I/O VL7
I/O VL10
I/O VL13
I/O VL16
I/O VL3
I/O VL6
I/O VL9
I/O VL12
I/O VL15
F
1
2
3
4
5
6
VCC
I/O VCC3
I/O VCC6
I/O VCC9
I/O VCC12 I/O VCC15
I/O VCC1
I/O VCC4
I/O VCC7
I/O VCC10
I/O VCC13 I/O VCC16
I/O VCC2
I/O VCC5
I/O VCC8
I/O VCC11
I/O VCC14
GND
I/O VL2
I/O VL5
I/O VL8
I/O VL11
I/O VL14
MULT
I/O VL1
I/O VL4
I/O VL7
I/O VL10
I/O VL13
I/O VL16
I/O VL3
I/O VL6
I/O VL9
I/O VL12
I/O VL15
F
E
E
D
D
C
C
B
B
A
A
+ VL
+ VL
WLP
(BOTTOM VIEW)
WLP
(BOTTOM VIEW)
Typical Operating Circuit
Chip Information
PROCESS: BiCMOS
+1.8V
+3.3V
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
VCC
VL
EN/(MULT)
MAX13101E
MAX13102E
MAX13103E
MAX13108E
+1.8V
SYSTEM
CONTROLLER
DATA
I/O VL_
I/O VCC_
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
36 WLP
W363A3-1
21-0024
40 TQFN-EP
T4055-1
21-0140
+3.3V
SYSTEM
DATA
GND
( ) ARE FOR MAX13108E
______________________________________________________________________________________
17
MAX13101E/MAX13102E/MAX13103E/MAX13108E
Pin Configurations (continued)
MAX13101E/MAX13102E/MAX13103E/MAX13108E
16-Channel Buffered CMOS
Logic-Level Translators
Revision History
REVISION
NUMBER
REVISION
DATE
2
8/06
3
6/08
DESCRIPTION
Release of the MAX13101EETL+
Changed UCSP to WLP packaging
PAGES
CHANGED
—
1, 2, 9, 10, 11, 16,
17, 18, 19
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.