4 A Dual-Channel Gate Driver ADuM3220 FEATURES GENERAL DESCRIPTION 4 A peak output current Precise timing characteristics 60 ns maximum isolator and driver propagation delay 5 ns maximum channel-to-channel matching High junction temperature operation: 125°C 3.3 V to 5 V input logic 4.5 V to 18 V output drive UVLO at 2.5 V VDD1 and 4.1 V VDD2 Thermal shutdown protection at >150°C Output shoot-through logic protection Default low output High frequency operation: dc to 1 MHz CMOS input logic levels High common-mode transient immunity: >25 kV/μs Enhanced system-level ESD performance per IEC 61000-4-x UL 1577 2500 V rms input-to-output withstand voltage (pending) Small footprint and low profile Narrow body, RoHS-compliant, 8-lead SOIC 5 mm × 6 mm × 1.6 mm The ADuM32201 is a 4 A isolated, dual-channel gate driver based on the Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic transformer technology, this isolation component provides outstanding performance characteristics superior to the alternatives, such as the combination of pulse transformers and gate drivers. The ADuM3220 isolator provides two independent isolation channels. It has a maximum propagation delay of 60 ns and 5 ns channel-to-channel matching. In comparison to gate drivers employing high voltage level translation methodologies, the ADuM3220 offers the benefit of true, galvanic isolation between the input and each output, enabling voltage translation across the isolation barrier. The ADuM3220 has shoot-through protection logic and a default output low characteristic as required for gate drive applications. It operates with an input supply voltage ranging from 3.0 V to 5.5 V, providing compatibility with lower voltage systems. The outputs may be operated at supply voltages from 5 V to 18 V, which supports typical gate drive voltages for synchronous dc/dc converters. The ADuM3220 isolator contains various circuit and layout enhancements to provide increased capability relative to system-level IEC 61000-4-x testing (ESD, burst, and surge). The precise capability in these tests is strongly determined by the design and layout of the user’s board or module. For more information, see the AN-793 Application Note, ESD/Latch-Up Considerations with iCoupler Isolation Products. APPLICATIONS Isolated synchronous dc/dc converters MOSFET/IGBT gate drivers The ADuM3220 specifies the junction temperature from −40°C to 125°C. VDD1 1 ADuM3220 VIA 2 ENCODE DECODE AND LEVEL SHIFT VIB 3 ENCODE DECODE AND LEVEL SHIFT GND1 4 8 VDD2 7 VOA 6 VOB 5 GND2 08994-001 FUNCTIONAL BLOCK DIAGRAM Figure 1. 1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,239. Other patents pending. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. ADuM3220 TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................7 Applications ....................................................................................... 1 ESD Caution...................................................................................7 General Description ......................................................................... 1 Pin Configuration and Function Descriptions..............................8 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................9 Revision History ............................................................................... 2 Applications Information .............................................................. 11 Specifications..................................................................................... 3 PC Board Layout ........................................................................ 11 Electrical Characteristics—5 V Operation................................ 3 Propagation Delay-Related Parameters ................................... 11 Electrical Characteristics—3.3 V Operation ............................. 4 Thermal Limitations and Switch Load Characteristics ......... 11 Package Characteristics ............................................................... 5 Output Load Characteristics ..................................................... 11 Regulatory Information ............................................................... 5 DC Correctness and Magnetic Field Immunity........................... 12 Insulation and Safety-Related Specifications ............................ 5 Power Consumption .................................................................. 13 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics .............................................................................. 6 Insulation Lifetime ..................................................................... 13 Outline Dimensions ....................................................................... 14 Recommended Operating Conditions ...................................... 6 Ordering Guide .......................................................................... 14 REVISION HISTORY 4/10—Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADuM3220 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V OPERATION All voltages are relative to their respective ground. 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/ maximum specifications apply over TJ = −40°C to 125°C. All typical specifications are at TJ = 25°C, VDD1 = 5 V, VDD2 = 10 V. Switching specifications are tested with CMOS signal levels. Table 1. Parameter DC SPECIFICATIONS Input Supply Current, Two Channels, Quiescent Output Supply Current, Two Channels, Quiescent Total Supply Current, Two Channels 1 DC to 1 MHz VDD1 Supply Current VDD2 Supply Current Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages Undervoltage Lockout, VDD2 Supply Positive-Going Threshold Negative-Going Threshold Hysteresis Output Short-Circuit Pulsed Current 2 SWITCHING SPECIFICATIONS Pulse Width 3 Data Rate 4 Propagation Delay 5 Propagation Delay Skew 6 Channel-to-Channel Matching 7 Channel-to-Channel Matching6 Output Rise/Fall Time (10% to 90%) Dynamic Input Supply Current per Channel Dynamic Output Supply Current per Channel Refresh Rate Symbol Min Typ Max Unit IDDI(Q) IDDO(Q) 1.2 4.7 1.5 10 mA mA IDD1(Q) IDD2(Q) IIA, IIB VIH VIL VOAH, VOAH VOAL, VOBL 1.4 11 +0.01 1.7 17 +10 mA mA μA V V V V −10 0.7 × VDD1 0.3 × VDD1 VDD2 − 0.1 VDD2UV+ VDD2UV− VDD2UVH IOA(SC), IOB(SC) 3.7 3.2 PW 100 tDLH, tDHL tDLH, tDHL tPSK tPSKCD tPSKCD tR/tF tR/tF IDDI(D) IDDO(D) fr 2.0 35 36 14 14 VDD2 0.0 4.1 3.7 0.4 4.0 45 50 1 1 20 22 0.05 1.5 1.2 1 0.15 4.4 4.1 1 60 68 12 5 7 25 28 V V V A ns MHz ns ns ns ns ns ns ns ns ns Mbps Test Conditions DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 0 ≤ VIA, VIB ≤ VDD1 IOx = −20 mA, VIx = VIxH IOx = +20 mA, VIx = VIxL VDD2 = 10 V CL = 2 nF, V DD2 = 10 V CL = 2 nF, V DD2 = 10 V CL = 2 nF, V DD2 = 10 V; see Figure 17 CL = 2 nF, V DD2 = 4.5 V; see Figure 17 CL = 2 nF, V DD2 = 10 V; see Figure 17 CL = 2 nF, V DD2 = 10 V; see Figure 17 CL = 2 nF, V DD2 = 4.5 V; see Figure 17 CL = 2 nF, V DD2 = 10 V; see Figure 17 CL = 2 nF, V DD2 = 4.5 V; see Figure 17 VDD2 = 10 V VDD2 = 10 V The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 and Figure 9 for total VDD1 and VDD2 supply currents as a function of data rate. 2 Short-circuit duration less than 1 μs. Average power must conform to the limit shown under the Absolute Maximum Ratings. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 TDHL propagation delay is measured from the 90% level of the rising edge of the VIx signal to the 10% level of the rising edge of the VOx signal. TDHL propagation delay is measured from the 10% level of the falling edge of the VIx signal to the 90% level of the falling edge of the VOx signal. See Figure 17 for waveforms of propagation delay parameters. 6 tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. See Figure 17 for waveforms of propagation delay parameters. 7 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Rev. 0 | Page 3 of 16 ADuM3220 ELECTRICAL CHARACTERISTICS—3.3 V OPERATION All voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 18 V, unless stated otherwise. All minimum/ maximum specifications apply over TJ = −40°C to 125°C. All typical specifications are at TJ = 25°C, VDD1 = 3.3 V, VDD2 = 10 V. Switching specifications are tested with CMOS signal levels. Table 2. Parameter DC SPECIFICATIONS Input Supply Current, Two Channels, Quiescent Output Supply Current, Two Channels, Quiescent Total Supply Current, Two Channels 1 DC to 1 MHz VDD1 Supply Current Symbol VDD2 Supply Current Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages Undervoltage Lockout, VDD2 Supply Positive Going Threshold Negative Going Threshold Hysteresis Output Short-Circuit Pulsed Current 2 SWITCHING SPECIFICATIONS Pulse Width 3 Data Rate 4 Propagation Delay 5 IDD2(Q) IIA, IIB VIH VIL VOAH, VOAH VOAL, VOBL Propagation Delay Skew 6 Channel-to-Channel Matching 7 Output Rise/Fall Time (10% to 90%) Dynamic Input Supply Current per Channel Dynamic Output Supply Current per Channel Refresh Rate Min Typ Max Unit IDDI(Q) IDDO(Q) 0.7 4.7 1.0 10 mA mA IDD1(Q) 0.8 1.0 mA 11 +0.01 17 +10 mA μA V V V V −10 0.7 × VDD1 0.3 × VDD1 VDD2 − 0.1 VDD2UV+ 3.7 VDD2UV− 3.2 VDD2UVH IOA(SC), IOB(SC) 2.0 PW tDLH, tDHL tDLH, tDHL tPSK tPSKCD tPSKCD tR/tF tR/tF IDDI(D) IDDO(D) fr VDD2 0.0 4.1 3.7 0.4 4.0 0.15 4.4 4.1 100 36 37 14 14 48 53 1 1 20 22 0.025 1.5 1.1 1 1 62 72 12 5 7 25 28 V V V A ns MHz ns ns ns ns ns ns ns mA/Mbps mA/Mbps Mbps Test Conditions DC to 1 MHz logic signal frequency DC to 1 MHz logic signal frequency 0 ≤ VIA, VIB ≤ VDD1 IOx = −20 mA, VIx = VIxH IOx = +20 mA, VIx = VIxL VDD2 = 10 V CL = 2 nF, VDD2 = 10 V CL = 2 nF, VDD2 = 10 V CL = 2 nF, VDD2 = 10 V; see Figure 17 CL = 2 nF, VDD2 = 4.5 V; see Figure 17 CL = 2 nF, VDD2 = 10 V; see Figure 17 CL = 2 nF, VDD2 = 10 V; see Figure 17 CL = 2 nF, VDD2 = 4.5 V; see Figure 17 CL = 2 nF, VDD2 = 10 V; see Figure 17 CL = 2 nF, VDD2 = 4.5 V; see Figure 17 VDD2 = 10 V VDD2 = 10 V The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See Figure 8 and Figure 9 for total VDD1 and VDD2 supply currents as a function of data rate. 2 Short-circuit duration less than 1 μs. Average power must conform to the limit shown under the .Absolute Maximum Ratings. 3 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 5 TDLH propagation delay is measured from the 90% level of the rising edge of the VIx signal to the 10% level of the rising edge of the VOx signal. tDHL propagation delay is measured from the 10% level of the falling edge of the VIx signal to the 90% level of the falling edge of the VOx signal. See Figure 17 for waveforms of propagation delay parameters. 6 tPSK is the magnitude of the worst-case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. See Figure 17 for waveforms of propagation delay parameters. 7 Channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier. Rev. 0 | Page 4 of 16 ADuM3220 PACKAGE CHARACTERISTICS Table 3. Parameter Resistance (Input-to-Output) 1 Capacitance (Input-to-Output)1 Input Capacitance IC Junction-to-Case Thermal Resistance, Side 1 Symbol RI-O CI-O CI θJCI IC Junction-to-Case Thermal Resistance, Side 2 θJCO 1 Min Typ 1012 1.0 4.0 46 Max 41 Unit Ω pF pF °C/W °C/W Test Conditions f = 1 MHz Thermocouple located at center of package underside Thermocouple located at center of package underside The device is considered a 2-terminal device; Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together. REGULATORY INFORMATION The ADuM3220 approval is pending by the organizations listed in Table 4. Table 4. UL Recognized under UL 1577 Component Recognition Program 1 Single/Basic 2500 V rms Isolation Voltage File E214100 1 2 CSA Approved under CSA Component Acceptance Notice #5A VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 2 Basic insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage Functional insulation per CSA 60950-1-03 and IEC 60950-1, 800 V rms(1131 V peak) maximum working voltage File 205078 Reinforced insulation, 560 V peak File 2471900-4880-0001 In accordance with UL 1577, each ADuM3220 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (current leakage detection limit = 5 μA). In accordance with DIN V VDE V 0884-10, each ADuM3220 is proof tested by applying an insulation test voltage ≥ 1050 V peak for 1 second (partial discharge detection limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 5. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 2500 4.90 min Unit V rms mm Minimum External Tracking (Creepage) L(I02) 4.01 min mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.017 min >175 IIIa mm V Rev. 0 | Page 5 of 16 Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) ADuM3220 DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage. Table 6. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety-Limiting Values Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS Conditions Symbol VIORM × 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VIO = 500 V 200 Unit I to IV I to III I to II 40/105/21 2 560 1050 V peak V peak 896 672 V peak V peak VTR 4000 V peak TS IS1 IS2 RS 150 160 47 >109 °C mA mA Ω VIORM VPR VPR VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 sec Maximum value allowed in the event of a failure (see Figure 2) Characteristic RECOMMENDED OPERATING CONDITIONS SAFETY-LIMITING CURRENT (mA) 180 Table 7. 160 Parameter Symbol Operating Junction Temperature TJ Supply Voltages 1 VDD1 VDD2 VDD1 Rise Time TVDD1 Common-Mode Transient Immunity, Input to Output Input Signal Rise and Fall Times 140 SIDE #1 120 100 80 60 SIDE #2 40 Min −40 3.0 4.5 −25 Max +125 5.5 18 1 +25 Unit °C V V V/µs kV/µs 1 ms 20 0 50 100 150 CASE TEMPERATURE (°C) 200 06866-002 1 0 All voltages are relative to their respective ground. See the DC Correctness and Magnetic Field Immunity section for information on immunity to external magnetic fields. Figure 2. Thermal Derating Curve; Dependence of Safety-Limiting Values on Case Temperature, per DIN V VDE V 0884-10. Safety-limiting current is defined as the average current at maximum VDD. Rev. 0 | Page 6 of 16 ADuM3220 ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Table 9. Maximum Continuous Working Voltage1 Table 8. Parameter Storage Temperature Operating Temperature Supply Voltage Ranges1 Input Voltage Range1, 2 Output Voltage Range1, 2 Average Output Current, per Pin3 Common-Mode Transients4 Symbol TST TA VDD1 VDD2 VIA, VIB VOA, VOB IO Rating −55°C to +150°C −40°C to +125°C −0.5 V to +7.0 V −0.5 V to +27 V −0.5 V to VDDI + 0.5 −0.5 to VDDO + 0.5 −23 mA to +23 mA Parameter AC Bipolar Voltage2 AC Unipolar Voltage3 Functional Insulation CMH, CML −100 kV/μs to +100 kV/μs DC Voltage4 Functional Insulation Basic Insulation 1 All voltages are relative to their respective ground. VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. 3 See Figure 2 for information on maximum allowable current for various temperatures. 4 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the Absolute Maximum Rating can cause latch-up or permanent damage. Max 565 Unit V peak Constraint 50-year minimum lifetime 1131 V peak 560 V peak Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 1131 V peak 560 V peak 2 Basic Insulation 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. 2 See Figure 21. 3 See Figure 22. 4 See Figure 23. ESD CAUTION Rev. 0 | Page 7 of 16 ADuM3220 VDD1 1 VIA 2 ADuM3220 8 VDD2 7 VOA VIB 3 6 VOB TOP VIEW GND1 4 (Not to Scale) 5 GND2 08994-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 10. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic VDD1 VIA VIB GND1 GND2 VOB VOA VDD2 Description Supply Voltage for Isolator Side 1, 3.0 V to 5.5 V. Logic Input A. Logic Input B. Ground 1. Ground reference for Isolator Side 1. Ground 2. Ground reference for Isolator Side 2. Logic Output B. Logic Output A. Supply Voltage for Isolator Side 2, 7 V to 18 V. Table 11. Truth Table (Positive Logic) VIA Input L L H H X VIB Input L H L H X VDD1 State Powered Powered Powered Powered Unpowered VDD2 State Powered Powered Powered Powered Powered VOA Output L L H L L VOB Output L H L L L X X Powered Unpowered Indeterminate Indeterminate Rev. 0 | Page 8 of 16 Notes Outputs return to the input state within 1 μs of VDDI power restoration. Outputs return to the input state within 1 μs of VDDO power restoration. ADuM3220 TYPICAL PERFORMANCE CHARACTERISTICS 600 500 GATE CHARGE (nC) CH2 = VO (2V/DIV) 2 400 300 VDD2 VDD2 VDD2 VDD2 200 CH1 = VI (5V/DIV) 100 = 5V = 8V = 10V = 15V CH2 2V Ω M40ns T 22.2% 2.5GSPS CH2 10k POINTS 7.2V 0 0 0.5 1.0 1.5 2.0 SWITCHING FREQUENCY (MHz) 08994-014 CH1 5V Ω 08994-004 1 Figure 7. Typical Maximum Load vs. Switching Frequency (RG = 1 Ω) Figure 4. Output Waveform for 2 nF Load with10 V Output Supply 2.0 CH2 = VO (2V/DIV) IDD1 CURRENT (mA) 1.5 2 CH1 = VI (5V/DIV) VDD1 = 5V 1.0 VDD1 = 3.3V 0.5 CH2 2V Ω M40ns T 21.4% 2.5GSPS CH2 10k POINTS 7.2V 0 08994-005 CH1 5V Ω 0 0.25 0.50 0.75 1.00 FREQUENCY(MHz) 08994-015 1 Figure 8. Typical IDD1 Supply Current vs. Frequency Figure 5. Output Waveform for 1 nF Load with10 V Output Supply 80 VDD2 = 15V 70 CH2 = VO (2V/DIV) IDD2 CURRENT (mA) 60 2 CH1 = VI (5V/DIV) VDD2 = 10V 50 40 30 VDD2 = 5V 20 CH2 2V Ω M40ns T 22.1% 2.5GSPS CH2 10k POINTS 7.2V 0 08994-006 CH1 5V Ω 0 0.25 0.50 0.75 1.00 FREQUENCY(MHz) Figure 6. Output Waveform for 1 nF Load with 5 Ω Series Resistance and 10 V Output Supply Rev. 0 | Page 9 of 16 Figure 9. Typical IDD2 Supply Current vs. Frequency with 2 nF Load 08994-016 10 1 60 30 50 25 RISE/FALL TIME (ns) 40 30 20 20 RISE TIME 10 5 10 20 40 60 80 100 120 140 JUNCTION TEMPERATURE (°C) 0 Figure 10. Typical Propagation Delay vs. Temperature 5 PROPAGATION DELAY CHANNEL-TO-CHANNEL MATCHING (ns) PROPAGATION DELAY (ns) tPHL 30 20 3.5 4.0 4.5 5.0 5.5 INPUT SUPPLY VOLTAGE (V) 08994-018 10 0 3.0 Figure 11. Typical Propagation Delay vs. Input Supply Voltage, VDD2 = 10 V tPHL tPLH 40 30 20 10 5 7 9 11 13 OUTPUT SUPPLY VOLTAGE (V) 15 17 15 17 4 3 2 PD MATCH tDLH 1 PD MATCH tDHL 0 7 9 11 13 15 Figure 14. Typical Propagation Delay Channel-to-Channel Matching vs. Output Supply Voltage 5 4 3 2 PD MATCH tDLH 1 PD MATCH tDHL 0 –40 –20 0 20 40 60 80 100 JUNCTION TEMPERATURE (°C) Figure 12. Typical Propagation Delay vs. Output Supply Voltage, VDD1 = 5 V 17 OUTPUT SUPPLY VOLTAGE (V) 08994-019 0 13 5 5 PROPAGATION DELAY CHANNEL-TO-CHANNEL MATCHING (ns) 60 50 11 Figure 13. Typical Rise/Fall Time Variation vs. Output Supply Voltage tPLH 40 9 OUTPUT SUPPLY VOLTAGE (V) 60 50 7 08994-020 0 08994-021 –20 08994-017 0 –40 PROPAGATION DELAY (ns) FALL TIME 15 120 140 08994-022 PROPAGATION DELAY (ns) ADuM3220 Figure 15. Typical Propagation Delay Channel-to-Channel Matching vs. Temperature, VDD2 = 10 V Rev. 0 | Page 10 of 16 ADuM3220 APPLICATIONS INFORMATION PC BOARD LAYOUT The ADuM3220 digital isolator requires no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins, as shown in Figure 16. Use a small ceramic capacitor with a value between 0.01 μF and 0.1 μF to provide a good high frequency bypass. On the output power supply pin, VDD2 it is recommended to also add a 10 μF value to provide the charge required to drive the gate capacitance at the ADuM3220 outputs. On the output supply pins, the bypass capacitors use of vias should be avoided or multiple vias should be employed to reduce the inductance in the bypassing. The total lead length between both ends of the smaller capacitor and the input or output power supply pin should not exceed 20 mm. VDD1 VIA VOA VIB VOB GND1 GND2 08994-023 VDD2 Figure 16. Recommended PCB Layout PROPAGATION DELAY-RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output can differ from the propagation delay to a logic high output. The ADuM3220 specifies tDLH (see Figure 17) as the time between the rising input high logic threshold, VIH, to the output rising 10% threshold. Likewise, the falling propagation delay, tDHL, is defined as the time between the input falling logic low threshold, VIL, and the output falling 90% threshold. The rise and fall times are dependent on the loading conditions and are not included in the propagation delay, as is the industry standard for gate drivers. THERMAL LIMITATIONS AND SWITCH LOAD CHARACTERISTICS For isolated gate drivers, the necessary separation between the input and output circuits prevents the use of a single thermal pad beneath the part, and heat is, therefore, dissipated mainly through the package pins. Package thermal dissipation limits the performance of switching frequency versus output load, as illustrated in Figure 7, for the maximum load capacitance that can be driven with a 1 Ω series gate resistance for different values of output voltage. For example, this curve shows that a typical ADuM3220 can drive a large MOSFET with 120 nC gate charge at 8 V output (which is equivalent to a 15 nF load) up to a frequency of about 300 kHz. OUTPUT LOAD CHARACTERISTICS The ADuM3220 output signals depend on the characteristics of the output load, which is typically an N-channel MOSFET. The driver output response to an N-channel MOSFET load can be modeled with a switch output resistance (Rsw), an inductance due to the printed circuit board trace (Ltrace), a series gate resistor (Rgate), and a gate to source capacitance (Cgs), as shown in Figure 18. RSW is the switch resistance of the internal ADuM3220 driver output, which is about 1.5 Ω. Rgate is the intrinsic gate resistance of the MOSFET and any external series resistance. A MOSFET that requires a 4 A gate driver would have a typical intrinsic gate resistance of about 1 Ω and a gate-to-source capacitance, Cgs, of between 2 nF and 10 nF. Ltrace is the inductance of the printed circuit board trace, typically a value of 5 nH or less for a well designed layout with a very short and wide connection from the ADuM3220 output to the gate of the MOSFET. The following equation defines the Q factor of the RLC circuit, which indicates how the ADuM3220 output responds to a step change. For a well damped output, Q is less than one. Adding a series gate resistance dampens the output response. 90% OUTPUT 10% Q= VIH L 1 × trace (Rsw + R gate ) C gs INPUT In Figure 4 and Figure 5, the ADuM3220 output waveforms for 10 V output are shown for a Cgs of 2 nF and 1 nF, respectively. Note the ringing of the output in Figure 5 with Cgs of 1 nF and a calculated Q factor of 1.5, where less than one is desired for good damping. VIL tR tF 08994-007 tDHL tDLH Figure 17. Propagation Delay Parameters Channel-to-channel matching refers to the maximum amount that the propagation delay differs between channels within a single ADuM3220 component. Propagation delay skew refers to the maximum amount that the propagation delay differs between multiple ADuM3220 components operating under the same conditions. Output ringing can be reduced by adding a series gate resistance to dampen the response. For applications using a 1 nF or less load, it is recommended to add a series gate resistor of about 5 Ω. As shown in Figure 6, Rgate is 5 Ω, which yields a calculated Q-factor of about 0.3, and illustrates a damped response in comparison with Figure 5. Rev. 0 | Page 11 of 16 ADuM3220 100 Figure 18. RLC Model of the Gate of an N-Channel MOSFET DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions of more than 2 μs at the input, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 μs, the input side is assumed to be unpowered or nonfunctional, in which case, the isolator output is forced to a default low state by the watchdog timer circuit. In addition, the outputs are in a low default state while the power is coming up before the UVLO threshold is crossed. The ADuM3220 is immune to external magnetic fields. The limitation on the ADuM3220 magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. The 3 V operating condition of the ADuM3220 is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (−dβ/dt) ∑π rn2, n = 1, 2, ... , N 10 1 0.1 0.01 0.001 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) 100M 08994-009 CGS Figure 19. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and had the worst-case polarity), the received pulse is reduced from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM3220 transformers. Figure 20 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM3220 is immune and only can be affected by extremely large currents operated at a high frequency and very close to the component. For the 1 MHz example, one would have to place a 0.5 kA current 5 mm away from the ADuM3220 to affect the component’s operation. 1000 where: β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM3220 and an imposed requirement that the induced voltage is at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 19. DISTANCE = 1m 100 10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1 0.01 1k 10k 100k 1M 10M MAGNETIC FIELD FREQUENCY (Hz) Figure 20. Maximum Allowable Current for Various Current-to-ADuM3220 Spacings Rev. 0 | Page 12 of 16 100M 08994-010 ADuM3220 VO MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss) LTRACE R GATE MAXIMUM ALLOWABLE CURRENT (kA) VOA RSW 08994-008 VIA ADuM3220 The supply current at a given channel of the ADuM3220 isolator is a function of the supply voltage, channel data rate, and channel output load. For each input channel, the supply current is given by IDDI = IDDI(Q) f ≤ 0.5fr IDDI = IDDI(D) × (2f – fr) + IDDI(Q) f > 0.5fr For each output channel, the supply current is given by f ≤ 0.5fr IDDO = (IDDO(D) + (0.5) × CLVDDO) × (2f – fr) + IDDO(Q) f > 0.5fr where: IDDI(D), IDDO(D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is the output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz, half of the input data rate, NRZ signaling). fr is the input stage refresh rate (Mbps). IDDI(Q), IDDO(Q) are the specified input and output quiescent supply currents (mA). To calculate the total IDD1 and IDD2 supply current, the supply currents for each input and output channel corresponding to IDD1 and IDD2 are calculated and totaled. Figure 8 provides total input IDD1 supply current as a function of data rate for both input channels. Figure 9 provides total IDD2 supply current as a function of data rate for both outputs loaded with 2 nF capacitance. The insulation lifetime of the ADuM3220 depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 21, Figure 22, and Figure 23 illustrate these different isolation voltage waveforms. A bipolar ac voltage environment is the worst case for the iCoupler products and is also the 50-year operating lifetime that Analog Devices recommends for maximum working voltage. In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. Any cross-insulation voltage waveform that does not conform to Figure 22 or Figure 23 should be treated as a bipolar ac waveform, and its peak voltage should be limited to the 50-year lifetime voltage value listed in Table 9. Note that the voltage presented in Figure 22 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V. RATED PEAK VOLTAGE 0V Figure 21. Bipolar AC Waveform INSULATION LIFETIME Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. Rev. 0 | Page 13 of 16 RATED PEAK VOLTAGE 08994-012 All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM3220. 0V Figure 22. Unipolar AC Waveform RATED PEAK VOLTAGE 08994-013 IDDO = IDDO(Q) The values shown in Table 9 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. 08994-011 POWER CONSUMPTION 0V Figure 23. DC Waveform ADuM3220 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 012407-A 8 4.00 (0.1574) 3.80 (0.1497) Figure 24. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters (inches) ORDERING GUIDE Model 1 ADuM3220ARZ ADuM3220ARZ-RL7 1 No. of Inputs, VDD1 Side 2 2 No. of Inputs, VDD2 Side 0 0 Maximum Data Rate (Mbps) 1 1 Maximum Propagation Delay, 5 V (ns) 60 60 Maximum Channel-to- Channel Matching (ns) 5 5 Z = RoHS Compliant Part. Rev. 0 | Page 14 of 16 Junction Temperature Range −40°C to 125°C −40°C to 125°C Package Description 8-Lead SOIC_N 8-Lead SOIC_N Package Option R-8 R-8 ADuM3220 NOTES Rev. 0 | Page 15 of 16 ADuM3220 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08994-0-4/10(0) Rev. 0 | Page 16 of 16