19-3692; Rev 1; 5/11 Ultra-Low-Voltage Level Translators The MAX13000E–MAX13005E 6-channel level translators provide the level shifting necessary to allow data transfer in multivoltage systems. Externally applied voltages, VCC and VL, set the logic levels on either side of the device. Logic signals present on the VL side of the device appear as higher voltage logic signals on the VCC side of the device, and vice-versa. The MAX13000E–MAX13005E feature a low VCC and VL quiescent supply current less than 4µA. The MAX13000E–MAX13005E also have ±15kV ESD protection on the I/O VCC side for greater protection in applications that route signals externally. The ESD protection is specified using the Human Body Model (HBM). The MAX13000E/MAX13001E/MAX13002E operate at a guaranteed 230kbps data rate. The MAX13003E/ MAX13004E/MAX13005E operate at a guaranteed 20Mbps data rate when VCC > +1.65V. The MAX13000E/MAX13003E are bidirectional level translators, allowing data translation in either direction (VL ↔ VCC) on any single data line without a DIRECTION input. The MAX13001E/MAX13002E/MAX13004E/ MAX13005E unidirectional level translators level shift data in one direction (VL → VCC or VCC → VL) on any single data line. The MAX13001E/MAX13002E/ MAX13004E/MAX13005E unidirectional translators’ inputs have the capability to interface with both CMOS and open-drain (OD) outputs. For more information see the Ordering Information, Selector Guide, and the InputDriver Requirements sections. The MAX13000E–MAX13005E operate with +0.9V to +3.6V VL voltages and +1.5V to +3.6V VCC voltages. The MAX13000E–MAX13005E are available in 16-bump UCSP™ and 16-pin TSSOP packages, and are specified over the extended -40°C to +85°C operating temperature range. Features ♦ Guaranteed Data-Rate Options 230kbps (MAX13000E/MAX13001E/MAX13002E) 20Mbps (MAX13003E/MAX13004E/MAX13005E) ♦ Bidirectional Level Translation Without a DIRECTION Input ♦ ♦ ♦ ♦ Operational Down to +0.9V on VL and +1.5V on VCC ±15kV ESD Protection on I/O VCC Lines per HBM Low <4µA Quiescent Current Enable/Shutdown Control ♦ 2mm x 2mm, 16-Bump UCSP and Lead Packaging Options ♦ CMOS or Open-Drain Outputs Interface Capability UCSP is a trademark of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc. MICROWIRE is a registered trademark of National Semiconductor Corp. Ordering Information PART MAX13000EEUE+ SPI™ and MICROWIRE® Level Translation Smart-Card Readers Portable POS Systems Portable Communication Devices Low-Cost Serial Interfaces Telecommunications Equipment PINPACKAGE -40°C to +85°C 16 TSSOP +Denotes a lead(Pb)-free/RoHS-compliant package. Ordering Information continued at end of data sheet. Pin Configurations BOTTOM VIEW MAX13000E/MAX13003E I/OVCC3 VCC GND I/OVCC4 I/OVCC1 I/OVCC2 I/OVCC5 I/OVCC6 I/OVL1 I/OVL2 I/OVL5 I/OVL6 I/OVL3 VL EN I/OVL4 1 2 3 4 D Applications CMOS Logic-Level Translation Open-Drain I/O Translation OD-to-CMOS Signal Conversion Low-Voltage ASIC Level Translation Cell Phones TEMP RANGE C B A 4 X 4 UCSP Pin Configurations continued at end of data sheet. Typical Operating Circuits and Selector Guide appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX13000E–MAX13005E General Description MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators ABSOLUTE MAXIMUM RATINGS Voltages referenced to GND. VCC ...........................................................................-0.3V to +4V VL ..............................................................................-0.3V to +4V I/OVCC_ .......................................................-0.3V to (VCC + 0.3V) I/OVL_ ............................................................-0.3V to (VL + 0.3V) EN .................................................................-0.3V to (VL + 0.3V) Short-Circuit Duration I/OVL_, I/OVCC_ to GND ..........Continuous Continuous Power Dissipation (TA = +70°C) 16-Pin TSSOP (derate 9.4mW/°C at +70°C) ................755mW 16-Bump UCSP (derate 8.2mW/°C at +70°C) .............659mW Operating Temperature Range ..........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4) PARAMETER VL Supply Range VCC Supply Range Supply Current from VCC (Note 3) SYMBOL VL VCC IQVCC MAX UNITS VL ≤ VCC (Note 2) CONDITIONS 0.9 VCC V (Note 2) 1.5 3.6 V 4 TA = +85°C 40 IQVL TA = +85°C VCC Shutdown Supply Current (Note 3) ISHDN-VCC TYP TA = +25°C TA = +25°C Supply Current from VL (Note 3) MIN (Note 3) 1 VL < VCC - 0.2V (Note 3) 5 2 4 VL < VCC - 0.2V 40 2 EN = GND, TA = +85°C 20 VL < VCC - 0.2V, EN = GND EN = GND VL Shutdown Supply Current (Note 3) TA = +85°C 1 4 VL < VCC - 0.2V, EN = GND 20 EN = GND 40 I/O VL_, I/O VCC_, EN = GND TA = +25°C 0.35 TA = +85°C 1 I/O Tri-Stated Output Leakage Current VL < VCC - 0.2V, I/O VL_, I/O VCC_, EN = GND TA = +25°C 0.2 TA = +85°C 0.5 2 µA 2 I/O Tri-State Output Leakage Current EN Input Leakage Current µA 20 EN = GND, TA = +25°C TA = +25°C µA µA µA µA TA = +25°C 0.35 TA = +85°C 1 _______________________________________________________________________________________ µA Ultra-Low-Voltage Level Translators (VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2/3 × VL V LOGIC-LEVEL THRESHOLDS I/OVL_ Input-Voltage-High Threshold VIHL I/OVL_ Input-Voltage-Low Threshold VILL I/OVCC_ Input-Voltage-High Threshold VIHC I/OVCC_ Input-Voltage-Low Threshold VILC EN Input-Voltage-High Threshold VIHEN EN Input-Voltage-Low Threshold VILEN I/OVL_ Output-Voltage High VOHL I/OVL_ Output-Voltage Low I/OVCC_ Output-Voltage High I/OVCC_ Output-Voltage Low VOLL VOHC VOLC 1/3 × VL V 2/3 × VCC 1/3 × VCC V 2/3 × VL I/OVL_ source current = 20µA V 1/3 × VL V VL 0.25 V MAX13002E/MAX13005E, OVL_ sink current = 1µA 0.3 MAX13000E/MAX13001E/MAX13003E/ MAX13004E, I/OVL_ sink current = 20µA 0.25 I/OVCC_ source current = 20µA V V VCC 0.25 V MAX13001E/MAX13004E, OVCC_ sink current = 1µA 0.3 MAX13000E/MAX13002E/MAX13003E/ MAX13005E, I/OVCC_ sink current = 20µA 0.25 V OUTPUT CURRENTS Output Sink Current During Transient (VCC Side) Output Sink Current During Transient (VL Side) VCC = +1.65V, MAX13003E/MAX13004E/MAX13005E 25 mA VCC = +1.65V, MAX13000E/MAX13001E/MAX13002E 1 VL = +1.2V, VCC = +1.65V, MAX13003E/MAX13004E/MAX13005E 30 VL = +1.2V, VCC = +1.65V, MAX13000E/MAX13001E/MAX13002E 1 mA _______________________________________________________________________________________ 3 MAX13000E–MAX13005E ELECTRICAL CHARACTERISTICS (continued) MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators ELECTRICAL CHARACTERISTICS (continued) (VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4) PARAMETER SYMBOL Output Source Current During Transient (VCC Side) CONDITIONS MIN TYP VCC = +1.65V, MAX13003E/MAX13004E/MAX13005E 22 VCC = +1.65V, MAX13000E/MAX13001E/MAX13002E 1 VL = +1.2V, VCC = +1.65V, MAX13003E/MAX13004E/MAX13005E 25 MAX UNITS mA Output Source Current During Transient (VL Side) mA VL = +1.2V, VCC = +1.65V, MAX13000E/MAX13001E/MAX13002E 1 ESD PROTECTION I/OVCC_ Human Body Model ±15 Air-Gap Discharge (IEC61000-4-2) ±10 Contact Discharge (IEC61000-4-2) ±8 kV TIMING CHARACTERISTICS (VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4) PARAMETER I/OVCC_ Rise Time SYMBOL tRVCC CONDITIONS tFVCC MAX 15 CI/OVCC = 50pF, MAX13003E/MAX13004E/MAX13005E, VCC = +1.5V, Figures 1a, 1b 15 400 15 CI/OVCC = 50pF, MAX13003E/MAX13004E/MAX13005E, VCC = +1.5V, Figures 1a, 1b 15 400 _______________________________________________________________________________________ UNITS ns 1400 CI/OVCC = 50pF, MAX13003E/MAX13004E/MAX13005E, VCC = +1.65V, Figures 1a, 1b CI/OVCC = 50pF, MAX13000E/MAX13001E/MAX13002E, Figures 1a, 1b 4 TYP CI/OVCC = 50pF, MAX13003E/MAX13004E/MAX13005E, VCC = +1.65V, Figures 1a, 1b CI/OVCC = 50pF, MAX13000E/MAX13001E/MAX13002E, Figures 1a, 1b I/OVCC_ Fall Time MIN 1400 ns Ultra-Low-Voltage Level Translators (VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4) PARAMETER I/OVL_ Rise Time SYMBOL tRVL CONDITIONS tFVL MAX 15 CI/OVL = 15pF, MAX13003E/MAX13004E/MAX13005E, VCC = +1.5V, Figures 2a, 2b 15 300 15 CI/OVL = 15pF, MAX13003E/MAX13004E/MAX13005E, VCC = +1.5V, Figures 2a, 2b 15 CI/OVCC = 50pF, MAX13003E/MAX13004E/MAX13005E, Figures 1a, 1b 300 I/OVCC-VL Propagation Delay from I/OVL to I/OVCC_ after EN (Note 5) ns ns 1200 20 ns I/OVL-VCC Propagation Delay (Driving I/OVCC_) UNITS 1200 CI/OVL = 50pF, MAX13003E/MAX13004E/MAX13005E, VCC = +1.65V, Figures 2a, 2b CI/OVL = 50pF, MAX13000E/MAX13001E/MAX13002E, Figures 2a, 2b Propagation Delay (Driving I/OVL_) TYP CI/OVL = 50pF, MAX13003E/MAX13004E/MAX13005E, VCC = +1.65V, Figures 2a, 2b CI/OVL = 50pF, MAX13000E/MAX13001E/MAX13002E, Figures 2a, 2b I/OVL_ Fall Time MIN CI/OVCC = 50pF, MAX13000E/MAX13001E/MAX13002E, Figures 1a, 1b 1000 VCC > +1.65V, CI/OVL = 50pF, MAX13003E/MAX13004E/MAX13005E, Figures 2a, 2b 20 VCC = 1.5V, CI/OVL = 15pF, MAX13003E/MAX13004E/MAX13005E, Figures 2a, 2b 20 CI/OVL = 50pF, MAX13000E/MAX13001E/MAX13002E, Figures 2a, 2b 1000 CI/OVCC = 50pF, CMOS output, Figure 3 2 CI/OVCC = 50pF, OD output, Figure 3 6 ns µs tEN-VCC _______________________________________________________________________________________ 5 MAX13000E–MAX13005E TIMING CHARACTERISTICS (continued) TIMING CHARACTERISTICS (continued) (VCC = +1.5V to +3.6V, VL = +0.9V to VCC, CI/OVL ≤ 15pF, CI/OVCC ≤ 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.) (Notes 1, 4) PARAMETER SYMBOL Propagation Delay from I/OVCC to I/OVL after EN (Note 5) CONDITIONS MIN TYP MAX CI/OVL = 50pF, CMOS output, Figure 4 2 CI/OVL = 50pF, OD output, Figure 4 6 tSKEW Part-to-Part Skew (Note 6) UNITS µs tEN-VL Channel-to-Channel Skew Each translator equally loaded, MAX13003E/MAX13004E/MAX13005E ±5 Each translator equally loaded, MAX13000E/MAX13001E/MAX13002E ±250 CI/OVL = 15pF, CI/OVCC = 15pF, VL = +1.8V, VCC = +2V, ΔT = +5°C, MAX13003E/MAX13004E/MAX13005E 10 ns tPPSKEW Maximum Data Rate ns MAX13003E/MAX13004E/MAX13005E VCC > +1.65V, CI/OVL = 50pF, CI/OVCC = 50pF 20 Mbps MAX13000E/MAX13001E/MAX13002E CI/OVL = 50pF, CI/OVCC = 50pF 230 kbps Note 1: All devices are 100% production tested at TA = +25°C. Limits are guaranteed by design over the entire temperature range. Note 2: VL must be less than or equal to VCC during normal operation. However, VL can be greater than VCC during startup and shutdown conditions. Note 3: This consumption is referred to as no signal transmission. Note 4: Guaranteed by design with an input signal full swing, rise/fall time ≤ 3ns, source resistance is 50Ω. Note 5: Enable input signal full swing and rise/fall time ≤ 50ns. Note 6: Guaranteed by design, not production tested. Typical Operating Characteristics (VCC = +3.3V, VL = +0.9V, TA = +25°C, MAX13003E.) 10 DATA RATE = 230kbps 1 0.1 0.1 0.01 DATA RATE = 230kbps 1.8 2.1 2.4 2.7 3.0 SUPPLY VOLTAGE (V) 3.3 3.6 DATA RATE = 20Mbps 1 0.1 DATA RATE = 230kbps 0.01 0.001 1.5 6 DATA RATE = 20Mbps 10 VCC SUPPLY CURRENT (mA) 100 MAX13000Etoc02 DATA RATE = 20Mbps 1 VL SUPPLY CURRENT (mA) MAX13000Etoc01 1000 VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE (DRIVING I/O VL, VL = 0.9V) VL SUPPLY CURRENT vs. SUPPLY VOLTAGE (DRIVING I/O VCC, VL = 0.9V) MAX13000Etoc03 VL SUPPLY CURRENT vs. SUPPLY VOLTAGE (DRIVING I/O VL, VL = 0.9V) VL SUPPLY CURRENT (μA) MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators 1.5 1.8 2.1 2.4 2.7 3.0 SUPPLY VOLTAGE (V) 3.3 3.6 1.5 1.8 2.1 2.4 2.7 3.0 SUPPLY VOLTAGE (V) _______________________________________________________________________________________ 3.3 3.6 Ultra-Low-Voltage Level Translators VL SUPPLY CURRENT vs. TEMPERATURE (DRIVING I/OVCC, VCC = +3.3V, VL = +0.9V) 0.1 DATA RATE = 230kbps 0.01 MAX13000E toc05 310 DATA RATE = 20Mbps 1.8 2.1 2.4 2.7 3.0 3.3 DATA RATE = 20Mbps 4.00 3.95 3.85 -40 3.6 4.05 3.90 290 1.5 -15 10 35 60 85 -40 -15 10 35 85 60 TEMPERATURE (°C) TEMPERATURE (°C) VL SUPPLY CURRENT vs. CAPACITIVE LOAD ON I/O VCC (DRIVING I/OVL, VCC = 3.3V, VL = +0.9V) VCC SUPPLY CURRENT vs. CAPACITIVE LOAD ON I/O VCC (DRIVING I/OVL, VCC = 3.3V, VL = +0.9V) RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O VCC (DRIVING I/OVL, VCC = 3.3V, VL = +0.9V) 60 40 20 DATA RATE = 230kbps 7 6 5 4 3 8 7 DATA RATE = 230kbps 30 40 50 60 70 80 20 30 40 50 60 70 80 RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O VL (DRIVING I/OVCC, = 3.3V, VL = +0.9V) PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O VCC (DRIVING I/OVL, VCC, = 3.3V, VL = +0.9V) tF 5 4 3 tR 2 9.0 8.5 PROPAGATION DELAY (ns) MAX31000Etoc10 6 8.0 7.5 7.0 6.5 6.0 1 5.5 0 5.0 10 20 30 40 50 60 70 CAPACITIVE LOAD (pF) 80 90 100 10 20 30 40 50 60 70 80 90 100 CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF) 7 tF 3 90 100 CAPACITIVE LOAD (pF) 8 4 0 10 90 100 PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O VL (DRIVING I/OVCC, VCC = 3.3V, VL = +0.9V) 6.5 6.0 PROPAGATION DELAY (ns) 20 5 1 0 10 tR 6 2 2 1 0 MAX31000Etoc09 9 MAX31000Etoc08 DATA RATE = 20Mbps MAX13000Etoc12 80 8 RISE/FALL TIME (ns) DATA RATE = 20Mbps 100 9 VCC SUPPLY CURRENT (mA) 120 MAX31000Etoc07 SUPPLY VOLTAGE (V) 140 VL SUPPLY CURRENT (μA) 320 300 0.001 RISE/FALL TIME (ns) 330 4.10 MAX13000E toc06 1.0 MAX31000Etoc11 VCC SUPPLY CURRENT (mA) DATA RATE = 20Mbps 340 VCC SUPPLY CURRENT (μA) MAX13000Etoc04 10 VCC SUPPLY CURRENT vs. TEMPERATURE (DRIVING I/OVCC, VCC = +3.3V, VL = +0.9V) VCC SUPPLY CURRENT (mA) VCC SUPPLY CURRENT vs. SUPPLY VOLTAGE (DRIVING I/OVCC, VL = +0.9V) 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 10 20 30 40 50 60 70 CAPACITIVE LOAD (pF) 80 90 100 10 20 30 40 50 60 70 80 90 100 CAPACITIVE LOAD (pF) _______________________________________________________________________________________ 7 MAX13000E–MAX13005E Typical Operating Characteristics (continued) (VCC = +3.3V, VL = +0.9V, TA = +25°C, MAX13003E.) Typical Operating Characteristics (continued) (VCC = +3.3V, VL = +0.9V, TA = +25°C, MAX13003E.) OD RAIL-TO-RAIL DRIVING (MAX13002E) (DRIVING I/OVL, VCC = +3.3V, VL = +0.9V, CI/OVCC = 56pF, DATA RATE = 230kbps, RPULLUP = 15kΩ) I/OVL_ 500mV/div GND RAIL-TO-RAIL DRIVING (DRIVING I/OVL, VCC = +3.3V, VL = +0.9V, CI/OVCC = 50pF, DATA RATE = 230kbps) MAX31000Etoc15 MAX31000Etoc14 I/OVL_ 500mV/div GND I/OVCC 2V/div GND I/OVCC 2V/div GND I/OVCC 2V/div GND 1μs/div 2μs/div 200ns/div RAIL-TO-RAIL DRIVING (DRIVING I/OVL, VCC = +3.3V, VL = +0.9V, CI/OVCC = 50pF, DATA RATE = 20Mbps) I/OVL_ 500mV/div GND I/OVCC 2V/div GND VCC + VL SUPPLY CURRENT vs. FREQUENCY (DRIVING I/OVL, VCC = +3.3V, VL = +0.9V) I/OVL_ 500mV/div GND I/OVCC 2V/div GND 40ns/div VCC + VL SUPPLY CURRENT (mA) MAX31000Etoc17 MAX31000Etoc16 RAIL-TO-RAIL DRIVING (DRIVING I/OVL VCC = +3.3V, VL = +0.9V, CI/OVCC = 50pF, DATA RATE = 4Mbps) 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I/OVL IS DRIVEN WITH A 0.9V SQUARE WAVE VCC + VL VCC VL 100 10ns/div 4250 8400 12,550 16,700 20,850 25,000 FREQUENCY (kHz) VOHL vs. IOHL FOR VL SIDE (VCC = 3.3V) VL = +2.5V 2.5 0.25 0.20 VL = +2.5V VOHL (V) VCC VL VL = +1.8V 1.5 8400 12,550 16,700 20,850 25,000 FREQUENCY (kHz) VL = +1.8V 0.15 VL = +0.9V 0.10 1.0 VL = +0.9V 0.05 0.5 0 4250 VOLL (V) VCC + VL 2.0 MAX13000Etoc21 I/OVCC IS DRIVEN WITH A 3.3V SQUARE WAVE 100 8 3.0 MAX31000Etoc19 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VOLL vs. IOLL FOR VL SIDE (VCC = 3.3V) MAX13000Etoc20 VCC + VL SUPPLY CURRENT vs. FREQUENCY (DRIVING I/OVCC, VCC = +3.3V, VL = +0.9V) 0 0 5 10 15 20 25 30 35 40 45 50 IOHL (μA) I/OVL_ 500mV/div GND MAX31000Etoc18 MAX31000Etoc13 OD RAIL-TO-RAIL DRIVING (MAX13005E) (DRIVING I/OVL, VCC = +3.3V, VL = +0.9V, CI/OVCC = 56pF, DATA RATE = 230Mbps, RPULLUP = 1kΩ) VCC + VL SUPPLY CURRENT (mA) MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators 0 5 10 15 20 25 30 35 40 45 50 IOLL (μA) _______________________________________________________________________________________ Ultra-Low-Voltage Level Translators VOLC (V) 0.20 VCC = +3.3V VCC = +1.8V 0.10 VCC = +3.3V 3.0 VOHC (V) VCC = +2.5V 0.15 3.5 MAX13000Etoc22 0.25 MAX13000Etoc23 VOHC vs. IOHC FOR VCC SIDE VOLC vs. IOLC FOR VCC SIDE VCC = +2.5V 2.5 2.0 VCC = +1.8V 1.5 0.05 1.0 0 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50 IOHC (μA) IOLC (μA) Pin Descriptions MAX13000E/MAX13003E PIN NAME FUNCTION TSSOP 1 UCSP B1 I/OVL1 CMOS Input/Output 1, Referenced to VL 2 B2 I/OVL2 CMOS Input/Output 2, Referenced to VL 3 A1 I/OVL3 CMOS Input/Output 3, Referenced to VL 4 A2 VL Logic Input Voltage, +0.9V ≤ VL ≤ VCC. Bypass VL to GND with a 0.1µF capacitor. 5 A3 EN Enable Input. When EN is pulled low, I/O VCC1 to I/O VCC6 and I/O VL1 to I/O VL6 are tri-stated. Drive EN high (VL) for normal operation. 6 A4 I/OVL4 CMOS Input/Output 4, Referenced to VL 7 B3 I/OVL5 CMOS Input/Output 5, Referenced to VL 8 B4 I/OVL6 9 C4 I/OVCC6 CMOS Input/Output 6, Referenced to VCC 10 C3 I/OVCC5 CMOS Input/Output 5, Referenced to VCC 11 D4 I/OVCC4 CMOS Input/Output 4, Referenced to VCC 12 D3 GND Ground 13 D2 VCC VCC Input Voltage, +1.5V ≤ VCC ≤ 3.6V. Bypass VCC to GND with a 0.1µF capacitor. For full ESD protection, use a 1µF bypass capacitor on VCC. 14 D1 I/OVCC3 CMOS Input/Output 3, Referenced to VCC 15 C2 I/OVCC2 CMOS Input/Output 2, Referenced to VCC 16 C1 I/OVCC1 CMOS Input/Output 1, Referenced to VCC CMOS Input/Output 6, Referenced to VL _______________________________________________________________________________________ 9 MAX13000E–MAX13005E Typical Operating Characteristics (continued) (VCC = +3.3V, VL = +0.9V, TA = +25°C, MAX13003E.) MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators Pin Descriptions (continued) MAX13001E/MAX13004E PIN 10 NAME FUNCTION TSSOP 1 UCSP B1 OVL1 CMOS Output 1, Referenced to VL 2 B2 OVL2 CMOS Output 2, Referenced to VL 3 A1 OVL3 CMOS Output 3, Referenced to VL 4 A2 VL Logic Input Voltage, +0.9V ≤ VL ≤ VCC. Bypass VL to GND with a 0.1µF capacitor. 5 A3 EN Enable Input. When EN is pulled low, OVCC1 to OVCC6 and IVL1 to IVL6 are tri-stated. Drive EN high (VL) for normal operation. 6 A4 OVL4 CMOS Output 4, Referenced to VL 7 B3 OVL5 CMOS Output 5, Referenced to VL 8 B4 OVL6 CMOS Output 6, Referenced to VL 9 C4 IVCC6 Open-Drain-Compatible Input 6, Reference to VCC 10 C3 IVCC5 Open-Drain-Compatible Input 5, Referenced to VCC 11 D4 IVCC4 Open-Drain-Compatible Input 4, Referenced to VCC 12 D3 GND Ground 13 D2 VCC VCC Input Voltage, +1.5V ≤ VCC ≤ 3.6V. Bypass VCC to GND with a 0.1µF capacitor. For full ESD protection, use a 1µF bypass capacitor on VCC. 14 D1 IVCC3 Open-Drain-Compatible Input 3, Referenced to VCC 15 C2 IVCC2 Open-Drain-Compatible Input 2, Referenced to VCC 16 C1 IVCC1 Open-Drain-Compatible Input 1, Referenced to VCC ______________________________________________________________________________________ Ultra-Low-Voltage Level Translators MAX13002E/MAX13005E PIN NAME FUNCTION TSSOP 1 UCSP B1 IVL1 Open-Drain-Compatible Input 1, Referenced to VL 2 B2 IVL2 Open-Drain-Compatible Input 2, Referenced to VL 3 A1 IVL3 Open-Drain-Compatible Input 3, Referenced to VL 4 A2 VL Logic Input Voltage, +0.9V ≤ VL ≤ VCC. Bypass VL to GND with a 0.1µF capacitor. 5 A3 EN Enable Input. When EN is pulled low, OVCC1 to OVCC6 and IVL1 to IVL6 are tri-stated. Drive EN high (VL) for normal operation. 6 A4 IVL4 Open-Drain-Compatible Input 4, Referenced to VL 7 B3 IVL5 Open-Drain-Compatible Input 5, Referenced to VL 8 B4 IVL6 Open-Drain-Compatible Input 6, Referenced to VL 9 C4 OVCC6 CMOS Output 6, Referenced to VCC 10 C3 OVCC5 CMOS Output 5, Referenced to VCC 11 D4 OVCC4 CMOS Output 4, Referenced to VCC 12 D3 GND Ground 13 D2 VCC VCC Input Voltage, +1.5V ≤ VCC ≤ 3.6V. Bypass VCC to GND with a 0.1µF capacitor. For full ESD protection, use a 1µF bypass capacitor on VCC. 14 D1 OVCC3 CMOS Output 3, Referenced to VCC 15 C2 OVCC2 CMOS Output 2, Referenced to VCC 16 C1 OVCC1 CMOS Output 1, Referenced to VCC ______________________________________________________________________________________ 11 MAX13000E–MAX13005E Pin Descriptions (continued) MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators Test Circuits/Timing Diagrams I/OVL_ 90% VL VCC 50% MAX13000E 10% EN tRISE/FALL I/OVL-VCC I/OVCC I/OVL_ SOURCE I/OVCC_ 90% RS CI/OVCC 50% 10% tFVCC tRVCC I/OVL-VCC UNUSED I/Os ARE GROUNDED. tRISE/FALL < 3ns (MAX13003E/MAX13004E/MAX13005E) tRISE/FALL < 80ns (MAX13000E/MAX13001E/MAX13002E) Figure 1b. Timing for Driving I/OVL Figure 1a. Driving I/OVL tRISE/FALL VL VCC I/OVCC_ MAX13000E 90% 50% EN 10% I/OVCC-VL I/OVL_ I/OVCC I/OVL_ I/OVCC-VL 90% 50% CI/OVL RS SOURCE 10% tFVL tRVL tRISE/FALL < 3ns (MAX13003E/MAX13004E/MAX13005E) UNUSED I/Os ARE GROUNDED. Figure 2a. Driving I/OVCC 12 tRISE/FALL < 80ns (MAX13000E/MAX13001E/MAX13002E) Figure 2b. Timing for Driving I/OVCC ______________________________________________________________________________________ Ultra-Low-Voltage Level Translators VL EN EN SOURCE MAX13000E t'EN-VCC 0 VL I/OVCC I/OVL_ I/OVL_ 0 CI/OVCC VL VCC VCC / 2 I/OVCC_ 0 VL t"EN-VCC EN SOURCE MAX13000E 0 EN I/OVL_ VL I/OVCC_ 0 VCC I/OVCC I/OVL_ CI/OVCC VCC / 2 0 tEN-VCC IS WHICH EVER IS LARGER BETWEEN t'EN-VCC AND t"EN-VCC. Figure 3. Propagation Delay from I/OVL to I/OVCC After EN VL EN VL EN SOURCE MAX13000E t'EN-VL VCC I/OVCC_ I/OVCC I/OVL_ 0 0 VL CI/OVL VCC I/OVL_ VL / 2 0 VL EN VL EN SOURCE t"EN-VL MAX13000E VCC I/OVCC_ I/OVL_ 0 VL I/OVCC CI/OVL 0 I/OVL_ VL / 2 0 tEN-VL IS WHICH EVER IS LARGER BETWEEN t'EN-VL AND t"EN-VL. Figure 4. Propagation Delay from I/OVCC to I/OVL After EN ______________________________________________________________________________________ 13 MAX13000E–MAX13005E Test Circuits/Timing Diagrams (continued) MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators Detailed Description The MAX13000E–MAX13005E logic-level translators provide the level shifting necessary to allow data transfer in multivoltage systems. Externally applied voltages, VCC and VL, set the logic levels on each side of the device. Logic signals present on the VL side of the device appear as higher voltage logic signals on the VCC side of the device, and vice-versa. The MAX13000E/MAX13003E are bidirectional level translators allowing data translation in either direction (VL ↔ VCC) on any single data line without the use of a DIRECTION input. The MAX13001E/MAX13002E/ MAX13004E/MAX13005E unidirectional level translators level shift data in one direction (VL → VCC or VCC → V L ) on any single data line. The MAX13001E/ MAX13002E/MAX13004E/MAX13005E unidirectional translators’ inputs have the capability to interface with both CMOS and open-drain (OD) outputs. For more information, see the Ordering Information section and the Input Driver Requirements section. The MAX13000E–MAX13005E accept VL from +0.9V to +3.6V. All devices have VCC ranging from +1.5V to +3.6V, making them ideal for data transfer between low-voltage ASICs/PLDs and higher voltage systems. The MAX13000E–MAX13005E feature low VCC quiescent supply current of less than 4µA, and VL quiescent supply current of less than 2µA when in shutdown. The MAX13000E–MAX13005E have ±15kV ESD protection on the VCC side for greater protection in applications that route signals externally. The ESD protection is specified using the Human Body Model (HBM).The MAX13000E/MAX13001E/MAX13002E operate at a guaranteed 230kbps data rate. The MAX13003E/ MAX13004E/MAX13005E operate at a guaranteed 20Mbps data rate when VCC > +1.65V. Level Translation For normal operation, ensure that +1.5V ≤ VCC ≤ +3.6V, and +0.9V ≤ VL ≤ VCC. During power-up sequencing, VL ≥ VCC does not damage the device whenever VL is within the absolute maximum ratings (see the Absolute Maximum Ratings section). During power-supply sequencing, when VCC is floating and VL is powered up, 1mA of current can be sourced to each load on the VL side, yet the device does not latch up. The MAX13000E–MAX13005E are designed to have VCC ≥ VL at all times; however, if VCC is turned off, the part will not be damaged and will not latch up. To prevent excessive leakage currents in either the I/O or supply lines, the I/O on the VL side must be left in the high state. 14 The maximum data rate for the MAX13000E– MAX13005E depends heavily on the load capacitance (see the Typical Operating Characteristics), output impedance of the driver, and the operational voltage range (see the Timing Characteristics table). Open-Drain Operation The MAX13001E/MAX13002E/MAX13004E/MAX13005E have input stages specifically designed to accommodate external open-drain drivers. When using opendrain drivers, the MAX13001E/MAX13002E/ MAX13004E/MAX13005E operate in a unidirectionalonly mode, translating from the OD side to the CMOS side. For improved performance, the rise- and fall-time accelerators are present on both the CMOS and the OD side. See the Input-Driver Requirement section. Do not use pullup resistors greater than 15kΩ for proper operation, and smaller pullup resistance may be needed for higher speed operation. Input-Driver Requirements The MAX13000E–MAX13005E feature four different architectures based on the speed of the part, as well as on whether the translator is a CMOS-to-CMOS translator, or whether it is an OD-to-CMOS translator. 20Mbps CMOS-to-CMOS Bidirectional Translator (MAX13003E) The MAX13003E architecture is based on a one-shot accelerator output stage (Figure 5). Accelerator output stages are always in tri-state, except when there is a transition on any of the translators on the input side, either I/OVL or I/OVCC. A short pulse is generated during which the one-shot output stage becomes active and charges/discharges the capacitances at the I/Os. Due to its bidirectional nature, the accelerator stages on both the I/OVCC and the I/OVL become active during an I/O transition from low to high or high to low. This can lead to some current feeding into the external source that is driving the translator. However, this behavior helps speed up the transition on the driven side. The type of devices that drive the inputs of the MAX13003E is usually specified with an output drivecurrent capability (IOUT). When driving the inputs of the MAX13003E, the maximum achievable speed is constrained by the drive current of the external driver. To insure the maximum possible throughput of 20Mbps, the external driver should meet the following requirement: IOUT ≥ 1.67 × 108 × V × (CIN + CP) ______________________________________________________________________________________ Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E VL VCC P ONE-SHOT 5kΩ I/OVL I/OVCC INVERTER 2 INVERTER 1 N ONE-SHOT P ONE-SHOT 5kΩ INVERTER 3 INVERTER 4 N ONE-SHOT Figure 5. Architecture of 20Mbps, CMOS-to-CMOS Bidirectional Translators where, CP is the parasitic capacitance of the traces, V is the supply voltage of the driven side (i.e., VL or VCC), and CIN is the input capacitance of the driven side (CIN = 10pF for VL side, CIN = 20pF for VCC side). 20Mbps OD-to-CMOS Unidirectional Translators (MAX13004E/MAX13005E) The MAX13004E/MAX13005E architecture is virtually the same as that for the bidirectional CMOS-to-CMOS translators, the only difference being that the output inverter (inverter 4) at the driving side accommodates the driving capabilities of an open-drain output (Figure 6). For proper operation, a pullup resistor needs to be connected from the open-drain output to the power supply of the driving side. Use pullup resistors no larger than 15kΩ. 230kbps CMOS-to-CMOS Bidirectional Translator (MAX13000E) The architecture of the MAX13000E lacks the one-shot accelerator output stages since the transitions that this device handles are limited by its data rate, 230kbps (Figure 7). For proper operation, the driver must meet the following conditions: 1kΩ maximum output impedance and 1mA minimum output current. 230kbps OD-to-CMOS Unidirectional Translators (MAX13001E/MAX13002E) The architecture of the MAX13001E/MAX13002E is similar to that of the 230kbps CMOS-to-CMOS part, with the difference that it accommodates the driving capability of an open-drain output on the driving side, and also that it has only a single one-shot output stage (Figure 8). For proper operation, a pullup resistor needs to be connected from the open-drain output to the power supply of the driving side. Use pullup resistors no larger than 15kΩ. Figure 9 shows a graph of the typical input current versus input voltage for all of the above configurations. Enable Output Mode (EN) The MAX13000E–MAX13005E feature an enable (EN) input. Drive EN low to set the MAX13000E–MAX13005E I/Os in tri-state mode. Drive EN high (VL) for normal operation. ±15kV ESD Protection As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The I/OV CC lines have extra protection against static discharge. Maxim’s engineers have developed state-of-the-art structures to protect these pins against ESD of ±15kV without damage. The ESD ______________________________________________________________________________________ 15 MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators 20Mbps OPEN-DRAIN-TO-CMOS UNIDIRECTIONAL LEVEL TRANSLATOR VCC/VL VL/VCC P ONE-SHOT 5kΩ IVCC/IVL OVL/OVCC INVERTER 2 OPEN-DRAIN COMPATIBLE INPUT INVERTER 1 CMOSCOMPATIBLE INPUT N ONE-SHOT P ONE-SHOT INVERTER 3 5kΩ 75kΩ INVERTER 4 N ONE-SHOT Figure 6. Architecture of 20Mbps, OD-to-CMOS Unidirectional Translators 230kbps Bidirectional CMOS-TO-CMOS Level Translator VL VCC 5kΩ I/OVL I/OVCC INVERTER 1 INVERTER 2 5kΩ INVERTER 4 INVERTER 3 Figure 7. Architecture of 230kbps, CMOS-to-CMOS Bidirectional Translator 16 ______________________________________________________________________________________ Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E 230kbps OPEN-DRAIN-TO-CMOS UNIDIRECTIONAL LEVEL TRANSLATOR VCC/VL VL/VCC 5kΩ IVCC/IVL OVL/OVCC INVERTER 1 OPEN-DRAIN COMPATIBLE INPUT INVERTER 2 CMOSCOMPATIBLE INPUT INVERTER 3 5kΩ 75kΩ INVERTER 4 5kΩ N ONE-SHOT Figure 8. Architecture of 230kbps, OD-to-CMOS Unidirectional Translator structures withstand high ESD in all states: normal operation, tri-state output mode, and power-down. After an ESD event, Maxim’s E-versions keep working without latchup, whereas competing products can latch and must be powered-down to remove latchup. ESD protection can be tested in various ways. The I/OVCC lines of the MAX13000E–MAX13005E are characterized for protection to ±15kV using the Human Body Model. IIN VTH_IN / RIN1 ESD Test Conditions 0 VTH_IN VIN VS WHERE, VS = VCC OR VL (VS - VTH_IN) / RIN2 RIN1 = RIN2 = 5kΩ FOR CMOS-TO-CMOS TRANSLATORS RIN1 = 75kΩ FOR OD-TO-CMOS TRANSLATORS Figure 9. Typical IIN vs. VIN ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. Human Body Model Figure 10 shows the Human Body Model and Figure 11 shows the current waveform it generates when discharged into a low impedance. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5kΩ resistor. ______________________________________________________________________________________ 17 MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators RC 1MΩ CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF RC 50Ω TO 100Ω RD 1500Ω DISCHARGE RESISTANCE CHARGE-CURRENTLIMIT RESISTOR DEVICE UNDER TEST STORAGE CAPACITOR HIGHVOLTAGE DC SOURCE Cs 150pF RD 330Ω DISCHARGE RESISTANCE DEVICE UNDER TEST STORAGE CAPACITOR Figure 10. Human Body ESD Test Model Figure 12. IEC 61000-4-2 Contact Discharge Test Model IP 100% 90% Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) UCSP Package Considerations AMPERES For general UCSP package information and PC layout considerations, please refer to Maxim application note: Wafer-Level Chip-Scale Package. 36.8% 10% 0 0 tRL UCSP Reliability TIME tDL CURRENT WAVEFORM Figure 11. Human Body Current Waveform IEC 61000-4-2 Standard ESD Protection The IEC 61000-4-2 standard (Figure 12) specifies ESD tolerance for electronic systems. The IEC61000-4-2 model specifies a 150pF capacitor that is discharged into the device through a 330Ω resistor. The MAX13000E–MAX13005E’s I/O on the V CC side are rated for IEC 61000-4-2 standard, (8kV Contact Discharge and ±10kV Air-Gap Discharge). The IEC 61000-4-2 model discharges higher peak current and more energy than the HBM due to the lower series resistance and larger capacitor. Applications Information The chip-scale package (UCSP) represents a unique packaging form factor that may not perform equally to a packaged product through traditional mechanical reliability tests. UCSP reliability is integrally linked to the user’s assembly methods, circuit board material, and usage environment. The user should closely review these areas when considering use of a UCSP package. Performance through Operating Life Test and Moisture Resistance remains uncompromised as it is primarily determined by the wafer-fabrication process. Mechanical stress performance is a greater consideration for a UCSP package. UCSPs are attached through direct solder contact to the user’s PC board, foregoing the inherent stress relief of a packaged product lead frame. Solder joint contact integrity must be considered. Information on Maxim’s qualification plan, test data, and recommendations are detailed in the UCSP application note, which can be found on Maxim’s website at www.maxim-ic.com. Power-Supply Decoupling To reduce ripple and the chance of transmitting incorrect data, bypass VL and VCC to ground with a 0.1µF capacitor. To ensure full ±15kV ESD protection, bypass VCC to ground with a 1µF capacitor. Place all capacitors as close to the power-supply inputs as possible. 18 ______________________________________________________________________________________ Ultra-Low-Voltage Level Translators VL VCC EN MAX13000E–MAX13005E I/OVL1 I/OVCC1 I/OVL2 I/OVCC2 I/OVL3 I/OVCC3 I/OVL4 I/OVCC4 I/OVL5 I/OVCC5 I/OVL6 I/OVCC6 GND ______________________________________________________________________________________ 19 MAX13000E–MAX13005E Functional Diagram Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E Typical Operating Circuits +0.9V +2.8V 0.1μF 1μF VCC VL +0.9V SYSTEM CONTROLLER +2.8V SYSTEM MAX13001E DATA1 DATA2 EN MAX13004E OVL_1 IVCC_1 OVL_2 IVCC_2 DATA3 OVL_3 IVCC_3 DATA3 DATA4 OVL_4 IVCC_4 DATA4 DATA5 OVL_5 IVCC_5 DATA5 DATA6 OVL_6 IVCC_6 DATA6 DATA1 DATA2 GND +0.9V +2.8V 0.1μF 1μF VCC VL +0.9V SYSTEM CONTROLLER +2.8V SYSTEM MAX13002E DATA1 DATA2 EN MAX13005E IVL_1 OVCC_1 IVL_2 OVCC_2 DATA3 IVL_3 OVCC_3 DATA3 DATA4 IVL_4 OVCC_4 DATA4 DATA5 IVL_5 OVCC_5 DATA5 DATA6 IVL_6 OVCC_6 DATA6 DATA1 DATA2 GND 20 ______________________________________________________________________________________ Ultra-Low-Voltage Level Translators +0.9V +2.8V 0.1μF 1μF VL +0.9V SYSTEM CONTROLLER VCC +2.8V SYSTEM MAX13000E DATA1 EN MAX13003E I/OVL_1 I/OVCC_1 DATA1 DATA2 I/OVL_2 I/OVCC_2 DATA2 DATA3 I/OVL_3 I/OVCC_3 DATA3 DATA4 I/OVL_4 I/OVCC_4 DATA4 DATA5 I/OVL_5 I/OVCC_5 DATA5 DATA6 I/OVL_6 I/OVCC_6 DATA6 GND Selector Guide PART DATA RATE (bps) NUMBER OF BIDIRECTIONAL TRANSLATORS NUMBER OF VL → VCC TRANSLATORS NUMBER OF VCC → VL TRANSLATORS TRANSLATOR CONFIGURATION MAX13000E 230k 6 — — CMOS-to-CMOS MAX13001E 230k — — 6 OD-to-CMOS MAX13002E 230k — 6 — OD-to-CMOS MAX13003E 20M 6 — — CMOS-to-CMOS MAX13004E 20M — — 6 OD-to-CMOS MAX13005E 20M — 6 — OD-to-CMOS ______________________________________________________________________________________ 21 MAX13000E–MAX13005E Typical Operating Circuits (continued) Ultra-Low-Voltage Level Translators MAX13000E–MAX13005E Pin Configurations (continued) BOTTOM VIEW MAX13001E/MAX13004E IVCC3 VCC GND MAX13002E/MAX13005E IVCC4 D OVCC3 VCC GND OVCC4 OVCC1 OVCC2 OVCC5 OVCC6 IVL1 IVL2 IVL5 IVL6 IVL3 VL EN IVL4 2 3 4 D IVCC1 IVCC2 IVCC5 IVCC6 C C OVL1 OVL2 OVL5 OVL6 B B OVL3 VL EN OVL4 A A 1 2 3 4 1 4 X 4 UCSP 4 X 4 UCSP TOP VIEW I/OVL1 1 16 I/OVCC1 OVL1 1 16 IVCC1 IVL1 1 16 OVCC1 I/OVL2 2 15 I/OVCC2 OVL2 2 15 IVCC2 IVL2 2 15 OVCC2 I/OVL3 3 14 I/OVCC3 OVL3 3 14 IVCC3 IVL3 3 14 OVCC3 VL 4 EN 5 13 VCC MAX13000E MAX13003E EN 5 13 VCC MAX13001E MAX13004E VL 4 12 GND EN 5 13 VCC MAX13002E MAX13005E 12 GND I/OVL4 6 11 I/OVCC4 OVL4 6 11 IVCC4 IVL4 6 11 OVCC4 I/OVL5 7 10 I/OVCC5 OVL5 7 10 IVCC5 IVL5 7 10 OVCC5 I/OVL6 8 9 I/OVCC6 OVL6 8 9 IVCC6 IVL6 8 9 TSSOP 22 12 GND VL 4 TSSOP TSSOP ______________________________________________________________________________________ OVCC6 Ultra-Low-Voltage Level Translators PART TEMP RANGE PINPACKAGE MAX13000EEBE+T* -40°C to +85°C 16 UCSP (4mm × 4mm) MAX13001EEUE+ -40°C to +85°C 16 TSSOP MAX13001EEBE+T* -40°C to +85°C 16 UCSP (4mm × 4mm) MAX13002EEUE+ -40°C to +85°C 16 TSSOP MAX13002EEBE+T* -40°C to +85°C 16 UCSP (4mm × 4mm) MAX13003EEUE+ -40°C to +85°C 16 TSSOP MAX13003EEBE+T* -40°C to +85°C 16 UCSP (4mm × 4mm) MAX13004EEUE+ -40°C to +85°C 16 TSSOP MAX13004EEBE+T* -40°C to +85°C 16 UCSP (4mm × 4mm) MAX13005EEUE+ -40°C to +85°C 16 TSSOP Chip Information PROCESS: BiCMOS 16 UCSP (4mm × 4mm) *Future Product—contact factory for availability. +Denotes a lead(Pb)-free/RoHS-compliant package. T =Tape and reel. MAX13005EEBE+T* -40°C to +85°C ______________________________________________________________________________________ 23 MAX13000E–MAX13005E Ordering Information (continued) MAX13000E–MAX13005E Ultra-Low-Voltage Level Translators Package Information For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. 24 PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 16 TSSOP U16+2 21-0066 90-0117 16 UCSP B16+1 21-0101 Refer to Application Note 1891 ______________________________________________________________________________________ Ultra-Low-Voltage Level Translators REVISION NUMBER REVISION DATE 0 6/05 Initial release 1 5/11 Added lead-free information to the Ordering Information DESCRIPTION PAGES CHANGED — 1, 23 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 25 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX13000E–MAX13005E Revision History