E PRELIMINARY INTEL® StrataFlash™ MEMORY TECHNOLOGY 32 AND 64 MBIT 28F320J5 and 28F640J5 n n n n n n High-Density Symmetrically-Blocked Architecture 64 128-Kbyte Erase Blocks (64 M) 32 128-Kbyte Erase Blocks (32 M) 4.5 V–5.5 V VCC Operation 2.7 V–3.6 V and 4.5 V–5.5 V I/O Capable Configurable x8 or x16 I/O 100 ns Read Access Time (32 M) 150 ns Read Access Time (64 M) Enhanced Data Protection Features Absolute Protection with VPEN = GND Flexible Block Locking Block Erase/Program Lockout during Power Transitions Industry-Standard Packaging µBGA* Package (64 M), SSOP and TSOP Packages (32 M) n n n n n n n Cross-Compatible Command Support Intel Basic Command Set Common Flash Interface Scaleable Command Set 32-Byte Write Buffer 6.3 µs per Byte Effective Programming Time 6,400,000 Total Erase Cycles (64 M) 3,200,000 Total Erase Cycles (32 M) 100,000 Erase Cycles per Block Automation Suspend Options Block Erase Suspend to Read Block Erase Suspend to Program System Performance Enhancements STS Status Output Expanded Temperature Operation –20 °C to +70 °C Intel® StrataFlash™ Memory Flash Technology Capitalizing on two-bit-per-cell technology, Intel® StrataFlash™ memory products provide 2X the bits in 1X the space. Offered in 64-Mbit (8-Mbyte) and 32-Mbit (4-Mbyte) densities, Intel StrataFlash memory devices are the first to bring reliable, two-bit-per-cell storage technology to the flash market. Intel StrataFlash memory benefits include: more density in less space, lowest cost-per-bit NOR devices, support for code and data storage, and easy migration to future devices. Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, Intel StrataFlash memory devices take advantage of 400 million units of manufacturing experience since 1988. As a result, Intel StrataFlash components are ideal for code or data applications where high density and low cost are required. Examples include networking, telecommunications, audio recording, and digital imaging. By applying FlashFile™ memory family pinouts, Intel StrataFlash memory components allow easy design migrations from existing 28F016SA/SV, 28F032SA, and Word-Wide FlashFile memory devices (28F160S5 and 28F320S5). Intel StrataFlash memory components deliver a new generation of forward-compatible software support. By using the Common Flash Interface (CFI) and the Scaleable Command Set (SCS), customers can take advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices. Manufactured on Intel’s 0.4 micron ETOX™ V process technology, Intel StrataFlash memory provides the highest levels of quality and reliability. July 1998 Order Number: 290606-006 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F320J5 and 28F640J4 may contain design defects or errors known as errata. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 8021-9808 or call 1-800-548-4725 or visit Intel’s website at http://www.intel.com COPYRIGHT © INTEL CORPORATION 1997, 1998 CG-041493 *Third-party brands and names are the property of their respective owners. 2 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT CONTENTS PAGE 1.0 PRODUCT OVERVIEW ...................................5 2.0 PRINCIPLES OF OPERATION .....................11 2.1 Data Protection ..........................................12 3.0 BUS OPERATION .........................................12 3.1 Read ..........................................................13 3.2 Output Disable ...........................................13 3.3 Standby......................................................13 3.4 Reset/Power-Down ....................................13 3.5 Read Query................................................14 3.6 Read Identifier Codes.................................14 3.7 Write ..........................................................14 4.0 COMMAND DEFINITIONS ............................14 4.1 Read Array Command................................18 4.2 Read Query Mode Command.....................18 4.2.1 Query Structure Output .......................18 4.2.2 Query Structure Overview ...................20 4.2.3 Block Status Register ..........................21 4.2.4 CFI Query Identification String.............22 4.2.5 System Interface Information...............23 4.2.6 Device Geometry Definition .................24 4.2.7 Primary-Vendor Specific Extended Query Table .......................................25 4.3 Read Identifier Codes Command ...............26 4.4 Read Status Register Command................27 4.5 Clear Status Register Command................27 4.6 Block Erase Command ..............................27 4.7 Block Erase Suspend Command................27 PRELIMINARY PAGE 4.8 Write to Buffer Command ...........................28 4.9 Byte/Word Program Commands.................28 4.10 Configuration Command...........................29 4.11 Set Block and Master Lock-Bit Commands................................................29 4.12 Clear Block Lock-Bits Command ..............30 5.0 DESIGN CONSIDERATIONS ........................40 5.1 Three-Line Output Control..........................40 5.2 STS and Block Erase, Program, and LockBit Configuration Polling ............................40 5.3 Power Supply Decoupling ..........................40 5.4 VCC, VPEN, RP# Transitions........................40 5.5 Power-Up/Down Protection ........................41 5.6 Power Dissipation.......................................41 6.0 ELECTRICAL SPECIFICATIONS..................42 6.1 Absolute Maximum Ratings ........................42 6.2 Operating Conditions..................................42 6.3 Capacitance ...............................................42 6.4 DC Characteristics .....................................43 6.5 AC Characteristics—Read-Only Operations.................................................46 6.6 AC Characteristics— Write Operations.......48 6.7 Block Erase, Program, and Lock-Bit Configuration Performance........................51 7.0 ORDERING INFORMATION..........................52 8.0 ADDITIONAL INFORMATION .......................53 3 ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT E REVISION HISTORY 4 Date of Revision Version Description 09/01/97 -001 Original Version 09/17/97 -002 Modifications made to cover sheet 12/01/97 -003 VCC/GND Pins Converted to No Connects specification change added ICCS, ICCD, ICCW, and ICCE specification change added Order Codes specification change added 1/31/98 -004 The µBGA* chip-scale package in Figure 2 was changed to a 52-ball package and appropriate documentation added. The 64-Mb µBGA package dimensions were changed in Figure 2. Changed Figure 4 to read SSOP instead of TSOP. 3/23/98 -005 32-Mbit Intel StrataFlash memory read access time added. The number of block erase cycles was changed. The write buffer program time was changed. The operating temperature was changed. A read parameter was added. Several program, erase, and lock-bit specifications were changed. Minor documentation changes were made as well. Datasheet designation changed from Advance Information to Preliminary. 7/13/98 -006 Intel StrataFlash memory 32-Mb µBGA package removed. tEHEL read specification reduced. Table 4 was modified. The Ordering Information was updated. PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 1.0 PRODUCT OVERVIEW The Intel® StrataFlash™ memory family contains high-density memories organized as 8 Mbytes or 4 Mwords (64-Mbit) and 4 Mbytes or 2 Mwords (32-Mbit). These devices can be accessed as 8- or 16-bit words. The 64-Mbit device is organized as sixty-four 128-Kbyte (131,072 bytes) erase blocks while the 32-Mbits device contains thirty-two 128Kbyte erase blocks. Blocks are selectively and individually lockable and unlockable in-system. See the memory map in Figure 5. A Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backwardcompatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Scaleable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. Individual block locking uses a combination of bits, block lock-bits and a master lock-bit, to lock and unlock blocks. Block lock-bits gate block erase and program operations while the master lock-bit gates block lock-bit modification. Three lock-bit configuration operations set and clear lock-bits (Set Block Lock-Bit, Set Master Lock-Bit, and Clear Block Lock-Bits commands). The status register indicates when the WSM’s block erase, program, or lock-bit configuration operation is finished. The STS (STATUS) output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status indication using STS minimizes both CPU overhead and system power consumption. When configured in level mode (default mode), it acts as a RY/BY# pin. When low, STS indicates that the WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates that the WSM is ready for a new command, block erase is suspended (and programming is inactive), or the device is in reset/power-down mode. Additionally, the configuration command allows the STS pin to be configured to pulse on completion of programming and/or block erases. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. Three CE pins are used to enable and disable the device. A unique CE logic design (see Table 2, Chip Enable Truth Table) reduces decoder logic typically required for multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4-chip miniature card or SIMM module. A block erase operation erases one of the device’s 128-Kbyte blocks typically within one second— independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. The BYTE# pin allows either x8 or x16 read/writes to the device. BYTE# at logic low selects 8-bit mode; address A0 selects between the low byte and high byte. BYTE# at logic high enables 16-bit operation; address A1 becomes the lowest order address and address A0 is not used (don’t care). A device block diagram is shown in Figure 1. Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming performance. By using the Write Buffer, data is programmed in buffer increments. This feature can improve system program performance by up to 20 times over non Write Buffer writes. When the device is disabled (see Table 2, Chip Enable Truth Table) and the RP# pin is at VCC, the standby mode is enabled. When the RP# pin is at GND, a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# switching high until outputs PRELIMINARY 5 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT are valid. Likewise, the device has a wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. available in 56-lead SSOP (Shrink Small Outline Package) and µBGA* package (micro Ball Grid Array). The 32-Mbit is available in 56-lead TSOP (Thin Small Outline Package) and 56-lead SSOP. Figures 2, 3, and 4 show the pinouts. The Intel StrataFlash memory devices are available in several package types. The 64-Mbit is DQ0 - DQ15 VCCQ Output Buffer Input Buffer Status Register Write Buffer Identifier Register VCC I/O Logic Data Register Output Multiplexer Query Command User Interface BYTE# CE Logic CE0 CE1 CE2 WE# OE# RP# Multiplexer Data Comparator 32-Mbit: A0- A21 64-Mbit: A0 - A22 Y-Decoder Y-Gating Input Buffer Address Latch STS Write State Machine X-Decoder 32-Mbit: Thirty-two 64-Mbit: Sixty-four 128-Kbyte Blocks Program/Erase Voltage Switch VPEN VCC GND Address Counter 0606_01 Figure 1. Intel® StrataFlash™ Memory Block Diagram 6 PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 1. Lead Descriptions Symbol Type Name and Function A0 INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is high). A1–A22 INPUT ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are internally latched during a program cycle. 32-Mbit: A0–A21 64-Mbit: A0–A22 DQ0–DQ7 INPUT/ LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and OUTPUT inputs commands during Command User Interface (CUI) writes. Outputs array, query, identifier, or status data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. Outputs DQ 6–DQ0 are also floated when the Write State Machine (WSM) is busy. Check SR.7 (Status Register bit 7) to determine WSM status. DQ8–DQ15 INPUT/ HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming OUTPUT operations. Outputs array, query, or identifier data in the appropriate read mode; not used for Status Register reads. Floated when the chip is de-selected, the outputs are disabled, or the WSM is busy. CE0, CE1, CE2 INPUT CHIP ENABLES: Activates the device’s control logic, input buffers, decoders, and sense amplifiers. When the device is de-selected (see Table 2, Chip Enable Truth Table), power reduces to standby levels. All timing specifications are the same for these three signals. Device selection occurs with the first edge of CE 0, CE1, or CE2 that enables the device. Device deselection occurs with the first edge of CE 0, CE1, or CE2 that disables the device (see Table 2, Chip Enable Truth Table). RP# INPUT RESET/ POWER-DOWN: Resets internal automation and puts the device in power-down mode. RP#-high enables normal operation. Exit from reset sets the device to read array mode. When driven low, RP# inhibits write operations which provides data protection during power transitions. RP# at VHH enables master lock-bit setting and block lock-bits configuration when the master lock-bit is set. RP# = V HH overrides block lock-bits thereby enabling block erase and programming operations to locked memory blocks. Do not permanently connect RP# to VHH. OE# INPUT OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle. OE# is active low. WE# INPUT WRITE ENABLE: Controls writes to the Command User Interface, the Write Buffer, and array blocks. WE# is active low. Addresses and data are latched on the rising edge of the WE# pulse. STS OPEN STATUS: Indicates the status of the internal state machine. When configured in DRAIN level mode (default mode), it acts as a RY/BY# pin. When configured in one of OUTPUT its pulse modes, it can pulse to indicate program and/or erase completion. For alternate configurations of the STATUS pin, see the Configurations command. Tie STS to VCCQ with a pull-up resistor. PRELIMINARY 7 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 1. Lead Descriptions (Continued) Symbol Type Name and Function BYTE# INPUT BYTE ENABLE: BYTE# low places the device in x8 mode. All data is then input or output on DQ0–DQ7, while DQ8–DQ15 float. Address A 0 selects between the high and low byte. BYTE# high places the device in x16 mode, and turns off the A0 input buffer. Address A1 then becomes the lowest order address. VPEN INPUT ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or configuring lock-bits. With VPEN ≤ VPENLK, memory contents cannot be altered. VCC SUPPLY DEVICE POWER SUPPLY: With VCC ≤ VLKO, all write attempts to the flash memory are inhibited. VCCQ OUTPUT OUTPUT BUFFER POWER SUPPLY: This voltage controls the device’s output BUFFER voltages. To obtain output voltages compatible with system data bus voltages, SUPPLY connect VCCQ to the system supply voltage. GND SUPPLY GROUND: Do not float any ground pins. NC 8 NO CONNECT: Lead is not internally connected; it may be driven or floated. PRELIMINARY E 8 ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 7 6 5 4 3 2 GND A10 VPEN CE0 A14 VCC A4 A7 A9 A11 A12 A15 A17 A19 A5 A6 A8 RP# A13 A16 A21 A2 A1 A3 A18 CE1 2 3 4 5 VCC A14 CE0 VPEN A10 GND A19 A17 A15 A12 A11 A9 A7 A4 A20 A20 A21 A16 A13 RP# A6 A5 A22 A22 CE1 A18 A1 A2 1 1 6 7 8 A A B B C C A8 D D A3 E E F F CE2 NC(1) BYTE# A0 DQ8 DQ1 DQ3 DQ12 DQ6 DQ0 DQ9 DQ2 DQ11 DQ4 DQ13 VCC(1) DQ10 GND VCCQ DQ5 DQ7 NC(1) WE# WE# NC(1) DQ7 BYTE# NC(1) CE2 DQ15 OE# OE# DQ15 DQ6 DQ12 DQ3 DQ1 DQ8 A0 DQ14 STS STS DQ14 DQ13 DQ4 DQ11 DQ2 DQ9 DQ0 GND(1) DQ5 VCCQ GND DQ10 VCC(1) G G H H I I GND(1) Bottom View - Ball Side Up 64-Mbit Intel® Top View StrataFlash™ Memory: 7.67 mm x 16.37 mm NOTE: 1. VCC (Ball I7), GND (Ball I2), and NC (Balls F2 and F7) have been removed. Future generations of Intel StrataFlash memory may make use of these missing ball locations. Figures are not drawn to scale. Figure 2. µBGA* Package (64 Mbit) PRELIMINARY 9 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 28F160S5 28F016SV 28F032SA 28F320J5 28F016SA NC CE1 NC A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 3/5# CE1 NC A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 3/5# CE1 CE2 A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 NC CE1 A21 A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPEN RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 28F320J5 28F032SA 28F016SV 28F160S5 28F016SA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Intel® StrataFlash™ Memory 56-Lead TSOP Standard Pinout 14 mm x 20 mm Top View 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 NC WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCCQ GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC CE2 WP# WE# OE# RY/BY# DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC WP# WE# OE# RY/BY# DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC WP# WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC Highlights pinout changes 0606_03 NOTE: 1. VCC (Pin 37) and GND (Pin 48) are not internally connected. For future device revisions, it is recommended that these pins be connected to their respected power supplies (i.e., Pin 37 = VCC and Pin 48 = GND). 2. For compatibility with future generations of Intel® StrataFlash™ memory, this NC (pin 56) should be connected to GND. Figure 3. TSOP Lead Configuration (32 Mbit) 10 PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 28F016SA 28F160S5 28F320S5 28F016SV CE0# A12 A13 A14 A15 3/5# CE1# NC A20 A19 A18 A17 A16 VCC GND DQ6 DQ14 DQ7 DQ15 RY/BY# OE# WE# WP# DQ13 DQ5 DQ12 DQ4 VCC CE0# A12 A13 A14 A15 NC CE1# NC A20 A19 A18 A17 A16 VCC GND DQ6 DQ14 DQ7 DQ15 RY/BY# OE# WE# WP# DQ13 DQ5 DQ12 DQ4 VCC 28F640J5 CE0# A12 A13 A14 A15 NC CE1# A21 A20 A19 A18 A17 A16 VCC GND DQ6 DQ14 DQ7 DQ15 RY/BY# OE# WE# WP# DQ13 DQ5 DQ12 DQ4 VCC CE0 A12 A13 A14 A15 A22 CE1 A21 A20 A19 A18 A17 A16 VCC GND DQ6 DQ14 DQ7 DQ15 STS OE# WE# NC DQ13 DQ5 DQ12 DQ4 VCCQ 28F320J5 CE0 A12 A13 A14 A15 NC CE1 A21 A20 A19 A18 A17 A16 VCC GND DQ6 DQ14 DQ7 DQ15 STS OE# WE# NC DQ13 DQ5 DQ12 DQ4 VCCQ 28F320J5 1 2 3 4 5 6 7 8 9 10 Intel® 11 12 StrataFlash™ Memory 56-Lead SSOP 13 Standard Pinout 14 15 16 mm x 23.7 mm 16 17 Top View 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VPEN RP# A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC CE2 DQ2 DQ10 DQ3 DQ11 GND 28F640J5 28F320S5 28F160S5 28F016SA 28F016SV VPEN RP# A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC CE2 DQ2 DQ10 DQ3 DQ11 GND VPP RP# A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC DQ2 DQ10 DQ3 DQ11 GND VPP RP# A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC DQ2 DQ10 DQ3 DQ11 GND VPP RP# A11 A10 A9 A1 A2 A3 A4 A5 A6 A7 GND A8 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC DQ2 DQ10 DQ3 DQ11 GND Highlights pinout changes. 0606_04 NOTE: 1. VCC (Pin 42) and GND (Pin 15) are not internally connected. For future device revisions, it is recommended that these pins be connected to their respected power supplies (i.e., Pin 42 = VCC and Pin 15 = GND). 2. For compatibility with future generations of Intel StrataFlash memory, this NC (pin 23) should be connected to GND Figure 4. SSOP Lead Configuration (64 Mbit and 32 Mbit) 2.0 PRINCIPLES OF OPERATION The Intel StrataFlash memory devices include an on-chip WSM to manage block erase, program, and lock-bit configuration functions. It allows for 100% TTL-level control inputs, fixed power supplies during block erasure, program, lock-bit configuration, and minimal processor overhead with RAM-like interface timings. PRELIMINARY After initial device power-up or return from reset/power-down mode (see Bus Operations), the device defaults to read array mode. Manipulation of external memory control pins allows array read, standby, and output disable operations. Read array, status register, query, and identifier codes can be accessed through the CUI (Command User Interface) independent of the VPEN voltage. 11 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT VPENH on VPEN enables successful block erasure, programming, and lock-bit configuration. All functions associated with altering memory contents—block erase, program, lock-bit configuration—are accessed via the CUI and verified through the status register. Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase, program, and lock-bit configuration. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification, and margining of data. Addresses and data are internally latched during program cycles. Interface software that initiates and polls progress of block erase, program, and lock-bit configuration can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read or program data from/to any other block. A [22-0]: 64-Mbit A [21-0]: 32-Mbit 2.1 Data Protection Depending on the application, the system designer may choose to make the VPEN switchable (available only when memory block erases, programs, or lockbit configurations are required) or hardwired to VPENH. The device accommodates either design practice and encourages optimization of the processor-memory interface. When VPEN ≤ VPENLK, memory contents cannot be altered. The CUI’s two-step block erase, byte/word program, and lock-bit configuration command sequences provide protection from unwanted operations even when VPENH is applied to VPEN. All program functions are disabled when VCC is below the write lockout voltage VLKO or when RP# is VIL. The device’s block locking capability provides additional protection from inadvertent code or data alteration by gating erase and program operations. 3.0 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. A [22-1]: 64-Mbit A [21-1]: 32-Mbit 7FFFFF 3FFFFF 128-Kbyte Block 63 64-Kword Block 63 64-Kword Block 31 64-Kword Block 1 64-Kword Block 0 3F0000 3FFFFF 1FFFFF 128-Kbyte Block 31 1F0000 03FFFF 32-Mbit 3E0000 01FFFF 128-Kbyte Block 1 020000 01FFFF 64-Mbit 7E0000 010000 00FFFF 128-Kbyte Block 0 000000 000000 Byte-Wide (x8) Mode Word Wide (x16) Mode 0606_05 Figure 5. Memory Map 12 PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 2. Chip Enable Truth Table(1,2) CE2 CE1 CE0 DEVICE VIL VIL VIL Enabled VIL VIL VIH Disabled VIL VIH VIL Disabled VIL VIH VIH Disabled VIH VIL VIL Enabled VIH VIL VIH Enabled VIH VIH VIL Enabled VIH VIH VIH Disabled NOTE: 1. See Application Note AP-647 Intel StrataFlash™ Memory Design Guide for typical CE configurations. 2. For single-chip applications CE2 and CE1 can be strapped to GND. 3.1 Read Information can be read from any block, query, identifier codes, or status register independent of the VPEN voltage. RP# can be at either VIH or VHH. Upon initial device power-up or after exit from reset/power-down mode, the device automatically resets to read array mode. Otherwise, write the appropriate read mode command (Read Array, Read Query, Read Identifier Codes, or Read Status Register) to the CUI. Six control pins dictate the data flow in and out of the component: CE0, CE1, CE2, OE#, WE#, and RP#. The device must be enabled (see Table 2, Chip Enable Truth Table), and OE# must be driven active to obtain data at the outputs. CE0, CE1, and CE2 are the device selection controls and, when enabled (see Table 2, Chip Enable Truth Table), select the memory device. OE# is the data output (DQ0–DQ15) control and, when active, drives the selected memory data onto the I/O bus. WE# must be at V IH. 3.2 Output Disable With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins DQ0–DQ15 are placed in a high-impedance state. PRELIMINARY 3.3 Standby CE0, CE1, and CE2 can disable the device (see Table 2, Chip Enable Truth Table) and place it in standby mode which substantially reduces device power consumption. DQ0–DQ15 outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, program, or lock-bit configuration, the WSM continues functioning, and consuming active power until the operation completes. 3.4 Reset/Power-Down RP# at VIL initiates the reset/power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and turns off numerous internal circuits. RP# must be held low for a minimum of tPLPH. Time tPHQV is required after return from reset mode until initial memory access outputs are valid. After this wakeup interval, normal operation is restored. The CUI is reset to read array mode and status register is set to 80H. During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In default mode, STS transitions low and remains low for a maximum time of tPLPH + tPHRH until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, program, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. Intel’s flash memories allow proper initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. 13 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT The read query operation outputs block status information, CFI (Common Flash Interface) ID string, system interface information, device geometry information, and Intel-specific extended query information. 3.6 Read Identifier Codes The read identifier codes operation outputs the manufacturer code, device code, block lock configuration codes for each block, and the master lock configuration code (see Figure 6). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. The block lock and master lock configuration codes identify locked and unlocked blocks and master lock-bit setting. 3.7 VPEN additionally enables block erase, program, and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 4 defines these commands. Word Address 3FFFFF The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte/Word Program command requires the command and address of the location to be written. Set Master and Block Lock-Bit commands require the command and address within the device (Master Lock) or block within the device (Block Lock) to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when the device is enabled and WE# is active. The address and data needed to execute a command are latched on the rising edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device (see Table 2, Chip Enable Truth Table). Standard microprocessor write timings are used. Block 63 Reserved for Future Implementation 3F0003 3F0002 3F0000 3EFFFF Block 63 Lock Configuration Reserved for Future Implementation (Blocks 32 through 62) Block 31 Reserved for Future Implementation Write Writing commands to the CUI enables reading of device data, query, identifier codes, inspection and clearing of the status register, and, when VPEN = VPENH, block erasure, program, and lock-bit configuration. A[22-1]: 64 Mbit A[21-1]: 32 Mbit 1F0003 1F0002 1F0000 1EFFFF 01FFFF Block 31 Lock Configuration Reserved for Future Implementation (Blocks 2 through 30) Block 1 Reserved for Future Implementation 010003 010002 010000 00FFFF 64 Mbit Read Query 32 Mbit 3.5 Block 1 Lock Configuration Reserved for Future Implementation Block 0 Reserved for Future Implementation 000004 000003 000002 000001 000000 Master Lock Configuration Block 0 Lock Configuration Device Code Manufacturer Code 0606_06 4.0 COMMAND DEFINITIONS When the VPEN voltage ≤ VPENLK, only read operations from the status register, query, identifier codes, or blocks are enabled. Placing VPENH on 14 NOTE: A0 is not used in either x8 or x16 modes when obtaining these identifier codes. Data is always given on the low byte in x16 mode (upper byte contains 00h). Figure 6. Device Identifier Code Memory Map PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 3. Bus Operations VPEN DQ(8) STS (default mode) X X DOUT High Z(9) VIH X X High Z X X X X X High Z X X X X X X High Z High Z(9) VIH or VHH Enabled VIL VIH See Figure 6 X Note 4 High Z(9) Read Query VIH or VHH Enabled VIL VIH See Table 7 X Note 5 High Z(9) Read Status (WSM off) VIH or VHH Enabled VIL VIH X X DOUT Read Status (WSM on) VIH or VHH Enabled VIL VIH X VPENH DQ7 = DOUT DQ15–8 = High Z DQ6–0 = High Z VIH or VHH Enabled VIH VIL X X DIN Mode CE0,1,2(10) OE#(11) WE#(11) Address Notes RP# 1,2,3 VIH or VHH Enabled VIL VIH Output Disable VIH or VHH Enabled VIH Standby VIH or VHH Disabled VIL Read Identifier Codes Read Array Reset/PowerDown Mode Write 3,6,7 X NOTES: 1. Refer to DC Characteristics. When VPEN ≤ VPENLK, memory contents can be read, but not altered. 2. X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN. See DC Characteristics for VPENLK and VPENH voltages. 3. In default mode, STS is VOL when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It is VOH when the WSM is not busy, in block erase suspend mode (with programming inactive), or reset/power-down mode. 4. See Read Identifier Codes Command section for read identifier code data. 5. See Read Query Mode Command section for read query data. 6. Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN = VPENH and VCC is within specification. Block erase, program, or lock-bit configuration with VIH < RP# < VHH produce spurious results and should not be attempted. 7. Refer to Table 4 for valid DIN during a write operation. 8. DQ refers to DQ0–DQ7 if BYTE# is low and DQ0–DQ15 if BYTE# is high. 9. High Z will be VOH with an external pull-up resistor. 10. See Table 2 for valid CE configurations. 11. OE# and WE# should never be enabled simultaneously. PRELIMINARY 15 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 4. Intel® StrataFlash™ Memory Command Set Definitions(14) Command Scaleable Bus Notes or Basic Cycles Command Req'd. Set(15) First Bus Cycle Oper(1) Read Array SCS/BCS 1 Read Identifier Codes SCS/BCS ≥2 Read Query SCS ≥2 Read Status Register SCS/BCS 2 Clear Status Register SCS/BCS 1 Write to Buffer SCS/BCS >2 Word/Byte Program SCS/BCS Block Erase Second Bus Cycle Addr(2) Data(3,4) Oper(1) Addr(2) Data(3,4) Write X FFH Write X 90H Read IA ID Write X 98H Read QA QD Write X 70H Read X SRD Write X 50H 7,8,9 Write BA E8H Write BA N 2 10,11 Write PA 40H or 10H Write PA PD SCS/BCS 2 9,10 Write BA 20H Write BA D0H Block Erase Suspend SCS/BCS 1 9,10 Write X B0H Block Erase Resume SCS/BCS 1 10 Write X D0H Configuration SCS 2 Write X B8H Write X CC Set Block Lock-Bit SCS 2 12 Write BA 60H Write BA 01H Clear Block LockBits SCS 2 13 Write X 60H Write X D0H 2 12,13 Write X 60H Write X F1H Set Master LockBit 16 5 6 PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT NOTES: 1. Bus operations are defined in Table 3. 2. X = Any valid address within the device. BA = Address within the block. IA = Identifier Code Address: see Figure 6 and Table 13. QA = Query database Address. PA = Address of memory location to be programmed. 3. ID = Data read from Identifier Codes. QD = Data read from Query database. SRD = Data read from status register. See Table 16 for a description of the status register bits. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#. CC = Configuration Code. 4. The upper byte of the data bus (DQ8–DQ15) during command writes is a “Don’t Care” in x16 operation. 5. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock codes. See Read Identifier Codes Command section for read identifier code data. 6. If the WSM is running, only DQ7 is valid; DQ15–DQ8 and DQ6–DQ0 float, which places them in a high-impedance state. 7. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing. 8. The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument. Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0000H to N = 000FH. The third and consecutive bus cycles, as determined by N, are for writing data into the Write Buffer. The Confirm command (D0H) is expected after exactly N + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. Please see Figure 7, Write to Buffer Flowchart, for additional information. 9. Programming the write buffer to flash or initiating the erase operation does not begin until a confirm command (D0h) is issued. 10. If the block is locked, RP# must be at VHH to enable block erase or program operations. Attempts to issue a block erase or program to a locked block while RP# is VIH will fail. 11. Either 40H or 10H are recognized by the WSM as the byte/word program setup. 12. If the master lock-bit is set, RP# must be at VHH to set a block lock-bit. RP# must be at VHH to set the master lock-bit. If the master lock-bit is not set, a block lock-bit can be set while RP# is VIH. 13. If the master lock-bit is set, RP# must be at VHH to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is VIH. 14. Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 15. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scaleable Command Set (SCS) is also referred to as the Intel Extended Command Set. PRELIMINARY 17 ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.1 Read Array Command Upon initial device power-up and after exit from reset/power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase, program, or lock-bit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend command. The Read Array command functions independently of the VPEN voltage and RP# can be VIH or VHH. 4.2 Read Query Mode Command This section defines the data structure or “database” returned by the SCS (Scaleable Command Set) Query command. System software should parse this structure to gain critical information to enable programming, block erases, and otherwise control the flash component. The SCS Query is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI. The Query can only be accessed when the WSM is off or the device is suspended. 4.2.1 E QUERY STRUCTURE OUTPUT The Query “database,” described later, allows system software to gain critical information for controlling the flash component. This section describes the device’s CFI-compliant interface that allows the host system to access Query data. Query data are always presented on the lowestorder data outputs DQ0–DQ7 only. The Query table device starting address is a 10h word address. The first two bytes of the Query structure, “Q” and ”R” in ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H data on upper bytes. Thus, the device outputs ASCII “Q” in the low byte DQ0–DQ7 and 00h in the high byte DQ8–DQ15. Since the device is x8/x16 capable, the x8 data is still presented in word-relative (16-bit) addresses. However, the “fill data” (00h) is not the same as driven by the upper bytes in the x16 mode. As in x16 mode, the byte address (A0 or A1 depending on pinout) is ignored for Query output so that the “odd byte address” (A0 or A1 high) repeats the “even byte address” data (A0 or A1 low). Therefore, in x8 mode using byte addressing, the device will output the sequence “Q,” “Q,” “R,” “R,” “Y,” “Y,” and so on, beginning at byte-relative address 20h (which is equivalent to word offset 10h in x16 mode). In Query addresses where two or more bytes of information are located, the least significant data byte is presented on the lower address, and the most significant data byte is presented on the higher address. 18 PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 5. Summary of Query Structure Output as a Function of Device and Mode Device type/ mode Query start location in maximum device bus width addresses x16 device/ x16 mode 10h x16 device/ x8 mode N/A(1) Query data with maximum device bus width addressing “x” = ASCII equivalent 10h: 0051h 11h: 0052h 12h: 0059h Query start address in bytes “Q” “R” “Y” N/A(1) Query data with byte addressing 20h 20h: 21h: 22h: 51h 00h 52h “Q” null “R” 20h 20h: 21h: 22h: 51h 51h 52h “Q” “Q” “R” NOTE: 1. The system must drive the lowest order addresses to access all the device’s array data when the device is configured in x8 mode. Therefore, word addressing where these lower addresses not toggled by the system is“Not Applicable” for x8configured devices. Table 6. Example of Query Structure Output of a x16- and x8-Capable Device Device Address Word Addressing: Query Data Byte Address Byte Addressing: Query Data A16–A1 D15–D0 A7–A0 D7–D0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h ... 0051h 0052h 0059h P_IDLO P_IDHI PLO PHI A_IDLO A_IDHI ... PRELIMINARY “Q” “R” “Y” PrVendor ID # PrVendor TblAdr AltVendor ID # 20h 21h 22h 23h 24h 25h 26h 27h 28h ... 51h 51h 52h 52h 59h 59h P_IDLO P_IDLO P_IDHI ... “Q” “Q” “R” “R” “Y” “Y” PrVendor ID # “ 19 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.2.2 QUERY STRUCTURE OVERVIEW The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or “database.” The structure sub-sections and address locations are summarized below. See AP646 Common Flash Interface (CFI) and Command Sets (order number 292204) for a full description of CFI. The following sections describe the Query structure sub-sections in detail. Table 7. Query Structure Offset Sub-Section Name Description 00h Manufacturer Code 01h Device Code (BA+2)h(2) Block Status Register Block-Specific Information Reserved Reserved for Vendor-Specific Information 10h CFI Query Identification String Command Set ID and Vendor Data Offset 1Bh System Interface Information Device Timing and Voltage Information 27h Device Geometry Definition Flash Device Layout P(3) Primary Vendor-Specific Extended Query table Vendor-Defined Additional Information Specific to the Primary Vendor Algorithm 04–0Fh NOTES: 1. Refer to Query Data Output section of Device Hardware interface for the detailed definition of offset address as a function of device word width and mode. 2. BA = The beginning location of a Block Address (i.e., 2000h is the beginning location of block 2 when the block size is 128 KB). 3. The Primary Vendor-Specific Extended Query table (P) address may change among SCS-compliant devices. Software should retrieve this address from address 15 to guarantee compatibility with future SCS-compliant devices. 20 PRELIMINARY E 4.2.3 ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT BLOCK STATUS REGISTER The Block Status Register indicates whether a given block is locked and can be accessed for program/erase operations. The Block Status Register is accessed from word address 02h within each block. Table 8. Block Status Register Offset Length (bytes) (BA +2)h1 01h Description Block Status Register BSR.0 = Block Lock Status (Optional) Intel® StrataFlash™ Memory x16 device/mode BA+2: 0000h or 0001h BA+2 (bit 0): 0 or 1 1 = Locked 0 = Unlocked BSR.1 = Block Erase Status (2) (Optional) 1 = Last erase operation did not complete successfully BA+2 (bit 1): 0 (The device does not support Block Erase Status) 0 = Last erase operation completed successfully BSR 2–7 Reserved for future use BA+2 (bits 2–7): 0 NOTES: 1. BA = The beginning location of a Block Address (i.e., 2000h is the beginning location of block 2). 2. Block Erase Status is an optional part of the SCS definition and is not incorporated on this device. PRELIMINARY 21 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.2.4 CFI QUERY IDENTIFICATION STRING The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which vendor-specified command set(s) is(are) supported. Table 9. CFI Identification 22 Offset Length (bytes) Description Intel® StrataFlash™ Memory 10h 03h Query-unique ASCII string “QRY“ 10: 11: 12: 0051h 0052h 0059h 13h 02h Primary Vendor Command Set and Control Interface ID Code 16-bit ID code for vendor-specified algorithms 13: 14: 0001h 0000h 15h 02h Address for Primary Algorithm Extended Query table Offset value = P = 31h 15: 16: 0031h 0000h 17h 02h Alternate Vendor Command Set and Control Interface ID Code second vendor-specified algorithm supported Note: 0000h means none exists 17: 18: 0000h 0000h 19h 02h Address for Secondary Algorithm Extended Query table Note: 0000h means none exists 19: 1A: 0000h 0000h PRELIMINARY E 4.2.5 ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT SYSTEM INTERFACE INFORMATION The following device information can optimize system interface software. Table 10. System Interface Information Offset Length (bytes) 1Bh 01h Description VCC Logic Supply Minimum Program/Erase voltage bits 7–4 bits 3–0 1Ch 01h 1Dh 01h 1Eh 01h 1C: 0055h 1D: 0000h 1E: 0000h HEX volts BCD 100 mv VPP [Programming] Supply Maximum Program/Erase voltage bits 7–4 bits 3–0 0045h BCD volts BCD 100 mv VPP [Programming] Supply Minimum Program/Erase voltage bits 7–4 bits 3–0 1B: BCD volts BCD 100 mv VCC Logic Supply Maximum Program/Erase voltage bits 7–4 bits 3–0 Intel® StrataFlash™ Memory HEX volts BCD 100 mv 1Fh 01h Typical time-out per single byte/word program, 2N µs 1F: 0007h 20h 01h Typical time-out for max. buffer write, 2N µs 20: 0007h 21h 01h Typical time-out per individual block erase, 2N ms 21: 000Ah 22h 01h Typical time-out for full chip erase, 2N ms (0000h = not supported) 22: 0000h 23h 01h Maximum time-out for byte/word program, 2N times typical 23: 0004h 24h 01h Maximum time-out for buffer write, 2N times typical 24: 0004h 25h 01h Maximum time-out per individual block erase, 2N times typical 25: 0004h 26h 01h Maximum time-out for chip erase, 2N times typical (00h = not supported) 26: 0000h PRELIMINARY 23 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 4.2.6 DEVICE GEOMETRY DEFINITION This field provides critical details of the flash device geometry. Table 11. Device Geometry Definition Offset Length (bytes) 27h 01h 28h 02h Description Device Size = 2N in number of bytes. Flash Device Interface description value meaning 0000h 0002h x8 asynchronous x8/x16 asynchronous Intel® StrataFlash™ Memory 27: 0017h (64-Mbit) 27: 0016h (32-Mbit) 28: 29: 0002h 0000h 2Ah 02h Maximum number of bytes in write buffer = 2 N 2A: 2B: 0005h 0000h 2Ch 01h Number of Erase Block Regions within device: 2C: 0001h bits 7–0 = x = # of Erase Block Regions 2Dh 04h Erase Block Region Information bits 15–0 = y, where y+1 = Number of Erase Blocks of identical size within region bits 31–16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes y: 64 Blocks (64-Mbit) 2D: 003Fh 2E: 0000h y: 32 Blocks (32-Mbit) 2D: 001Fh 2E: 0000h z: (128 KB size) 2F: 0000h 30: 0002h 24 PRELIMINARY E 4.2.7 ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT PRIMARY-VENDOR SPECIFIC EXTENDED QUERY TABLE Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query table specifies this and other similar information. Table 12. Primary Vendor-Specific Extended Query Offset(1) Length (bytes) (P)h 03h Primary extended Query table unique ASCII string “PRI” 31: 32: 33: 0050h 0052h 0049h (P +3)h 01h Major version number, ASCII 34: 0031 (P +4)h 01h Minor version number, ASCII 35: 0031 (P +5)h 04h Optional Feature and Command Support 36: 37: 38: 39: 000Ah 0000h 0000h 0000h 3A: 0001h 3B: 3C: 0001h 0000h bit 0 bit 1 bit 2 bit 3 bit 4 Chip Erase Supported Suspend Erase Supported Suspend Program Supported Lock/Unlock Supported Queued Erase Supported bits 5–31 (P +9)h 01h Intel® StrataFlash™ Memory Description (1=yes, 0=no) (1=yes, 0=no) (1=yes, 0=no) (1=yes, 0=no) (1=yes, 0=no) Reserved for future use; undefined bits are “0” Supported functions after Suspend Read Array, Status, and Query are always supported during suspended Erase. This field defines other operations supported. bit 0 Program supported after Erase Suspend (1=yes, 0=no) bits 1–7 (P +A)h 02h Reserved for future use; undefined bits are “0” Block Status Register Mask Defines which bits in the Block Status Register section of Query are implemented. bit 0 bit 1 Block Status Register Lock Bit [BSR.0] active (1=yes, 0=no) Block Status Register Valid Bit [BSR.1] active (1=yes, 0=no) bits 2–15 Reserved for future use; undefined bits are “0” NOTE: 1. The Primary Vendor-Specific Extended Query table (P) address may change among SCS-compliant devices. Software should retrieve this address from address 15 to guarantee compatibility with future SCS-compliant devices. PRELIMINARY 25 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 12. Primary Vendor-Specific Extended Query (Continued) Offset(1) Length (bytes) (P +C)h 01h VCC Optimum Program/Erase voltage (highest performance) bits 7–4 bits 3–0 (P +D)h 01h Intel® StrataFlash™ Memory Description 0050h 3E: 0000h BCD value in volts BCD value in 100 millivolts VPP [Programming] Optimum Program/Erase voltage bits 7–4 bits 3–0 3D: HEX value in volts BCD value in 100 millivolts Note: This value is 0000h; no VPP pin is present (P +E)h reserved Reserved for future use NOTE: 1. The Primary Vendor-Specific Extended Query table (P) address may change among SCS-compliant devices. Software should retrieve this address from address 15 to guarantee compatibility with future SCS-compliant devices. Table 13. Identifier Codes(1) 4.3 Read Identifier Codes Command The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 6 retrieve the manufacturer, device, block lock configuration and master lock configuration codes (see Table 13 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VPEN voltage and RP# can be VIH or VHH. This command is valid only when the WSM is off or the device is suspended. Following the Read Identifier Codes command, the following information can be read: 26 Code Address(1) Data Manufacture Code Device Code 32-Mbit 64-Mbit Block Lock Configuration • Block Is Unlocked • Block Is Locked • Reserved for Future Use Master Lock Configuration • Device Is Unlocked • Device Is Locked • Reserved for Future Use 00000 00001 00001 X0002(2) (00) 89 (00) 14 (00) 15 DQ0 = 0 DQ0 = 1 DQ1–7 00003 DQ0 = 0 DQ0 = 1 DQ1–7 NOTE: 1. A0 is not used in either x8 or x16 modes when obtaining the identifier codes. The lowest order address line is A1. Data is always presented on the low byte in x16 mode (upper byte contains 00h). 2. X selects the specific block’s lock configuration code. See Figure 6 for the device identifier code memory map. PRELIMINARY E 4.4 ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Read Status Register Command The status register may be read to determine when a block erase, program, or lock-bit configuration is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of OE# or the first edge of CE0, CE1, or CE2 that enables the device (see Table 2, Chip Enable Truth Table). OE# must toggle to VIH or the device must be disabled (see Table 2, Chip Enable Truth Table) before further reads to update the status register latch. The Read Status Register command functions independently of the VPEN voltage. RP# can be VIH or VHH. During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR.7 is valid until the Write State Machine completes or suspends the operation. Device I/O pins DQ0–DQ6 and DQ8– DQ15 are placed in a high-impedance state. When the operation completes or suspends (check Status Register bit 7), all contents of the Status Register are valid when read. 4.5 Clear Status Register Command Status register bits SR.5, SR.4, SR.3, and SR.1 are set to “1”s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 16). By allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VPEN voltage. RP# can be VIH or VHH. The Clear Status Register Command is only valid when the WSM is off or the device is suspended. PRELIMINARY 4.6 Block Erase Command Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires an appropriate address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 9). The CPU can detect block erase completion by analyzing the output of the STS pin or status register bit SR.7. Toggle OE#, CE0, CE1, or CE2 to update the status register. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to “1.” Also, reliable block erasure can only occur when VCC is valid and VPEN = VPENH. If block erase is attempted while VPEN ≤ VPENLK, SR.3 and SR.5 will be set to “1.” Successful block erase requires that the corresponding block lock-bit be cleared or, if set, that RP# = VHH. If block erase is attempted when the corresponding block lock-bit is set and RP# = VIH, SR.1 and SR.5 will be set to “1.” Block erase operations with VIH < RP# < VHH produce spurious results and should not be attempted. 4.7 Block Erase Suspend Command The Block Erase Suspend command allows block-erase interruption to read or program data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bit SR.7 then SR.6 can determine when the block erase operation has been suspended (both will be set to “1”). In default mode, STS will also transition to 27 ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT VOH. Specification tWHRH defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A program command sequence can also be issued during erase suspend to program data in other blocks. During a program operation with block erase suspended, status register bit SR.7 will return to “0” and the STS output (in default mode) will transition to VOL. The only other valid commands while block erase is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and STS (in default mode) will return to VOL. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 10). VPEN must remain at VPENH (the same VPEN level used for block erase) while block erase is suspended. RP# must also remain at VIH or VHH (the same RP# level used for block erase). Block erase cannot resume until program operations initiated during block erase suspend have completed. 4.8 Write to Buffer Command E Internally, this device programs many flash cells in parallel. Because of this parallel programming, maximum programming performance and lower power are obtained by aligning the start address at the beginning of a write buffer boundary (i.e., A4–A0 of the start address = 0). After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM (Write State Machine) to begin copying the buffer data to the flash array. If a command other than Write Confirm is written to the device, an “Invalid Command/Sequence” error will be generated and Status Register bits SR.5 and SR.4 will be set to a “1.” For additional buffer writes, issue another Write to Buffer setup command and check XSR.7. If an error occurs while writing, the device will stop writing, and Status Register bit SR.4 will be set to a “1” to indicate a program failure. The internal WSM verify only detects errors for “1”s that do not successfully program to “0”s. If a program error is detected, the status register should be cleared. Any time SR.4 and/or SR.5 is set (e.g., a media failure occurs during a program or an erase), the device will not accept any more Write to Buffer commands. Additionally, if the user attempts to program past an erase block boundary with a Write to Buffer command, the device will abort the Write to Buffer operation. This will generate an "Invalid Command/ Sequence" error and Status Register bits SR.5 and SR.4 will be set to a “1.” To program the flash device, a Write to Buffer command sequence is initiated. A variable number of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. First, the Write to Buffer setup command is issued along with the Block Address (see Figure 7, Write to Buffer Flowchart). At this point, the eXtended Status Register (XSR, see Table 17) information is loaded and XSR.7 reverts to "buffer available" status. If XSR.7 = 0, the write buffer is not available. To retry, continue monitoring XSR.7 by issuing the Write to Buffer setup command with the Block Address until XSR.7 = 1. When XSR.7 transitions to a “1,” the buffer is ready for loading. Reliable buffered writes can only occur when VPEN = VPENH. If a buffered write is attempted while VPEN ≤ VPENLK, Status Register bits SR.4 and SR.3 will be set to “1.” Buffered write attempts with invalid VCC and VPEN voltages produce spurious results and should not be attempted. Finally, successful programming requires that the corresponding Block Lock-Bit be reset or, if set, that RP# = VHH. If a buffered write is attempted when the corresponding Block Lock-Bit is set and RP# = VIH, SR.1 and SR.4 will be set to “1.” Buffered write operations with VIH < RP# < VHH produce spurious results and should not be attempted. Now a word/byte count is given to the part with the Block Address. On the next write, a device start address is given along with the write buffer data. Subsequent writes provide additional device addresses and data, depending on the count. All subsequent addresses must lie within the start address plus the count. 4.9 28 Byte/Word Program Commands Byte/Word program is executed by a two-cycle command sequence. Byte/Word program setup (standard 40H or alternate 10H) is written followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT then takes over, controlling the program and program verify algorithms internally. After the program sequence is written, the device automatically outputs status register data when read (see Figure 8). The CPU can detect the completion of the program event by analyzing the STS pin or status register bit SR.7. An invalid configuration code will result in both status register bits SR.4 and SR.5 being set to “1.” When configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns. 4.11 When program is complete, status register bit SR.4 should be checked. If a program error is detected, the status register should be cleared. The internal WSM verify only detects errors for “1”s that do not successfully program to “0”s. The CUI remains in read status register mode until it receives another command. Reliable byte/word programs can only occur when VCC and VPEN are valid. If a byte/word program is attempted while VPEN ≤ VPENLK, status register bits SR.4 and SR.3 will be set to “1.” Successful byte/word programs require that the corresponding block lock-bit be cleared or, if set, that RP# = VHH. If a byte/word program is attempted when the corresponding block lock-bit is set and RP# = VIH, SR.1 and SR.4 will be set to “1.” Byte/Word program operations with VIH < RP# < VHH produce spurious results and should not be attempted. 4.10 Configuration Command The Status (STS) pin can be configured to different states using the Configuration command. Once the STS pin has been configured, it remains in that configuration until another configuration command is issued or RP# is asserted low. Initially, the STS pin defaults to RY/BY# operation where RY/BY# low indicates that the state machine is busy. RY/BY# high indicates that the state machine is ready for a new operation or suspended. Table 15 displays the possible STS configurations. To reconfigure the Status (STS) pin to other modes, the Configuration command is given followed by the desired configuration code. The three alternate configurations are all pulse mode for use as a system interrupt as described below. For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 00h configuration code with the Configuration command resets the STS pin to the default RY/BY# level mode. The possible configurations and their usage are described in Table 15. The Configuration command may only be given when the device is not busy or suspended. Check SR.7 for device status. PRELIMINARY Set Block and Master Lock-Bit Commands A flexible block locking and unlocking scheme is enabled via a combination of block lock-bits and a master lock-bit. The block lock-bits gate program and erase operations while the master lock-bit gates block-lock bit modification. With the master lock-bit not set, individual block lock-bits can be set using the Set Block Lock-Bit command. The Set Master Lock-Bit command, in conjunction with RP# = VHH, sets the master lock-bit. After the master lock-bit is set, subsequent setting of block lock-bits requires both the Set Block Lock-Bit command and VHH on the RP# pin. These commands are invalid while the WSM is running or the device is suspended. See Table 14 for a summary of hardware and software write protection options. Set block lock-bit and master lock-bit commands are executed by a two-cycle sequence. The set block or master lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set master lock-bit confirm (and any device address). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Figure 11). The CPU can detect the completion of the set lock-bit event by analyzing the STS pin output or status register bit SR.7. When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block or Master Lock-Bit command will result in status register bits SR.4 and SR.5 being set to “1.” Also, reliable operations occur only when VCC and VPEN are valid. With VPEN ≤ VPENLK, lock-bit contents are protected against alteration. 29 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT A successful set block lock-bit operation requires that the master lock-bit be zero or, if the master lock-bit is set, that RP# = VHH. If it is attempted with the master lock-bit set and RP# = VIH, SR.1 and SR.4 will be set to “1” and the operation will fail. Set block lock-bit operations while VIH < RP# < VHH produce spurious results and should not be attempted. A successful set master lock-bit operation requires that RP# = VHH. If it is attempted with RP# = VIH, SR.1 and SR.4 will be set to “1” and the operation will fail. Set master lock-bit operations with VIH < RP# < VHH produce spurious results and should not be attempted. 4.12 Clear Block Lock-Bits Command All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. With the master lock-bit not set, block lock-bits can be cleared using only the Clear Block Lock-Bits command. If the master lock-bit is set, clearing block lock-bits requires both the Clear Block Lock-Bits command and VHH on the RP# pin. This command is invalid while the WSM is running or the device is suspended. See Table 14 for a summary of hardware and software write protection options. Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup is first written. The device automatically outputs status register data when read (see Figure 12). The CPU can detect completion of the clear block lock-bits event by analyzing the STS pin output or status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register bits SR.4 and SR.5 being set to “1.” Also, a reliable clear block lock-bits operation can only occur when VCC and VPEN are valid. If a clear block lock-bits operation is attempted while VPEN ≤ VPENLK, SR.3 and SR.5 will be set to “1.” A successful clear block lock-bits operation requires that the master lock-bit is not set or, if the master lock-bit is set, that RP# = VHH. If it is attempted with the master lock-bit set and RP# = VIH, SR.1 and SR.5 will be set to “1” and the operation will fail. A clear block lock-bits operation with VIH < RP# < VHH produce spurious results and should not be attempted. If a clear block lock-bits operation is aborted due to VPEN or VCC transitioning out of valid range or RP# active transition, block lock-bit values are left in an undetermined state. A repeat of clear block lockbits is required to initialize block lock-bit contents to known values. Once the master lock-bit is set, it cannot be cleared. Table 14. Write Protection Alternatives Operation Master Block Lock-Bit Lock-Bit Block Erase or Program X 0 1 Set or Clear Block Lock-Bit 0 1 X X Set Master Lock-Bit X X 30 RP# Effect VIH or VHH Block Erase and Program Enabled VIH Block is Locked. Block Erase and Program Disabled VHH Block Lock-Bit Override. Block Erase and Program Enabled VIH or VHH Set or Clear Block Lock-Bit Enabled VIH Master Lock-Bit Is Set. Set or Clear Block Lock-Bit Disabled VHH Master Lock-Bit Override. Set or Clear Block Lock-Bit Enabled VIH Set Master Lock-Bit Disabled VHH Set Master Lock-Bit Enabled PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 15. Configuration Coding Definitions Reserved Pulse On Program Complete(1) Pulse On Erase Complete(1) bits 7–2 bit 1 bit 0 DQ7–DQ2 = Reserved DQ7–DQ2 are reserved for future use. DQ1–DQ0 = STS Pin Configuration Codes default (DQ1–DQ0 = 00) RY/BY#, level mode — used to control HOLD to a memory controller to prevent accessing a flash memory subsystem while any flash device's WSM is busy. 00 = default, level mode RY/BY# (device ready) indication 01 = pulse on Erase complete 10 = pulse on Program complete configuration 01 ER INT, pulse mode — used to generate a system interrupt pulse when any flash device in an array has completed a Block 11 = pulse on Erase or Program Complete Erase or sequence of Queued Block Erases. Helpful for reformatting blocks after file system free space Configuration Codes 01b, 10b, and 11b are all pulse reclamation or “cleanup” mode such that the STS pin pulses low then high when the operation indicated by the given configuration 10 PR INT, pulse mode configuration is completed. — used to generate a system interrupt pulse when any flash device in an array has complete a Program Configuration Command Sequences for STS pin operation. Provides highest performance for servicing configuration (masking bits DQ7–DQ2 to 00h) are continuous buffer write operations. as follows: configuration 11 ER/PR INT, pulse mode Default RY/BY# level mode: B8h, 00h — used to generate system interrupts to trigger ER INT (Erase Interrupt): B8h, 01h servicing of flash arrays when either erase or Pulse-on-Erase Complete program operations are completed when a common PR INT (Program Interrupt): B8h, 02h interrupt service routine is desired. Pulse-on-Program Complete ER/PR INT (Erase or Program Interrupt): B8h, 03h Pulse-on-Erase or Program Complete NOTE: 1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns. PRELIMINARY 31 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 16. Status Register Definitions WSMS ESS ECLBS PSLBS VPENS R DPS R bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 High Z When Busy? Status Register Bits No SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy Yes SR.6 = ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed Yes Yes SR.5 = ERASE AND CLEAR LOCK-BITS STATUS 1 = Error in Block Erasure or Clear Lock-Bits 0 = Successful Block Erase or Clear Lock-Bits SR.4 = 1 = 0 = Yes SR.3 = 1 = Yes SR.2 = Yes SR.1 = 1 = 0 = 0 = Yes 32 NOTES: Check STS or SR.7 to determine block erase, program, or lock-bit configuration completion. SR.6–SR.0 are not driven while SR.7 = “0.” If both SR.5 and SR.4 are “1”s after a block erase or lock-bit configuration attempt, an improper command sequence was entered. SR.3 does not provide a continuous programming voltage level indication. The WSM interrogates and indicates the programming voltage level only after Block PROGRAM AND SET LOCK-BIT STATUS Erase, Program, Set Block/Master Lock-Bit, Error in Programming or Set Master/Block or Clear Block Lock-Bits command Lock-Bit sequences. Successful Programming or Set Master/Block Lock Bit SR.1 does not provide a continuous indication of master and block lock-bit PROGRAMMING VOLTAGE STATUS values. The WSM interrogates the master Low Programming Voltage Detected, lock-bit, block lock-bit, and RP# only after Operation Aborted Block Erase, Program, or Lock-Bit Programming Voltage OK configuration command sequences. It informs the system, depending on the RESERVED FOR FUTURE attempted operation, if the block lock-bit is ENHANCEMENTS set, master lock-bit is set, and/or RP# is not VHH. Read the block lock and master lock DEVICE PROTECT STATUS configuration codes using the Read Master Lock-Bit, Block Lock-Bit and/or Identifier Codes command to determine RP# Lock Detected, Operation Abort master and block lock-bit status. Unlock SR.0 = RESERVED FOR FUTURE ENHANCEMENTS SR.2 and SR.0 are reserved for future use and should be masked when polling the status register. PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Table 17. eXtended Status Register Definitions WBS Reserved bit 7 bits 6–0 High Z When Busy? Status Register Bits No XSR.7 = WRITE BUFFER STATUS 1 = Write buffer available 0 = Write buffer not available Yes XSR.6–XSR.0 = RESERVED FOR FUTURE ENHANCEMENTS PRELIMINARY NOTES: After a Buffer-Write command, XSR.7 = 1 indicates that a Write Buffer is available. SR.6–SR.0 are reserved for future use and should be masked when polling the status register. 33 ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Set Time-Out Issue Write to Buffer Command E8H, Block Address No Command Write Write to Buffer Comments Data = E8H Block Address XSR. 7 = Valid Addr = Block Address Read Read Extended Status Register Check XSR. 7 1 = Write Buffer Available 0 = Write Buffer Not Available Standby Write (Note 1, 2) Data = N = Word/Byte Count N = 0 Corresponds to Count = 1 Addr = Block Address Write (Note 3, 4) Data = Write Buffer Data Addr = Device Start Address Write Word or Byte Count, Block Address Write (Note 5, 6) Data = Write Buffer Data Addr = Device Address Write Buffer Data, Start Address Write XSR.7 = 0 Write to Buffer Time-Out? 1 X=0 Check X = N? Standby No Abort Write to Buffer Command? Program Buffer Data = D0H to Flash Addr = Block Address Confirm Read Yes Yes Bus Operation E Yes Yes Write to Another Block Address No Write to Buffer Aborted Write Next Buffer Data, Device Address X=X+1 Program Buffer to Flash Confirm D0H Status Register Data with the Device Enabled, OE# Low Updates SR Addr = Block Address Check SR.7 1 = WSM Ready 0 = WSM Busy 1. Byte or word count values on DQ 0-DQ 7 are loaded into the count register. Count ranges on this device for byte mode are N = 00H to 1FH and for word mode are N = 0000H to 000FH. 2. The device now outputs the status register when read (XSR is no longer available). 3. Write Buffer contents will be programmed at the device start address or destination flash address. 4. Align the start address on a Write Buffer boundary for maximum programming performance (i.e., A 4- A 0 of the start address = 0). 5. The device aborts the Write to Buffer command if the current address is outside of the original block address. 6. The status register indicates an "improper command sequence" if the Write to Buffer command is aborted. Follow this with a Clear Status Register command. Full status check can be done after all erase and write sequences complete. Write FFH after the last operation to reset the device to read array mode. Another Write to Buffer? Issue Read Status Command No Read Status Register SR.7 = 0 1 Full Status Check if Desired Programming Complete 0606_07 Figure 7. Write to Buffer Flowchart 34 PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Write 40H, Address Write Data and Address Bus Operation Command Comments Write Setup Byte/ Word Program Data = 40H Addr = Location to Be Programmed Write Byte/Word Program Data = Data to Be Programmed Addr = Location to Be Programmed Read Read Status Register Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Repeat for subsequent programming operations. 0 SR.7 = SR full status check can be done after each program operation, or after a sequence of programming operations. 1 Full Status Check if Desired Write FFH after the last program operation to place device in read array mode. Byte/Word Program Complete FULL STATUS CHECK PROCEDURE Bus Operation Read Status Register Data (See Above) Command Standby Check SR.3 1 = Programming to Voltage Error Detect Standby Check SR.1 1 = Device Protect Detect RP# = VIH, Block Lock-Bit Is Set Only required for systems implemeting lock-bit configuration. Standby Check SR.4 1 = Programming Error 1 SR.3 = Voltage Range Error 0 1 SR.1 = Device Protect Error 0 1 SR.4 = Programming Error 0 Comments SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are programmed before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. Byte/Word Program Successful 0606_08 Figure 8. Byte/Word Program Flowchart PRELIMINARY 35 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Bus Operation Command Write Erase Block Device Supports Queuing Check XSR.7 1 = Erase Queue Avail. 0 = No Erase Queue Avail. Yes Standby Set Time-Out Write No Erase Block Read Extended Status Register Standby Queued Erase Section (Include this section for compatibility with future SCS-compliant devices) Erase Block Time-Out? 0=No No Write (Note 1) 1=Yes Read Another Block Erase? Standby Yes Yes Issue Erase Command 28H Block Address Yes Erase Confirm Data = D0H Addr = X Status register data With the device enabled, OE# low updates SR Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy 1. The Erase Confirm byte must follow Erase Setup when the Erase Queue status (XSR.7) = 0. 1=No No Data = 28H Addr = Block Address SR.7 = Valid; SR.6 - 0 = X With the device enabled, OE# low updates SR Addr = X Check XSR.7 1 = Erase Queue Avail. 0 = No Erase Queue Avail. Read Is Queue Available? XSR.7= Data = 28H or 20H Addr = Block Address XSR.7 = Valid Addr = X Read Issue Block Queue Erase Command 28H, Block Address Comments Full status check can be done after all erase and write sequences complete. Write FFH after the last operation to reset the device to read array mode. Read Extended Status Register Issue Single Block Erase Command 20H, Block Address Is Queue Full? XSR.7= 0=Yes Write Confirm D0H Block Address Issue Read Status Command Write Confirm D0H Block Address Another Block Erase? No Read Status Register No 0 SR.7 = Suspend Erase Yes Suspend Erase Loop 1 Full Status Check if Desired Erase Flash Block(s) Complete 0606_09 Figure 9. Block Erase Flowchart 36 PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Bus Operation Command Write Erase Suspend Write B0H 0 Data = B0H Addr = X Status Register Data Addr = X Read Read Status Register Comments Standby Check SR.7 1 - WSM Ready 0 = WSM Busy Standby Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed SR.7 = Write Erase Resume Data = D0H Addr = X 1 0 SR.6 = Block Erase Completed 1 Read Program Read or Program? Read Array Data Program Loop No Done? Yes Write D0H Write FFH Block Erase Resumed Read Array Data 0606_10 Figure 10. Block Erase Suspend/Resume Flowchart PRELIMINARY 37 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Bus Operation Command Comments Write 60H, Block/Device Address Write Set Block/Master Lock-Bit Setup Data = 60H Addr =Block Address (Block), Device Address (Master) Write 01H/F1H, Block/Device Address Write Set Block or Master Lock-Bit Confirm Data = 01H (Block) F1H (Master) Addr = Block Address (Block), Device Address (Master) Read Read Status Register Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy Standby 0 SR.7 = Repeat for subsequent lock-bit operations. 1 Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations Full Status Check if Desired Write FFH after the last lock-bit set operation to place device in read array mode. Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Bus Operation Read Status Register Data (See Above) 1 SR.3 = 0 Standby Check SR.1 1 = Device Protect RP# = VIH (Set Master Lock-Bit Operation) RP# = VIH, Master Lock-Bit Is Set (set Block Lock-Bit Operation) Standby Check SR.4, 5 Both 1 = Command Sequence Error Standby Check SR.4 1 = Set Lock-Bit Error Device Protect Error 1 SR.4,5 = Command Sequence Error 0 1 0 Check SR.3 1 = Programming Voltage Error Detect 1 0 Set Lock-Bit Error Comments Standby Voltage Range Error SR. 1 = SR.4 = Command SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command, in cases where multiple lock-bits are set before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. Set Lock-Bit Successful 0606_11 Figure 11. Set Block Lock-Bit Flowchart 38 PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Start Write 60H Bus Operation Command Write Clear Block Lock-Bits Setup Data = 60H Addr = X Write Clear Block or Lock-Bits Confirm Data = D0H Addr = X Write D0H Read Status Register Data Read Status Register Check SR.7 1 = WSM Ready 0 = WSM Busy Standby 0 SR.7 = Comments Write FFH after the clear lock-bits operation to place device in read array mode. 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Bus Operation Read Status Register Data (See Above) 1 SR.3 = 0 Command Standby Check SR.3 1 = Programming Voltage Error Detect Standby Check SR.1 1 = Device Protect RP# = VIH, Master Lock-Bit Is Set Standby Check SR.4, 5 Both 1 = Command Sequence Error Standby Check SR.5 1 = Clear Block Lock-Bits Error Voltage Range Error 1 SR. 1 = Device Protect Error 0 1 SR.4,5 = Command Sequence Error 0 1 SR.5 = Clear Block Lock-Bits Error Comments SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command. If an error is detected, clear the status register before attempting retry or other error recovery. 0 Clear Block Lock-Bits Successful 0606_12 Figure 12. Clear Block Lock-Bit Flowchart PRELIMINARY 39 ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 5.0 DESIGN CONSIDERATIONS 5.1 5.3 Three-Line Output Control The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1, CE2, OE#, and RP#) to accommodate multiple memory connections. This control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that contention will not occur. data bus To use these control inputs efficiently, an address decoder should enable the device (see Table 2, Chip Enable Truth Table) while OE# should be connected to all memory devices and the system’s READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. 5.2 STS and Block Erase, Program, and Lock-Bit Configuration Polling STS is an open drain output that should be connected to VCCQ by a pull-up resistor to provide a hardware method of detecting block erase, program, and lock-bit configuration completion. In default mode, it transitions low after block erase, program, or lock-bit configuration commands and returns to High Z when the WSM has finished executing the internal algorithm. For alternate configurations of the STS pin, see the Configuration command. STS can be connected to an interrupt input of the system CPU or controller. It is active at all times. STS, in default mode, is also High Z when the device is in block erase suspend (with programming inactive) or in reset/power-down mode. 40 E Power Supply Decoupling Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of CE0, CE1, CE2, and OE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Since Intel StrataFlash memory devices draw their power from three VCC pins (these devices do not include a VPP pin), it is recommended that systems without separate power and ground planes attach a 0.1 µF ceramic capacitor between each of the device’s three VCC pins (this includes VCCQ) and ground. These high-frequency, low-inductance capacitors should be placed as close as possible to package leads on each StrataFlash device. Each device should have a 0.1 µF ceramic capacitor connected between its VCC and GND. These high-frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed between VCC and GND at the array’s power supply connection. The bulk capacitor will overcome voltage slumps caused by PC board trace inductance. 5.4 VCC, VPEN, RP# Transitions Block erase, program, and lock-bit configuration are not guaranteed if VPEN or VCC falls outside of the specified operating ranges, or RP# ≠ VIH or VHH. If RP# transitions to VIL during block erase, program, or lock-bit configuration, STS (in default mode) will remain low for a maximum time of tPLPH + tPHRH until the reset operation is complete. Then, the operation will abort and the device will enter reset/power-down mode. The aborted operation may leave data partially corrupted after programming, or partially altered after an erase or lock-bit configuration. Therefore, block erase and lock-bit configuration commands must be repeated after normal operation is restored. Device power-off or RP# = VIL clears the status register. PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT The CUI latches commands issued by system software and is not altered by VPEN, CE0, CE1, or CE2 transitions, or WSM actions. Its state is read array mode upon power-up, after exit from reset/power-down mode, or after VCC transitions below VLKO. VCC must be kept at or above VPEN during VCC transitions. A system designer must guard against spurious writes for VCC voltages above VLKO when VPEN is active. Since WE# must be low and the device enabled (see Table 2, Chip Enable Truth Table) for a command write, driving WE# to VIH or disabling the device will inhibit writes. The CUI’s two-step command sequence architecture provides added protection against data alteration. After block erase, program, or lock-bit configuration, even after VPEN transitions down to VPENLK, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. VPEN must be kept at or below VCC during VPEN transitions. Keeping VPEN below VPENLK prevents inadvertent data alteration. In-system block lock and unlock capability protects the device against inadvertent programming. The device is disabled while RP# = VIL regardless of its control inputs. 5.5 5.6 Power-Up/Down Protection The device is designed to offer protection against accidental block erasure, programming, or lock-bit configuration during power transitions. Internal circuitry resets the CUI to read array mode at power-up. PRELIMINARY Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory’s nonvolatility increases usable battery life because data is retained when system power is removed. 41 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 6.0 ELECTRICAL SPECIFICATIONS 6.1 NOTICE: This datasheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. Absolute Maximum Ratings* Temperature under Bias Expanded .............................. –20 °C to +70 °C *WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. Storage Temperature................. –65 °C to +125 °C Voltage On Any Pin (except RP#) ............................................ –2.0 V to +7.0 V (1) RP# Voltage with Respect to GND during Lock-Bit Configuration Operations–2.0 V to +14.0 V(1,2,3) Output Short Circuit Current.....................100 mA(4) NOTES: 1. All specified voltages are with respect to GND. Minimum DC voltage is –0.5 V on input/output pins and –0.2 V on VCC and VPEN pins. During transitions, this level may undershoot to –2.0 V for periods <20 ns. Maximum DC voltage on input/output pins, VCC, and VPEN is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. 2. Maximum DC voltage on RP# may overshoot to +14.0 V for periods <20 ns. 3. RP# voltage is normally at VIL or VIH. Connection to supply of VHH is allowed for a maximum cumulative period of 80 hours. 4. Output shorted for no more than one second. No more than one output shorted at a time. 6.2 Operating Conditions Temperature and VCC Operating Conditions Symbol Parameter Notes Min Max Unit TA Operating Temperature –20 +70 °C VCC VCC1 Supply Voltage (5 V ± 10%) 4.50 5.50 V VCCQ1 VCCQ1 Supply Voltage (5 V ± 10%) 4.50 5.50 V VCCQ2 VCCQ2 Supply Voltage (2. 7V−3.6 V) 2.70 3.60 V Test Condition Ambient Temperature Capacitance(1) 6.3 TA = +25°C, f = 1 MHz Typ Max Unit CIN Symbol Input Capacitance Parameter 6 8 pF VIN = 0.0 V Condition COUT Output Capacitance 8 12 pF VOUT = 0.0 V NOTE: 1. Sampled, not 100% tested. 42 PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 6.4 DC Characteristics Sym Parameter Notes Typ Max Unit Test Conditions ILI Input and VPEN Load Current 1 ±1 µA VCC = VCC Max VIN = VCC or GND ILO Output Leakage Current 1 ±10 µA VCC = VCC Max VIN = VCC or GND ICCS VCC Standby Current 80 150 µA CMOS Inputs, VCC = VCC Max, CE0 = CE1 = CE2 = RP# = VCCQ1 ± 0.2 V 450 900 µA CMOS Inputs, RP# = V CC = VCC Max, CE0 = CE1 = CE2 = VCCQ2 Min 325 650 µA CMOS Inputs, RP# = V CC = VCC Max, CE2 = GND, CE0 = CE1 = VCCQ2 Min 210 400 µA CMOS Inputs, RP# = V CC = VCC Max, CE1 = CE2 = GND, CE0 = VCCQ2 Min or CE0 = CE2 = GND, CE1 = VCCQ2 Min 0.71 2 mA TTL Inputs, VCC = VCC Max, CE0 = CE1 = CE2 = RP# = VIH 80 125 µA RP# = GND ± 0.2V IOUT (STS) = 0 mA 35 55 mA CMOS Inputs, VCC = VCCQ =VCC Max Device is enabled (see Table 2, Chip Enable Truth Table) f = 5 MHz IOUT = 0 mA 45 65 mA TTL Inputs ,VCC = VCC Max Device is enabled (see Table 2, Chip Enable Truth Table) f = 5 MHz IOUT = 0 mA 35 60 mA CMOS Inputs, VPEN = VCC 40 70 mA TTL Inputs, VPEN = VCC 35 70 mA CMOS Inputs, VPEN = VCC ICCD VCC Power-Down Current ICCR VCC Read Current ICCW VCC Program or Set 1,3,5 1,5,6 1,6,7 Lock-Bit Current ICCE VCC Block Erase or Clear Block Lock-Bits 1,6,7 Current ICCES VCC Block Erase Suspend Current PRELIMINARY 40 1,2 80 mA TTL Inputs, VPEN = VCC 10 mA Device is disabled (see Table 2, Chip Enable Truth Table) 43 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 6.4 DC Characteristics (Continued) Sym Parameter Notes Min Max Unit Test Conditions VIL Input Low Voltage 7 –0.5 0.8 V VIH Input High Voltage 7 2.0 VCC + 0.5 V VOL Output Low Voltage 3,7 0.45 V VCCQ = VCCQ1 Min IOL = 5.8 mA 0.4 V VCCQ = VCCQ2 Min IOL = 2 mA VOH1 Output High Voltage (TTL) 3,7 2.4 V VCCQ = VCCQ1 Min or VCCQ = VCCQ2 Min IOH = –2.5 mA (VCCQ1) –2 mA (VCCQ2) VOH2 Output High Voltage (CMOS) 3,7 0.85 VCCQ V VCCQ = VCCQ1 Min or VCCQ = VCCQ2 Min IOH = –2.5 mA VCCQ –0.4 V VCCQ = VCCQ1 Min or VCCQ = VCCQ2 Min IOH = –100 µA V VPENLK VPEN Lockout during Normal Operations 4,7,11 3.6 VPENH VPEN during Block Erase, Program, or Lock-Bit Operations 4,11 4.5 VLKO VCC Lockout Voltage 8 3.25 VHH RP# Unlock Voltage 9,10 11.4 5.5 V V 12.6 V Set master lock-bit Override lock-bit NOTES: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact Intel’s Application Support Hotline or your local sales office for information about typical specifications. 2. ICCES is specified with the device de-selected. If the device is read or written while in erase suspend mode, the device’s current draw is ICCR or ICCW. 3. Includes STS. 4. Block erases, programming, and lock-bit configurations are inhibited when VPEN ≤ VPENLK, and not guaranteed in the range between VPENLK (max) and VPENH (min), and above VPENH (max). 5. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH. 6. Add 5 mA for VCCQ = VCCQ2 min. 7. Sampled, not 100% tested. 8. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO, and not guaranteed in the range between VLKO (min) and VCC (min), and above VCC (max). 9. Master lock-bit set operations are inhibited when RP# = VIH. Block lock-bit configuration operations are inhibited when the master lock-bit is set and RP# = VIH. Block erases and programming are inhibited when the corresponding block-lock bit is set and RP# = VIH. Block erase, program, and lock-bit configuration operations are not guaranteed and should not be attempted with VIH < RP# < VHH. 10. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours. 11. Tie VPEN to VCC (4.5 V–5.5 V). 44 PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 2.4 2.0 Input 2.0 Output 0.8 Test Points 0.8 0.45 AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns. Figure 13. Transient Input/Output Reference Waveform for VCCQ = 5.0 V ± 10% (Standard Testing Configuration) 2.7 Input 1.35 Test Points 1.35 Output 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35 V (50% of VCCQ). Input rise and fall times (10% to 90%) <10 ns. Figure 14. Transient Input/Output Reference Waveform for VCCQ = 2.7 V−3.6 V Test Configuration Capacitance Loading Value 1.3V Test Configuration 1N914 CL (pF) VCCQ = 5.0 V ± 10% 100 VCCQ = 2.7 V−3.6 V 50 RL = 3.3 kΩ Device Under Test Out CL NOTE: CL Includes Jig Capacitance Figure 15. Transient Equivalent Testing Load Circuit PRELIMINARY 45 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT AC Characteristics—Read-Only Operations(1) 6.5 Versions 5 V ± 10% VCCQ –100/–150(4) –120(4) (All units in ns unless otherwise noted) 2.7 V—3.6V VCCQ –100/–150(4) –120(4) # Sym R1 tAVAV R2 R3 tAVQV tELQV Parameter Read/Write Cycle Time Address to Output Delay CEX to Output Delay R4 tGLQV OE# to Output Delay R5 tPHQV RP# High to Output Delay Notes Min 32 Mbit 100 64 Mbit 150 Max Min Max 120 32 Mbit 100 64 Mbit 150 120 32 Mbit 2 100 120 64 Mbit 2 150 2 50 50 32 Mbit 180 180 64 Mbit 210 R6 tELQX CEX to Output in Low Z 3 0 0 R7 tGLQX OE# to Output in Low Z 3 0 0 R8 tEHQZ CEX High to Output in High Z 3 55 55 R9 tGHQZ OE# High to Output in High Z 3 15 15 R10 tOH Output Hold from Address, CEX, or OE# Change, Whichever Occurs First 3 R11 tELFL tELFH CEX Low to BYTE# High or Low 3 R12 tFLQV tFHQV BYTE# to Output Delay R13 tFLQZ BYTE# to Output in High Z 3 R14 tEHEL CEx Pulse width 3 0 10 0 10 10 1000 1000 1000 1000 10 NOTES: CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2, Chip Enable Truth Table). 1. See Figure 16, AC Waveform for Read Operations for the maximum allowable input slew rate. 2. OE# may be delayed up to tELQV-tGLQV after the first edge of CE0, CE1, or CE2 that enables the device (see Table 2, Chip Enable Truth Table) without impact on tELQV. 3. Sampled, not 100% tested. 4. See Figures 13–15, Transient Input/Output Reference Waveform for VCCQ = 5.0 V ±10%, Transient Input/Output Reference Waveform for VCCQ = 2.7 V –3.6 V, and Transient Equivalent Testing Load Circuit for testing characteristics. 46 PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Standby Device Address Selection Data Valid VIH ADDRESSES [A] Address Stable VIL R1 Disabled (VIH) R14 CEX [E] Enabled (VIL) OE# [G] VIL WE# [W] R9 R3 VIH VIL DATA [D/Q] VOH DQ0-DQ15 R4 R10 R5 High Z R6 Valid Output VOL VCC R8 R2 VIH High Z R7 VIH VIL VIH RP# [P] VIL R11 R12 R13 VIH BYTE# [F] VIL 0606_16 NOTES: CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2, Chip Enable Truth Table). Figure 16. AC Waveform for Read Operations PRELIMINARY 47 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT AC Characteristics— Write Operations(1,2) 6.6 Valid for All Speeds Versions # Sym Parameter Notes Min Max Unit W1 tPHWL (tPHEL) RP# High Recovery to WE# (CEX ) Going Low 3 1 µs W2 tELWL (tWLEL) CEX (WE#) Low to WE# (CEX) Going Low 8 0 ns W3 tWP Write Pulse Width 8 70 ns W4 tDVWH (tDVEH) Data Setup to WE# (CEX ) Going High 4 50 ns W5 tAVWH (tAVEH) Address Setup to WE# (CEX ) Going High 4 50 ns W6 tWHEH (tEHWH) CEX (WE#) Hold from WE# (CEX) High 10 ns W7 tWHDX (tEHDX) Data Hold from WE# (CEX ) High 0 ns W8 tWHAX (tEHAX) Address Hold from WE# (CEX ) High 0 ns W9 tWPH Write Pulse Width High 9 30 ns W10 tPHHWH (tPHHEH) RP# VHH Setup to WE# (CEX ) Going High 3 0 ns W11 tVPWH (tVPEH) VPEN Setup to WE# (CEX ) Going High 3 0 ns W12 tWHGL (tEHGL) Write Recovery before Read 6 35 ns W13 tWHRL (tEHRL) WE# (CEX ) High to STS Going Low 5 W14 tQVPH RP# VHH Hold from Valid SRD, STS Going High 3,5,7 0 ns W15 tQVVL VPEN Hold from Valid SRD, STS Going High 3,5,7 0 ns 90 ns NOTES: CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2, Chip Enable Truth Table). 1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics–Read-Only Operations. 2. A write operation can be initiated and terminated with either CEX or WE#. 3. Sampled, not 100% tested. 4. Refer to Table 4 for valid AIN and DIN for block erase, program, or lock-bit configuration. 5. STS timings are based on STS configured in its RY/BY# default mode. 6. For array access, tAVQV is required in addition to tWHGL for any accesses after a write. 7. VPEN should be held at VPENH (and if necessary RP# should be held at VHH) until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0). 8. Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low first) to CEX or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. If CEX is driven low 10 ns before WE# going low, WE# pulse width requirement decreases to tWP - 10 ns. 9. Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 48 PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT A ADDRESSES [A] VIH VIL B C AIN AIN W5 Disabled (V IH) CEX, (WE#) [E(W)] Enabled (V IL) VIL W6 W2 DATA [D/Q] VIL W16 W3 W4 VIH F W12 W9 Disabled (V IH) WE#, (CEX) [W(E)] Enabled (V IL) E W8 W1 VIH OE# [G] D High Z W7 DIN Valid SRD DIN DIN W13 VOH STS [R] VOL W10 W14 W11 W15 VHH RP# [P] VIH VIL VPENH VPENLK VPEN [V] VIL 0606_17 NOTES: CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 2, Chip Enable Truth Table). STS is shown in its default mode (RY/BY#). 1. VCC power-up and standby. 2. Write block erase, write buffer, or program setup. 3. Write block erase or write buffer confirm, or valid address and data. 4. Automated erase delay. 5. Read status register or query data. 6. Write Read Array command. Figure 17. AC Waveform for Write Operations PRELIMINARY 49 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT STS (R) VIH VIL P2 RP# (P) VIH VIL P1 0606_18 NOTES: STS is shown in its default mode (RY/BY#). Figure 18. AC Waveform for Reset Operation Reset Specifications(1) Sym. Parameter Notes Min P1 # tPLPH RP# Pulse Low Time (If RP# is tied to VCC, this specification is not applicable) 2 35 P2 tPHRH RP# High to Reset during Block Erase, Program, or Lock-Bit Configuration 3 Max Unit µs 100 ns NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum required RP# Pulse Low Time is 100 ns. 3. A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid. 50 PRELIMINARY E 6.7 # ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT Block Erase, Program, and Lock-Bit Configuration Performance(3,4) Notes Min Typ(1) Max Unit Write Buffer Byte Program Time 2,5 TBD 6.3 TBD µs Write Buffer Word Program Time 2,5 TBD 12.6 TBD µs Byte Program Time (Using Word/Byte Program Command) Block Program Time (Using Write to Buffer Command) Block Erase Time 2 TBD 180 TBD µs 2 TBD 0.8 TBD sec 2 TBD 0.7 TBD sec Set Lock-Bit Time 2 TBD 32 TBD µs Clear Block Lock-Bits Time 2 TBD 0.3 TBD sec 26 TBD µs Sym W16 tWHQV1 tEHQV1 W16 tWHQV2 tEHQV2 W16 tWHQV3 tEHQV3 W16 tWHQV4 tEHQV4 W16 tWHQV5 tEHQV5 W16 tWHQV6 tEHQV6 W16 tWHRH tEHRH Parameter Erase Suspend Latency Time to Read NOTES: 1. Typical values measured at TA = +25 °C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. These performance numbers are valid for all speed versions. 4. Sampled but not 100% tested. 5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary. PRELIMINARY 51 E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 7.0 ORDERING INFORMATION G2 8 F 6 4 0 J 5 - 1 5 0 Package G = 56-Ball µBGA* CSP E = 56-Lead TSOP DA = 56-Lead SSOP Access Speed (ns) (100, 120, 150) Product line designator for all Intel® Flash products Voltage (VCC/VPEN) 5 = 5 V/5 V Device Density 640 = x8/x16 (64 Mbit) 320 = x8/x16 (32 Mbit) Product Family J = Intel® StrataFlashTM memory, 2 bits-per-cell Valid Operational Conditions Order Code by Density 32 Mbit DA28F320J5-100 DA28F320J5-120 E28F320J5-100 E28F320J5-120 5 V VCC 64 Mbit DA28F640J5-150 G28F640J5-150 52 2.7 V – 3.6 V VCCQ 5 V ± 10% VCCQ Yes Yes Yes Yes Yes Yes PRELIMINARY E ® INTEL StrataFlash™ MEMORY TECHNOLOGY, 32 AND 64 MBIT 8.0 ADDITIONAL INFORMATION (1,2) Order Number Document 210830 Flash Memory Databook 292123 AP-374 Flash Memory Write Protection Techniques 292203 AP-644 Intel® StrataFlash™ Memory Migration Guide 292204 AP-646 Common Flash Interface (CFI) and Command Sets 292205 AP-647 Intel® StrataFlash™ Memory Design Guide 297848 Intel® StrataFlash™ Memory 32 and 64 Mbit Specification Update NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.intel.com for technical documentation and tools. PRELIMINARY 53